ARM: rename ARMV4_5_STATE_* as ARM_STATE_*
[openocd/ztw.git] / src / target / armv4_5_cache.c
blobdcbcef3a131947d2ca0941b61244f0d96aac1c45
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
24 #include "armv4_5_cache.h"
25 #include <helper/log.h>
27 int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common *cache)
29 int size, assoc, M, len, multiplier;
31 cache->ctype = (cache_type_reg & 0x1e000000U) >> 25;
32 cache->separate = (cache_type_reg & 0x01000000U) >> 24;
34 size = (cache_type_reg & 0x1c0000) >> 18;
35 assoc = (cache_type_reg & 0x38000) >> 15;
36 M = (cache_type_reg & 0x4000) >> 14;
37 len = (cache_type_reg & 0x3000) >> 12;
38 multiplier = 2 + M;
40 if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */
42 /* cache is present */
43 cache->d_u_size.linelen = 1 << (len + 3);
44 cache->d_u_size.associativity = multiplier << (assoc - 1);
45 cache->d_u_size.nsets = 1 << (size + 6 - assoc - len);
46 cache->d_u_size.cachesize = multiplier << (size + 8);
48 else
50 /* cache is absent */
51 cache->d_u_size.linelen = -1;
52 cache->d_u_size.associativity = -1;
53 cache->d_u_size.nsets = -1;
54 cache->d_u_size.cachesize = -1;
57 if (cache->separate)
59 size = (cache_type_reg & 0x1c0) >> 6;
60 assoc = (cache_type_reg & 0x38) >> 3;
61 M = (cache_type_reg & 0x4) >> 2;
62 len = (cache_type_reg & 0x3);
63 multiplier = 2 + M;
65 if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */
67 /* cache is present */
68 cache->i_size.linelen = 1 << (len + 3);
69 cache->i_size.associativity = multiplier << (assoc - 1);
70 cache->i_size.nsets = 1 << (size + 6 - assoc - len);
71 cache->i_size.cachesize = multiplier << (size + 8);
73 else
75 /* cache is absent */
76 cache->i_size.linelen = -1;
77 cache->i_size.associativity = -1;
78 cache->i_size.nsets = -1;
79 cache->i_size.cachesize = -1;
82 else
84 cache->i_size = cache->d_u_size;
87 return ERROR_OK;
90 int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx, struct armv4_5_cache_common *armv4_5_cache)
92 if (armv4_5_cache->ctype == -1)
94 command_print(cmd_ctx, "cache not yet identified");
95 return ERROR_OK;
98 command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
99 (armv4_5_cache->separate) ? "separate caches" : "unified cache");
101 command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
102 armv4_5_cache->d_u_size.linelen,
103 armv4_5_cache->d_u_size.associativity,
104 armv4_5_cache->d_u_size.nsets,
105 armv4_5_cache->d_u_size.cachesize);
107 command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
108 armv4_5_cache->i_size.linelen,
109 armv4_5_cache->i_size.associativity,
110 armv4_5_cache->i_size.nsets,
111 armv4_5_cache->i_size.cachesize);
113 return ERROR_OK;