src/flash/mflash.h

   1 /***************************************************************************
   2  *   Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com>             *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 #ifndef _MFLASH_H
  21 #define _MFLASH_H
  22
  23 struct command_context;
  24
  25 typedef unsigned long mg_io_uint32;
  26 typedef unsigned short mg_io_uint16;
  27 typedef unsigned char mg_io_uint8;
  28
  29 struct mflash_gpio_num
  30 {
  31         char port[2];
  32         signed short num;
  33 };
  34
  35 struct mflash_gpio_drv
  36 {
  37         const char *name;
  38         int (*set_gpio_to_output) (struct mflash_gpio_num gpio);
  39         int (*set_gpio_output_val) (struct mflash_gpio_num gpio, uint8_t val);
  40 };
  41
  42 typedef struct _mg_io_type_drv_info {
  43
  44         mg_io_uint16 general_configuration;                             /* 00 */
  45         mg_io_uint16 number_of_cylinders;                               /* 01 */
  46         mg_io_uint16 reserved1;                                                 /* 02 */
  47         mg_io_uint16 number_of_heads;                                   /* 03 */
  48         mg_io_uint16 unformatted_bytes_per_track;               /* 04 */
  49         mg_io_uint16 unformatted_bytes_per_sector;              /* 05 */
  50         mg_io_uint16 sectors_per_track;                                 /* 06 */
  51         mg_io_uint16  vendor_unique1[3];                                /* 07/08/09 */
  52
  53         mg_io_uint8  serial_number[20];                                 /* 10~19 */
  54
  55         mg_io_uint16 buffer_type;                                               /* 20 */
  56         mg_io_uint16 buffer_sector_size;                                /* 21 */
  57         mg_io_uint16 number_of_ecc_bytes;                               /* 22 */
  58
  59         mg_io_uint8  firmware_revision[8];                              /* 23~26 */
  60         mg_io_uint8  model_number[40];                                  /* 27 */
  61
  62         mg_io_uint8  maximum_block_transfer;                    /* 47 low byte */
  63         mg_io_uint8  vendor_unique2;                                    /* 47 high byte */
  64         mg_io_uint16 dword_io;                                                  /* 48 */
  65
  66         mg_io_uint16 capabilities;                                              /* 49 */
  67         mg_io_uint16 reserved2;                                                 /* 50 */
  68
  69         mg_io_uint8  vendor_unique3;                                    /* 51 low byte */
  70         mg_io_uint8  pio_cycle_timing_mode;                             /* 51 high byte */
  71         mg_io_uint8  vendor_unique4;                                    /* 52 low byte */
  72         mg_io_uint8  dma_cycle_timing_mode;                             /* 52 high byte */
  73         mg_io_uint16 translation_fields_valid;                  /* 53 (low bit) */
  74         mg_io_uint16 number_of_current_cylinders;               /* 54 */
  75         mg_io_uint16 number_of_current_heads;                   /* 55 */
  76         mg_io_uint16 current_sectors_per_track;                 /* 56 */
  77         mg_io_uint16 current_sector_capacity_lo;                /* 57 & 58 */
  78         mg_io_uint16 current_sector_capacity_hi;                /* 57 & 58 */
  79         mg_io_uint8  multi_sector_count;                                /* 59 low */
  80         mg_io_uint8  multi_sector_setting_valid;                /* 59 high (low bit) */
  81
  82         mg_io_uint16 total_user_addressable_sectors_lo; /* 60 & 61 */
  83         mg_io_uint16 total_user_addressable_sectors_hi; /* 60 & 61 */
  84
  85         mg_io_uint8  single_dma_modes_supported;                /* 62 low byte */
  86         mg_io_uint8  single_dma_transfer_active;                /* 62 high byte */
  87         mg_io_uint8  multi_dma_modes_supported;                 /* 63 low byte */
  88         mg_io_uint8  multi_dma_transfer_active;                 /* 63 high byte */
  89         mg_io_uint16 adv_pio_mode;
  90         mg_io_uint16 min_dma_cyc;
  91         mg_io_uint16 recommend_dma_cyc;
  92         mg_io_uint16 min_pio_cyc_no_iordy;
  93         mg_io_uint16 min_pio_cyc_with_iordy;
  94         mg_io_uint8  reserved3[22];
  95         mg_io_uint16 major_ver_num;
  96         mg_io_uint16 minor_ver_num;
  97         mg_io_uint16 feature_cmd_set_suprt0;
  98         mg_io_uint16 feature_cmd_set_suprt1;
  99         mg_io_uint16 feature_cmd_set_suprt2;
 100         mg_io_uint16 feature_cmd_set_en0;
 101         mg_io_uint16 feature_cmd_set_en1;
 102         mg_io_uint16 feature_cmd_set_en2;
 103         mg_io_uint16 reserved4;
 104         mg_io_uint16 req_time_for_security_er_done;
 105         mg_io_uint16 req_time_for_enhan_security_er_done;
 106         mg_io_uint16 adv_pwr_mgm_lvl_val;
 107         mg_io_uint16 reserved5;
 108         mg_io_uint16 re_of_hw_rst;
 109         mg_io_uint8  reserved6[68];
 110         mg_io_uint16 security_stas;
 111         mg_io_uint8  vendor_uniq_bytes[62];
 112         mg_io_uint16 cfa_pwr_mode;
 113         mg_io_uint8  reserved7[186];
 114
 115         mg_io_uint16 scts_per_secure_data_unit;
 116         mg_io_uint16 integrity_word;
 117
 118 } mg_io_type_drv_info;
 119
 120 typedef struct _mg_pll_t
 121 {
 122         unsigned int   lock_cyc;
 123         unsigned short feedback_div;    /* 9bit divider */
 124         unsigned char  input_div;       /* 5bit divider */
 125         unsigned char  output_div;      /* 2bit divider */
 126 } mg_pll_t;
 127
 128 struct mg_drv_info {
 129         mg_io_type_drv_info drv_id;
 130         uint32_t tot_sects;
 131 };
 132
 133 struct mflash_bank
 134 {
 135         uint32_t base;
 136
 137         struct mflash_gpio_num rst_pin;
 138
 139         struct mflash_gpio_drv *gpio_drv;
 140         struct target *target;
 141         struct mg_drv_info *drv_info;
 142 };
 143
 144 int mflash_register_commands(struct command_context *cmd_ctx);
 145
 146 #define MG_MFLASH_SECTOR_SIZE           (0x200)         /* 512Bytes = 2^9 */
 147 #define MG_MFLASH_SECTOR_SIZE_MASK      (0x200-1)
 148 #define MG_MFLASH_SECTOR_SIZE_SHIFT     (9)
 149
 150 #define MG_BUFFER_OFFSET        0x8000
 151 #define MG_REG_OFFSET           0xC000
 152 #define MG_REG_FEATURE          0x2             /* write case */
 153 #define MG_REG_ERROR            0x2             /* read case */
 154 #define MG_REG_SECT_CNT         0x4
 155 #define MG_REG_SECT_NUM         0x6
 156 #define MG_REG_CYL_LOW          0x8
 157 #define MG_REG_CYL_HIGH         0xA
 158 #define MG_REG_DRV_HEAD         0xC
 159 #define MG_REG_COMMAND          0xE             /* write case */
 160 #define MG_REG_STATUS           0xE             /* read  case */
 161 #define MG_REG_DRV_CTRL         0x10
 162 #define MG_REG_BURST_CTRL       0x12
 163
 164 #define MG_OEM_DISK_WAIT_TIME_LONG              15000   /* msec */
 165 #define MG_OEM_DISK_WAIT_TIME_NORMAL    3000    /* msec */
 166 #define MG_OEM_DISK_WAIT_TIME_SHORT             1000    /* msec */
 167
 168 #define MG_PLL_CLK_OUT 66000000.0 /* 66Mhz */
 169 #define MG_PLL_MAX_FEEDBACKDIV_VAL 512
 170 #define MG_PLL_MAX_INPUTDIV_VAL 32
 171 #define MG_PLL_MAX_OUTPUTDIV_VAL 4
 172
 173 #define MG_PLL_STD_INPUTCLK 12000000.0 /* 12Mhz */
 174 #define MG_PLL_STD_LOCKCYCLE 10000
 175
 176 #define MG_UNLOCK_OTP_AREA 0xFF
 177
 178 #define MG_FILEIO_CHUNK 1048576
 179
 180 #define ERROR_MG_IO (-1600)
 181 #define ERROR_MG_TIMEOUT (-1601)
 182 #define ERROR_MG_INVALID_PLL (-1603)
 183 #define ERROR_MG_INTERFACE (-1604)
 184 #define ERROR_MG_INVALID_OSC (-1605)
 185 #define ERROR_MG_UNSUPPORTED_SOC (-1606)
 186
 187 typedef enum _mg_io_type_wait{
 188
 189         mg_io_wait_bsy       = 1,
 190         mg_io_wait_not_bsy   = 2,
 191         mg_io_wait_rdy       = 3,
 192         mg_io_wait_drq       = 4,       /* wait for data request */
 193         mg_io_wait_drq_noerr = 5,       /* wait for DRQ but ignore the error status bit */
 194         mg_io_wait_rdy_noerr = 6        /* wait for ready, but ignore error status bit */
 195
 196 } mg_io_type_wait;
 197
 198 /*= "Status Register" bit masks. */
 199 typedef enum _mg_io_type_rbit_status{
 200
 201         mg_io_rbit_status_error            = 0x01, /* error bit in status register */
 202         mg_io_rbit_status_corrected_error  = 0x04, /* corrected error in status register */
 203         mg_io_rbit_status_data_req         = 0x08, /* data request bit in status register */
 204         mg_io_rbit_status_seek_done        = 0x10, /* DSC - Drive Seek Complete */
 205         mg_io_rbit_status_write_fault      = 0x20, /* DWF - Drive Write Fault */
 206         mg_io_rbit_status_ready            = 0x40,
 207         mg_io_rbit_status_busy             = 0x80
 208
 209 } mg_io_type_rbit_status;
 210
 211 /*= "Error Register" bit masks. */
 212 typedef enum _mg_io_type_rbit_error{
 213
 214         mg_io_rbit_err_general          = 0x01,
 215         mg_io_rbit_err_aborted          = 0x04,
 216         mg_io_rbit_err_bad_sect_num     = 0x10,
 217         mg_io_rbit_err_uncorrectable    = 0x40,
 218         mg_io_rbit_err_bad_block        = 0x80
 219
 220 } mg_io_type_rbit_error;
 221
 222 /* = "Device Control Register" bit. */
 223 typedef enum _mg_io_type_rbit_devc{
 224
 225         mg_io_rbit_devc_intr      = 0x02,       /* interrupt enable bit (1:disable, 0:enable) */
 226         mg_io_rbit_devc_srst      = 0x04        /* softwrae reset bit (1:assert, 0:de-assert) */
 227
 228 } mg_io_type_rbit_devc;
 229
 230 /* "Drive Select/Head Register" values. */
 231 typedef enum _mg_io_type_rval_dev{
 232
 233         mg_io_rval_dev_must_be_on      =   0x80, /* These 1 bits are always on */
 234         mg_io_rval_dev_drv_master      =  (0x00 | mg_io_rval_dev_must_be_on), /* Master */
 235         mg_io_rval_dev_drv_slave0      =  (0x10 | mg_io_rval_dev_must_be_on), /* Slave0 */
 236         mg_io_rval_dev_drv_slave1      =  (0x20 | mg_io_rval_dev_must_be_on), /* Slave1 */
 237         mg_io_rval_dev_drv_slave2      =  (0x30 | mg_io_rval_dev_must_be_on), /* Slave2 */
 238         mg_io_rval_dev_lba_mode        =  (0x40 | mg_io_rval_dev_must_be_on)
 239
 240 } mg_io_type_rval_dev;
 241
 242 typedef enum _mg_io_type_cmd
 243 {
 244         mg_io_cmd_read             =0x20,
 245         mg_io_cmd_write            =0x30,
 246
 247         mg_io_cmd_setmul           =0xC6,
 248         mg_io_cmd_readmul          =0xC4,
 249         mg_io_cmd_writemul         =0xC5,
 250
 251         mg_io_cmd_idle             =0x97, /* 0xE3 */
 252         mg_io_cmd_idle_immediate   =0x95, /* 0xE1 */
 253
 254         mg_io_cmd_setsleep         =0x99, /* 0xE6 */
 255         mg_io_cmd_stdby            =0x96, /* 0xE2 */
 256         mg_io_cmd_stdby_immediate  =0x94, /* 0xE0 */
 257
 258         mg_io_cmd_identify         =0xEC,
 259         mg_io_cmd_set_feature      =0xEF,
 260
 261         mg_io_cmd_confirm_write    =0x3C,
 262         mg_io_cmd_confirm_read     =0x40,
 263         mg_io_cmd_wakeup           =0xC3
 264
 265 } mg_io_type_cmd;
 266
 267 typedef enum _mg_feature_id
 268 {
 269         mg_feature_id_transmode = 0x3
 270 } mg_feature_id;
 271
 272 typedef enum _mg_feature_val
 273 {
 274         mg_feature_val_trans_default = 0x0,
 275         mg_feature_val_trans_vcmd = 0x3,
 276         mg_feature_val_trand_vcmds = 0x2
 277 } mg_feature_val;
 278
 279 typedef enum _mg_vcmd
 280 {
 281         mg_vcmd_update_xipinfo = 0xFA, /* FWPATCH commmand through IOM I/O */
 282         mg_vcmd_verify_fwpatch = 0xFB, /* FWPATCH commmand through IOM I/O */
 283         mg_vcmd_update_stgdrvinfo = 0xFC, /* IOM identificatin info program command */
 284         mg_vcmd_prep_fwpatch = 0xFD, /* FWPATCH commmand through IOM I/O */
 285         mg_vcmd_exe_fwpatch = 0xFE, /* FWPATCH commmand through IOM I/O */
 286         mg_vcmd_wr_pll = 0x8B,
 287         mg_vcmd_purge_nand = 0x8C, /* Only for  Seagle */
 288         mg_vcmd_lock_otp = 0x8D,
 289         mg_vcmd_rd_otp = 0x8E,
 290         mg_vcmd_wr_otp = 0x8F
 291 } mg_vcmd;
 292
 293 typedef enum _mg_opmode
 294 {
 295         mg_op_mode_xip = 1, /* TRUE XIP */
 296         mg_op_mode_snd = 2, /* BOOT + Storage */
 297         mg_op_mode_stg = 0  /* Only Storage */
 298 } mg_opmode;
 299
 300 #endif