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kinetis auto mass erase on secured devices
[openocd/ntfreak.git] / src / target / arm_adi_v5.c
blob21dc54cd3d2ccd7ddf779690ba5b2f857fb08fe6
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "arm.h"
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
75
76
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
78
79 /*
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 */
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 {
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
86 }
87
88 /***************************************************************************
89 * *
90 * DP and MEM-AP register access through APACC and DPACC *
91 * *
92 ***************************************************************************/
93
94 /**
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
98 *
99 * @param dap The DAP
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
102 */
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t ap)
104 {
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
106
107 if (new_ap != dap->ap_current)
108 {
109 dap->ap_current = new_ap;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 */
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
116 }
117 }
118
119 /**
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
122 *
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
127 *
128 * @todo Rename to reflect it being specifically a MEM-AP function.
129 *
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
135 *
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 */
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
139 {
140 int retval;
141
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
144 {
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
148 return retval;
149 dap->ap_csw_value = csw;
150 }
151 if (tar != dap->ap_tar_value)
152 {
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
156 return retval;
157 dap->ap_tar_value = tar;
158 }
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
162 return ERROR_OK;
163 }
164
165 /**
166 * Asynchronous (queued) read of a word from memory or a system register.
167 *
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
173 *
174 * @return ERROR_OK for success. Otherwise a fault code.
175 */
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
177 uint32_t *value)
178 {
179 int retval;
180
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
183 */
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
187 return retval;
188
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
190 }
191
192 /**
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
195 *
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
200 *
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
203 */
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
205 uint32_t *value)
206 {
207 int retval;
208
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
211 return retval;
212
213 return dap_run(dap);
214 }
215
216 /**
217 * Asynchronous (queued) write of a word to memory or a system register.
218 *
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
224 *
225 * @return ERROR_OK for success. Otherwise a fault code.
226 */
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
228 uint32_t value)
229 {
230 int retval;
231
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
234 */
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
238 return retval;
239
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
241 value);
242 }
243
244 /**
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
247 *
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
252 *
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
254 */
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
256 uint32_t value)
257 {
258 int retval = mem_ap_write_u32(dap, address, value);
259
260 if (retval != ERROR_OK)
261 return retval;
262
263 return dap_run(dap);
264 }
265
266 /*****************************************************************************
267 * *
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
269 * *
270 * Write a buffer in target order (little endian) *
271 * *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
274 {
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 const uint8_t* pBuffer = buffer;
278
279 count >>= 2;
280 wcount = count;
281
282 /* if we have an unaligned access - reorder data */
283 if (adr & 0x3u)
284 {
285 for (writecount = 0; writecount < count; writecount++)
286 {
287 int i;
288 uint32_t outvalue;
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
290
291 for (i = 0; i < 4; i++)
292 {
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
294 outvalue >>= 8;
295 adr++;
296 }
297 pBuffer += sizeof(uint32_t);
298 }
299 }
300
301 while (wcount > 0)
302 {
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
306 blocksize = wcount;
307
308 /* handle unaligned data at 4k boundary */
309 if (blocksize == 0)
310 blocksize = 1;
311
312 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
313 if (retval != ERROR_OK)
314 return retval;
315
316 for (writecount = 0; writecount < blocksize; writecount++)
317 {
318 retval = dap_queue_ap_write(dap, AP_REG_DRW,
319 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
320 if (retval != ERROR_OK)
321 break;
322 }
323
324 if ((retval = dap_run(dap)) == ERROR_OK)
325 {
326 wcount = wcount - blocksize;
327 address = address + 4 * blocksize;
328 buffer = buffer + 4 * blocksize;
329 }
330 else
331 {
332 errorcount++;
333 }
334
335 if (errorcount > 1)
336 {
337 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
338 return retval;
339 }
340 }
341
342 return retval;
343 }
344
345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
346 const uint8_t *buffer, int count, uint32_t address)
347 {
348 int retval = ERROR_OK;
349 int wcount, blocksize, writecount, i;
350
351 wcount = count >> 1;
352
353 while (wcount > 0)
354 {
355 int nbytes;
356
357 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
358 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
359
360 if (wcount < blocksize)
361 blocksize = wcount;
362
363 /* handle unaligned data at 4k boundary */
364 if (blocksize == 0)
365 blocksize = 1;
366
367 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
368 if (retval != ERROR_OK)
369 return retval;
370 writecount = blocksize;
371
372 do
373 {
374 nbytes = MIN((writecount << 1), 4);
375
376 if (nbytes < 4)
377 {
378 retval = mem_ap_write_buf_u16(dap, buffer,
379 nbytes, address);
380 if (retval != ERROR_OK)
381 {
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32 ", count 0x%x",
384 address, count);
385 return retval;
386 }
387
388 address += nbytes >> 1;
389 }
390 else
391 {
392 uint32_t outvalue;
393 memcpy(&outvalue, buffer, sizeof(uint32_t));
394
395 for (i = 0; i < nbytes; i++)
396 {
397 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
398 outvalue >>= 8;
399 address++;
400 }
401
402 memcpy(&outvalue, buffer, sizeof(uint32_t));
403 retval = dap_queue_ap_write(dap,
404 AP_REG_DRW, outvalue);
405 if (retval != ERROR_OK)
406 break;
407
408 if ((retval = dap_run(dap)) != ERROR_OK)
409 {
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32 ", count 0x%x",
412 address, count);
413 return retval;
414 }
415 }
416
417 buffer += nbytes >> 1;
418 writecount -= nbytes >> 1;
419
420 } while (writecount);
421 wcount -= blocksize;
422 }
423
424 return retval;
425 }
426
427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
428 {
429 int retval = ERROR_OK;
430
431 if (count >= 4)
432 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
433
434 while (count > 0)
435 {
436 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
437 if (retval != ERROR_OK)
438 return retval;
439 uint16_t svalue;
440 memcpy(&svalue, buffer, sizeof(uint16_t));
441 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
442 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
443 if (retval != ERROR_OK)
444 break;
445
446 retval = dap_run(dap);
447 if (retval != ERROR_OK)
448 break;
449
450 count -= 2;
451 address += 2;
452 buffer += 2;
453 }
454
455 return retval;
456 }
457
458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
459 const uint8_t *buffer, int count, uint32_t address)
460 {
461 int retval = ERROR_OK;
462 int wcount, blocksize, writecount, i;
463
464 wcount = count;
465
466 while (wcount > 0)
467 {
468 int nbytes;
469
470 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
471 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
472
473 if (wcount < blocksize)
474 blocksize = wcount;
475
476 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
477 if (retval != ERROR_OK)
478 return retval;
479 writecount = blocksize;
480
481 do
482 {
483 nbytes = MIN(writecount, 4);
484
485 if (nbytes < 4)
486 {
487 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
488 if (retval != ERROR_OK)
489 {
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32 ", count 0x%x",
492 address, count);
493 return retval;
494 }
495
496 address += nbytes;
497 }
498 else
499 {
500 uint32_t outvalue;
501 memcpy(&outvalue, buffer, sizeof(uint32_t));
502
503 for (i = 0; i < nbytes; i++)
504 {
505 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
506 outvalue >>= 8;
507 address++;
508 }
509
510 memcpy(&outvalue, buffer, sizeof(uint32_t));
511 retval = dap_queue_ap_write(dap,
512 AP_REG_DRW, outvalue);
513 if (retval != ERROR_OK)
514 break;
515
516 if ((retval = dap_run(dap)) != ERROR_OK)
517 {
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32 ", count 0x%x",
520 address, count);
521 return retval;
522 }
523 }
524
525 buffer += nbytes;
526 writecount -= nbytes;
527
528 } while (writecount);
529 wcount -= blocksize;
530 }
531
532 return retval;
533 }
534
535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
536 {
537 int retval = ERROR_OK;
538
539 if (count >= 4)
540 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
541
542 while (count > 0)
543 {
544 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
545 if (retval != ERROR_OK)
546 return retval;
547 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
548 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
549 if (retval != ERROR_OK)
550 break;
551
552 retval = dap_run(dap);
553 if (retval != ERROR_OK)
554 break;
555
556 count--;
557 address++;
558 buffer++;
559 }
560
561 return retval;
562 }
563
564 /* FIXME don't import ... this is a temporary workaround for the
565 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
566 */
567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
568 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
569 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
570
571 /**
572 * Synchronously read a block of 32-bit words into a buffer
573 * @param dap The DAP connected to the MEM-AP.
574 * @param buffer where the words will be stored (in host byte order).
575 * @param count How many words to read.
576 * @param address Memory address from which to read words; all the
577 * words must be readable by the currently selected MEM-AP.
578 */
579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
580 int count, uint32_t address)
581 {
582 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
583 uint32_t adr = address;
584 uint8_t* pBuffer = buffer;
585
586 count >>= 2;
587 wcount = count;
588
589 while (wcount > 0)
590 {
591 /* Adjust to read blocks within boundaries aligned to the
592 * TAR autoincrement size (at least 2^10). Autoincrement
593 * mode avoids an extra per-word roundtrip to update TAR.
594 */
595 blocksize = max_tar_block_size(dap->tar_autoincr_block,
596 address);
597 if (wcount < blocksize)
598 blocksize = wcount;
599
600 /* handle unaligned data at 4k boundary */
601 if (blocksize == 0)
602 blocksize = 1;
603
604 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
605 address);
606 if (retval != ERROR_OK)
607 return retval;
608
609 /* FIXME remove these three calls to adi_jtag_dp_scan(),
610 * so this routine becomes transport-neutral. Be careful
611 * not to cause performance problems with JTAG; would it
612 * suffice to loop over dap_queue_ap_read(), or would that
613 * be slower when JTAG is the chosen transport?
614 */
615
616 /* Scan out first read */
617 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
618 DPAP_READ, 0, NULL, NULL);
619 if (retval != ERROR_OK)
620 return retval;
621 for (readcount = 0; readcount < blocksize - 1; readcount++)
622 {
623 /* Scan out next read; scan in posted value for the
624 * previous one. Assumes read is acked "OK/FAULT",
625 * and CTRL_STAT says that meant "OK".
626 */
627 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
628 DPAP_READ, 0, buffer + 4 * readcount,
629 &dap->ack);
630 if (retval != ERROR_OK)
631 return retval;
632 }
633
634 /* Scan in last posted value; RDBUFF has no other effect,
635 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
636 */
637 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
638 DPAP_READ, 0, buffer + 4 * readcount,
639 &dap->ack);
640 if (retval != ERROR_OK)
641 return retval;
642
643 retval = dap_run(dap);
644 if (retval != ERROR_OK)
645 {
646 errorcount++;
647 if (errorcount <= 1)
648 {
649 /* try again */
650 continue;
651 }
652 LOG_WARNING("Block read error address 0x%" PRIx32, address);
653 return retval;
654 }
655 wcount = wcount - blocksize;
656 address += 4 * blocksize;
657 buffer += 4 * blocksize;
658 }
659
660 /* if we have an unaligned access - reorder data */
661 if (adr & 0x3u)
662 {
663 for (readcount = 0; readcount < count; readcount++)
664 {
665 int i;
666 uint32_t data;
667 memcpy(&data, pBuffer, sizeof(uint32_t));
668
669 for (i = 0; i < 4; i++)
670 {
671 *((uint8_t*)pBuffer) =
672 (data >> 8 * (adr & 0x3));
673 pBuffer++;
674 adr++;
675 }
676 }
677 }
678
679 return retval;
680 }
681
682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
683 uint8_t *buffer, int count, uint32_t address)
684 {
685 uint32_t invalue;
686 int retval = ERROR_OK;
687 int wcount, blocksize, readcount, i;
688
689 wcount = count >> 1;
690
691 while (wcount > 0)
692 {
693 int nbytes;
694
695 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
696 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
697 if (wcount < blocksize)
698 blocksize = wcount;
699
700 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
701 if (retval != ERROR_OK)
702 return retval;
703
704 /* handle unaligned data at 4k boundary */
705 if (blocksize == 0)
706 blocksize = 1;
707 readcount = blocksize;
708
709 do
710 {
711 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
712 if (retval != ERROR_OK)
713 return retval;
714 if ((retval = dap_run(dap)) != ERROR_OK)
715 {
716 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
717 return retval;
718 }
719
720 nbytes = MIN((readcount << 1), 4);
721
722 for (i = 0; i < nbytes; i++)
723 {
724 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
725 buffer++;
726 address++;
727 }
728
729 readcount -= (nbytes >> 1);
730 } while (readcount);
731 wcount -= blocksize;
732 }
733
734 return retval;
735 }
736
737 /**
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
744 */
745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
746 int count, uint32_t address)
747 {
748 uint32_t invalue, i;
749 int retval = ERROR_OK;
750
751 if (count >= 4)
752 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
753
754 while (count > 0)
755 {
756 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
757 if (retval != ERROR_OK)
758 return retval;
759 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
760 if (retval != ERROR_OK)
761 break;
762
763 retval = dap_run(dap);
764 if (retval != ERROR_OK)
765 break;
766
767 if (address & 0x1)
768 {
769 for (i = 0; i < 2; i++)
770 {
771 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
772 buffer++;
773 address++;
774 }
775 }
776 else
777 {
778 uint16_t svalue = (invalue >> 8 * (address & 0x3));
779 memcpy(buffer, &svalue, sizeof(uint16_t));
780 address += 2;
781 buffer += 2;
782 }
783 count -= 2;
784 }
785
786 return retval;
787 }
788
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
791 *
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
794 */
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
796 uint8_t *buffer, int count, uint32_t address)
797 {
798 uint32_t invalue;
799 int retval = ERROR_OK;
800 int wcount, blocksize, readcount, i;
801
802 wcount = count;
803
804 while (wcount > 0)
805 {
806 int nbytes;
807
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
810
811 if (wcount < blocksize)
812 blocksize = wcount;
813
814 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
815 if (retval != ERROR_OK)
816 return retval;
817 readcount = blocksize;
818
819 do
820 {
821 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
822 if (retval != ERROR_OK)
823 return retval;
824 if ((retval = dap_run(dap)) != ERROR_OK)
825 {
826 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
827 return retval;
828 }
829
830 nbytes = MIN(readcount, 4);
831
832 for (i = 0; i < nbytes; i++)
833 {
834 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
835 buffer++;
836 address++;
837 }
838
839 readcount -= nbytes;
840 } while (readcount);
841 wcount -= blocksize;
842 }
843
844 return retval;
845 }
846
847 /**
848 * Synchronously read a block of bytes into a buffer
849 * @param dap The DAP connected to the MEM-AP.
850 * @param buffer where the bytes will be stored.
851 * @param count How many bytes to read.
852 * @param address Memory address from which to read data; all the
853 * data must be readable by the currently selected MEM-AP.
854 */
855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
856 int count, uint32_t address)
857 {
858 uint32_t invalue;
859 int retval = ERROR_OK;
860
861 if (count >= 4)
862 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
863
864 while (count > 0)
865 {
866 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
867 if (retval != ERROR_OK)
868 return retval;
869 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
870 if (retval != ERROR_OK)
871 return retval;
872 retval = dap_run(dap);
873 if (retval != ERROR_OK)
874 break;
875
876 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
877 count--;
878 address++;
879 buffer++;
880 }
881
882 return retval;
883 }
884
885 /*--------------------------------------------------------------------*/
886 /* Wrapping function with selection of AP */
887 /*--------------------------------------------------------------------*/
888 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
889 uint32_t address, uint32_t *value)
890 {
891 dap_ap_select(swjdp, ap);
892 return mem_ap_read_u32(swjdp, address, value);
893 }
894
895 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
896 uint32_t address, uint32_t value)
897 {
898 dap_ap_select(swjdp, ap);
899 return mem_ap_write_u32(swjdp, address, value);
900 }
901
902 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
903 uint32_t address, uint32_t *value)
904 {
905 dap_ap_select(swjdp, ap);
906 return mem_ap_read_atomic_u32(swjdp, address, value);
907 }
908
909 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
910 uint32_t address, uint32_t value)
911 {
912 dap_ap_select(swjdp, ap);
913 return mem_ap_write_atomic_u32(swjdp, address, value);
914 }
915
916 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
917 uint8_t *buffer, int count, uint32_t address)
918 {
919 dap_ap_select(swjdp, ap);
920 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
921 }
922
923 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
924 uint8_t *buffer, int count, uint32_t address)
925 {
926 dap_ap_select(swjdp, ap);
927 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
928 }
929
930 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
931 uint8_t *buffer, int count, uint32_t address)
932 {
933 dap_ap_select(swjdp, ap);
934 return mem_ap_read_buf_u32(swjdp, buffer, count, address);
935 }
936
937 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
938 const uint8_t *buffer, int count, uint32_t address)
939 {
940 dap_ap_select(swjdp, ap);
941 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
942 }
943
944 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
945 const uint8_t *buffer, int count, uint32_t address)
946 {
947 dap_ap_select(swjdp, ap);
948 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
949 }
950
951 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
952 const uint8_t *buffer, int count, uint32_t address)
953 {
954 dap_ap_select(swjdp, ap);
955 return mem_ap_write_buf_u32(swjdp, buffer, count, address);
956 }
957
958 #define MDM_REG_STAT 0x00
959 #define MDM_REG_CTRL 0x04
960 #define MDM_REG_ID 0xfc
961
962 #define MDM_STAT_FMEACK (1<<0)
963 #define MDM_STAT_FREADY (1<<1)
964 #define MDM_STAT_SYSSEC (1<<2)
965 #define MDM_STAT_SYSRES (1<<3)
966 #define MDM_STAT_FMEEN (1<<5)
967 #define MDM_STAT_BACKDOOREN (1<<6)
968 #define MDM_STAT_LPEN (1<<7)
969 #define MDM_STAT_VLPEN (1<<8)
970 #define MDM_STAT_LLSMODEXIT (1<<9)
971 #define MDM_STAT_VLLSXMODEXIT (1<<10)
972 #define MDM_STAT_CORE_HALTED (1<<16)
973 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
974 #define MDM_STAT_CORESLEEPING (1<<18)
975
976 #define MEM_CTRL_FMEIP (1<<0)
977 #define MEM_CTRL_DBG_DIS (1<<1)
978 #define MEM_CTRL_DBG_REQ (1<<2)
979 #define MEM_CTRL_SYS_RES_REQ (1<<3)
980 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
981 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
982 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
983 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
984
985 /**
986 *
987 */
988 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
989 {
990 uint32_t val;
991 int retval;
992 enum reset_types jtag_reset_config = jtag_get_reset_config();
993
994 dap_ap_select(dap, 1);
995
996 /* first check mdm-ap id register */
997 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
998 if (retval != ERROR_OK)
999 return retval;
1000 dap_run(dap);
1001
1002 if ( val != 0x001C0000 )
1003 {
1004 LOG_DEBUG("id doesn't match %08X != 0x001C0000",val);
1005 dap_ap_select(dap, 0);
1006 return ERROR_FAIL;
1007 }
1008
1009 /* read and parse status register
1010 * it's important that the device is out of
1011 * reset here
1012 */
1013 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1014 if (retval != ERROR_OK)
1015 return retval;
1016 dap_run(dap);
1017
1018 LOG_DEBUG("MDM_REG_STAT %08X",val);
1019
1020 if ( (val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY) )
1021 {
1022 LOG_DEBUG("MDMAP: system is secured, masserase needed");
1023
1024 if ( !(val & MDM_STAT_FMEEN) )
1025 {
1026 LOG_DEBUG("MDMAP: masserase is disabled");
1027 }
1028 else
1029 {
1030 /* we need to assert reset */
1031 if ( jtag_reset_config & RESET_HAS_SRST )
1032 {
1033 /* default to asserting srst */
1034 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1035 {
1036 jtag_add_reset(1, 1);
1037 }
1038 else
1039 {
1040 jtag_add_reset(0, 1);
1041 }
1042 }
1043 else
1044 {
1045 LOG_DEBUG("SRST not configured");
1046 dap_ap_select(dap, 0);
1047 return ERROR_FAIL;
1048 }
1049
1050 while(1)
1051 {
1052 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
1053 if (retval != ERROR_OK)
1054 return retval;
1055 dap_run(dap);
1056 /* read status register and wait for ready */
1057 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1058 if (retval != ERROR_OK)
1059 return retval;
1060 dap_run(dap);
1061 LOG_DEBUG("MDM_REG_STAT %08X",val);
1062
1063 if ( (val&1))
1064 break;
1065 }
1066
1067 while(1)
1068 {
1069 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1070 if (retval != ERROR_OK)
1071 return retval;
1072 dap_run(dap);
1073 /* read status register */
1074 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1075 if (retval != ERROR_OK)
1076 return retval;
1077 dap_run(dap);
1078 LOG_DEBUG("MDM_REG_STAT %08X",val);
1079 /* read control register and wait for ready */
1080 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1081 if (retval != ERROR_OK)
1082 return retval;
1083 dap_run(dap);
1084 LOG_DEBUG("MDM_REG_CTRL %08X",val);
1085
1086 if ( val == 0x00 )
1087 break;
1088 }
1089 }
1090 }
1091
1092 dap_ap_select(dap, 0);
1093
1094 return ERROR_OK;
1095 }
1096
1097 /** */
1098 struct dap_syssec_filter {
1099 /** */
1100 uint32_t idcode;
1101 /** */
1102 int (*dap_init)(struct adiv5_dap *dap);
1103 };
1104
1105 /** */
1106 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1107 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1108 };
1109
1110
1111 /**
1112 *
1113 */
1114 int dap_syssec(struct adiv5_dap *dap)
1115 {
1116 unsigned int i;
1117 struct jtag_tap *tap;
1118
1119 for(i=0;i<sizeof(dap_syssec_filter_data);i++)
1120 {
1121 tap = dap->jtag_info->tap;
1122
1123 while (tap != NULL)
1124 {
1125 if (!tap->hasidcode)
1126 continue;
1127 if ( dap_syssec_filter_data[i].idcode == tap->idcode )
1128 {
1129 LOG_DEBUG("DAP: mdmap_init for idcode: %08x",tap->idcode);
1130 dap_syssec_filter_data[i].dap_init(dap);
1131 }
1132 tap = tap->next_tap;
1133 }
1134 }
1135
1136 return ERROR_OK;
1137 }
1138
1139 /*--------------------------------------------------------------------------*/
1140
1141
1142 /* FIXME don't import ... just initialize as
1143 * part of DAP transport setup
1144 */
1145 extern const struct dap_ops jtag_dp_ops;
1146
1147 /*--------------------------------------------------------------------------*/
1148
1149 /**
1150 * Initialize a DAP. This sets up the power domains, prepares the DP
1151 * for further use, and arranges to use AP #0 for all AP operations
1152 * until dap_ap-select() changes that policy.
1153 *
1154 * @param dap The DAP being initialized.
1155 *
1156 * @todo Rename this. We also need an initialization scheme which account
1157 * for SWD transports not just JTAG; that will need to address differences
1158 * in layering. (JTAG is useful without any debug target; but not SWD.)
1159 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1160 */
1161 int ahbap_debugport_init(struct adiv5_dap *dap)
1162 {
1163 uint32_t ctrlstat;
1164 int cnt = 0;
1165 int retval;
1166
1167 LOG_DEBUG(" ");
1168
1169 /* JTAG-DP or SWJ-DP, in JTAG mode
1170 * ... for SWD mode this is patched as part
1171 * of link switchover
1172 */
1173 if (!dap->ops)
1174 dap->ops = &jtag_dp_ops;
1175
1176 /* Default MEM-AP setup.
1177 *
1178 * REVISIT AP #0 may be an inappropriate default for this.
1179 * Should we probe, or take a hint from the caller?
1180 * Presumably we can ignore the possibility of multiple APs.
1181 */
1182 dap->ap_current = !0;
1183 dap_ap_select(dap, 0);
1184
1185 /* DP initialization */
1186
1187 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1188 if (retval != ERROR_OK)
1189 return retval;
1190
1191 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1192 if (retval != ERROR_OK)
1193 return retval;
1194
1195 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1196 if (retval != ERROR_OK)
1197 return retval;
1198
1199 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1200 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1201 if (retval != ERROR_OK)
1202 return retval;
1203
1204 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1205 if (retval != ERROR_OK)
1206 return retval;
1207 if ((retval = dap_run(dap)) != ERROR_OK)
1208 return retval;
1209
1210 /* Check that we have debug power domains activated */
1211 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1212 {
1213 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1214 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1215 if (retval != ERROR_OK)
1216 return retval;
1217 if ((retval = dap_run(dap)) != ERROR_OK)
1218 return retval;
1219 alive_sleep(10);
1220 }
1221
1222 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1223 {
1224 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1225 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1226 if (retval != ERROR_OK)
1227 return retval;
1228 if ((retval = dap_run(dap)) != ERROR_OK)
1229 return retval;
1230 alive_sleep(10);
1231 }
1232
1233 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1234 if (retval != ERROR_OK)
1235 return retval;
1236 /* With debug power on we can activate OVERRUN checking */
1237 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1238 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1239 if (retval != ERROR_OK)
1240 return retval;
1241 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1242 if (retval != ERROR_OK)
1243 return retval;
1244
1245 dap_syssec(dap);
1246
1247 return ERROR_OK;
1248 }
1249
1250 /* CID interpretation -- see ARM IHI 0029B section 3
1251 * and ARM IHI 0031A table 13-3.
1252 */
1253 static const char *class_description[16] ={
1254 "Reserved", "ROM table", "Reserved", "Reserved",
1255 "Reserved", "Reserved", "Reserved", "Reserved",
1256 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1257 "Reserved", "OptimoDE DESS",
1258 "Generic IP component", "PrimeCell or System component"
1259 };
1260
1261 static bool
1262 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1263 {
1264 return cid3 == 0xb1 && cid2 == 0x05
1265 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1266 }
1267
1268 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1269 uint32_t *out_dbgbase, uint32_t *out_apid)
1270 {
1271 uint32_t ap_old;
1272 int retval;
1273 uint32_t dbgbase, apid;
1274
1275 /* AP address is in bits 31:24 of DP_SELECT */
1276 if (ap >= 256)
1277 return ERROR_INVALID_ARGUMENTS;
1278
1279 ap_old = dap->ap_current;
1280 dap_ap_select(dap, ap);
1281
1282 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1283 if (retval != ERROR_OK)
1284 return retval;
1285 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1286 if (retval != ERROR_OK)
1287 return retval;
1288 retval = dap_run(dap);
1289 if (retval != ERROR_OK)
1290 return retval;
1291
1292 /* Excavate the device ID code */
1293 struct jtag_tap *tap = dap->jtag_info->tap;
1294 while (tap != NULL) {
1295 if (tap->hasidcode)
1296 break;
1297 tap = tap->next_tap;
1298 }
1299 if (tap == NULL || !tap->hasidcode)
1300 return ERROR_OK;
1301
1302 dap_ap_select(dap, ap_old);
1303
1304 /* The asignment happens only here to prevent modification of these
1305 * values before they are certain. */
1306 *out_dbgbase = dbgbase;
1307 *out_apid = apid;
1308
1309 return ERROR_OK;
1310 }
1311
1312 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1313 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1314 {
1315 uint32_t ap_old;
1316 uint32_t romentry, entry_offset = 0, component_base, devtype;
1317 int retval = ERROR_FAIL;
1318
1319 if (ap >= 256)
1320 return ERROR_INVALID_ARGUMENTS;
1321
1322 ap_old = dap->ap_current;
1323 dap_ap_select(dap, ap);
1324
1325 do
1326 {
1327 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1328 entry_offset, &romentry);
1329 if (retval != ERROR_OK)
1330 return retval;
1331
1332 component_base = (dbgbase & 0xFFFFF000)
1333 + (romentry & 0xFFFFF000);
1334
1335 if (romentry & 0x1) {
1336 retval = mem_ap_read_atomic_u32(dap,
1337 (component_base & 0xfffff000) | 0xfcc,
1338 &devtype);
1339 if ((devtype & 0xff) == type) {
1340 *addr = component_base;
1341 retval = ERROR_OK;
1342 break;
1343 }
1344 }
1345 entry_offset += 4;
1346 } while (romentry > 0);
1347
1348 dap_ap_select(dap, ap_old);
1349
1350 return retval;
1351 }
1352
1353 static int dap_info_command(struct command_context *cmd_ctx,
1354 struct adiv5_dap *dap, int ap)
1355 {
1356 int retval;
1357 uint32_t dbgbase, apid;
1358 int romtable_present = 0;
1359 uint8_t mem_ap;
1360 uint32_t ap_old;
1361
1362 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1363 if (retval != ERROR_OK)
1364 return retval;
1365
1366 ap_old = dap->ap_current;
1367 dap_ap_select(dap, ap);
1368
1369 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1370 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1371 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1372 if (apid)
1373 {
1374 switch (apid&0x0F)
1375 {
1376 case 0:
1377 command_print(cmd_ctx, "\tType is JTAG-AP");
1378 break;
1379 case 1:
1380 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1381 break;
1382 case 2:
1383 command_print(cmd_ctx, "\tType is MEM-AP APB");
1384 break;
1385 default:
1386 command_print(cmd_ctx, "\tUnknown AP type");
1387 break;
1388 }
1389
1390 /* NOTE: a MEM-AP may have a single CoreSight component that's
1391 * not a ROM table ... or have no such components at all.
1392 */
1393 if (mem_ap)
1394 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1395 dbgbase);
1396 }
1397 else
1398 {
1399 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1400 }
1401
1402 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1403 if (romtable_present)
1404 {
1405 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1406 uint16_t entry_offset;
1407
1408 /* bit 16 of apid indicates a memory access port */
1409 if (dbgbase & 0x02)
1410 command_print(cmd_ctx, "\tValid ROM table present");
1411 else
1412 command_print(cmd_ctx, "\tROM table in legacy format");
1413
1414 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1415 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1416 if (retval != ERROR_OK)
1417 return retval;
1418 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1419 if (retval != ERROR_OK)
1420 return retval;
1421 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1422 if (retval != ERROR_OK)
1423 return retval;
1424 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1425 if (retval != ERROR_OK)
1426 return retval;
1427 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1428 if (retval != ERROR_OK)
1429 return retval;
1430 retval = dap_run(dap);
1431 if (retval != ERROR_OK)
1432 return retval;
1433
1434 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1435 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1436 ", CID2 0x%2.2x"
1437 ", CID1 0x%2.2x"
1438 ", CID0 0x%2.2x",
1439 (unsigned) cid3, (unsigned)cid2,
1440 (unsigned) cid1, (unsigned) cid0);
1441 if (memtype & 0x01)
1442 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1443 else
1444 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1445 "Dedicated debug bus.");
1446
1447 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1448 entry_offset = 0;
1449 do
1450 {
1451 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1452 if (retval != ERROR_OK)
1453 return retval;
1454 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1455 if (romentry&0x01)
1456 {
1457 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1458 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1459 uint32_t component_base;
1460 unsigned part_num;
1461 char *type, *full;
1462
1463 component_base = (dbgbase & 0xFFFFF000)
1464 + (romentry & 0xFFFFF000);
1465
1466 /* IDs are in last 4K section */
1467
1468
1469 retval = mem_ap_read_atomic_u32(dap,
1470 component_base + 0xFE0, &c_pid0);
1471 if (retval != ERROR_OK)
1472 return retval;
1473 c_pid0 &= 0xff;
1474 retval = mem_ap_read_atomic_u32(dap,
1475 component_base + 0xFE4, &c_pid1);
1476 if (retval != ERROR_OK)
1477 return retval;
1478 c_pid1 &= 0xff;
1479 retval = mem_ap_read_atomic_u32(dap,
1480 component_base + 0xFE8, &c_pid2);
1481 if (retval != ERROR_OK)
1482 return retval;
1483 c_pid2 &= 0xff;
1484 retval = mem_ap_read_atomic_u32(dap,
1485 component_base + 0xFEC, &c_pid3);
1486 if (retval != ERROR_OK)
1487 return retval;
1488 c_pid3 &= 0xff;
1489 retval = mem_ap_read_atomic_u32(dap,
1490 component_base + 0xFD0, &c_pid4);
1491 if (retval != ERROR_OK)
1492 return retval;
1493 c_pid4 &= 0xff;
1494
1495 retval = mem_ap_read_atomic_u32(dap,
1496 component_base + 0xFF0, &c_cid0);
1497 if (retval != ERROR_OK)
1498 return retval;
1499 c_cid0 &= 0xff;
1500 retval = mem_ap_read_atomic_u32(dap,
1501 component_base + 0xFF4, &c_cid1);
1502 if (retval != ERROR_OK)
1503 return retval;
1504 c_cid1 &= 0xff;
1505 retval = mem_ap_read_atomic_u32(dap,
1506 component_base + 0xFF8, &c_cid2);
1507 if (retval != ERROR_OK)
1508 return retval;
1509 c_cid2 &= 0xff;
1510 retval = mem_ap_read_atomic_u32(dap,
1511 component_base + 0xFFC, &c_cid3);
1512 if (retval != ERROR_OK)
1513 return retval;
1514 c_cid3 &= 0xff;
1515
1516
1517 command_print(cmd_ctx,
1518 "\t\tComponent base address 0x%" PRIx32
1519 ", start address 0x%" PRIx32,
1520 component_base,
1521 /* component may take multiple 4K pages */
1522 component_base - 0x1000*(c_pid4 >> 4));
1523 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1524 (int) (c_cid1 >> 4) & 0xf,
1525 /* See ARM IHI 0029B Table 3-3 */
1526 class_description[(c_cid1 >> 4) & 0xf]);
1527
1528 /* CoreSight component? */
1529 if (((c_cid1 >> 4) & 0x0f) == 9) {
1530 uint32_t devtype;
1531 unsigned minor;
1532 char *major = "Reserved", *subtype = "Reserved";
1533
1534 retval = mem_ap_read_atomic_u32(dap,
1535 (component_base & 0xfffff000) | 0xfcc,
1536 &devtype);
1537 if (retval != ERROR_OK)
1538 return retval;
1539 minor = (devtype >> 4) & 0x0f;
1540 switch (devtype & 0x0f) {
1541 case 0:
1542 major = "Miscellaneous";
1543 switch (minor) {
1544 case 0:
1545 subtype = "other";
1546 break;
1547 case 4:
1548 subtype = "Validation component";
1549 break;
1550 }
1551 break;
1552 case 1:
1553 major = "Trace Sink";
1554 switch (minor) {
1555 case 0:
1556 subtype = "other";
1557 break;
1558 case 1:
1559 subtype = "Port";
1560 break;
1561 case 2:
1562 subtype = "Buffer";
1563 break;
1564 }
1565 break;
1566 case 2:
1567 major = "Trace Link";
1568 switch (minor) {
1569 case 0:
1570 subtype = "other";
1571 break;
1572 case 1:
1573 subtype = "Funnel, router";
1574 break;
1575 case 2:
1576 subtype = "Filter";
1577 break;
1578 case 3:
1579 subtype = "FIFO, buffer";
1580 break;
1581 }
1582 break;
1583 case 3:
1584 major = "Trace Source";
1585 switch (minor) {
1586 case 0:
1587 subtype = "other";
1588 break;
1589 case 1:
1590 subtype = "Processor";
1591 break;
1592 case 2:
1593 subtype = "DSP";
1594 break;
1595 case 3:
1596 subtype = "Engine/Coprocessor";
1597 break;
1598 case 4:
1599 subtype = "Bus";
1600 break;
1601 }
1602 break;
1603 case 4:
1604 major = "Debug Control";
1605 switch (minor) {
1606 case 0:
1607 subtype = "other";
1608 break;
1609 case 1:
1610 subtype = "Trigger Matrix";
1611 break;
1612 case 2:
1613 subtype = "Debug Auth";
1614 break;
1615 }
1616 break;
1617 case 5:
1618 major = "Debug Logic";
1619 switch (minor) {
1620 case 0:
1621 subtype = "other";
1622 break;
1623 case 1:
1624 subtype = "Processor";
1625 break;
1626 case 2:
1627 subtype = "DSP";
1628 break;
1629 case 3:
1630 subtype = "Engine/Coprocessor";
1631 break;
1632 }
1633 break;
1634 }
1635 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1636 (unsigned) (devtype & 0xff),
1637 major, subtype);
1638 /* REVISIT also show 0xfc8 DevId */
1639 }
1640
1641 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1642 command_print(cmd_ctx,
1643 "\t\tCID3 0%2.2x"
1644 ", CID2 0%2.2x"
1645 ", CID1 0%2.2x"
1646 ", CID0 0%2.2x",
1647 (int) c_cid3,
1648 (int) c_cid2,
1649 (int)c_cid1,
1650 (int)c_cid0);
1651 command_print(cmd_ctx,
1652 "\t\tPeripheral ID[4..0] = hex "
1653 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1654 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1655 (int) c_pid1, (int) c_pid0);
1656
1657 /* Part number interpretations are from Cortex
1658 * core specs, the CoreSight components TRM
1659 * (ARM DDI 0314H), CoreSight System Design
1660 * Guide (ARM DGI 0012D) and ETM specs; also
1661 * from chip observation (e.g. TI SDTI).
1662 */
1663 part_num = (c_pid0 & 0xff);
1664 part_num |= (c_pid1 & 0x0f) << 8;
1665 switch (part_num) {
1666 case 0x000:
1667 type = "Cortex-M3 NVIC";
1668 full = "(Interrupt Controller)";
1669 break;
1670 case 0x001:
1671 type = "Cortex-M3 ITM";
1672 full = "(Instrumentation Trace Module)";
1673 break;
1674 case 0x002:
1675 type = "Cortex-M3 DWT";
1676 full = "(Data Watchpoint and Trace)";
1677 break;
1678 case 0x003:
1679 type = "Cortex-M3 FBP";
1680 full = "(Flash Patch and Breakpoint)";
1681 break;
1682 case 0x00d:
1683 type = "CoreSight ETM11";
1684 full = "(Embedded Trace)";
1685 break;
1686 // case 0x113: what?
1687 case 0x120: /* from OMAP3 memmap */
1688 type = "TI SDTI";
1689 full = "(System Debug Trace Interface)";
1690 break;
1691 case 0x343: /* from OMAP3 memmap */
1692 type = "TI DAPCTL";
1693 full = "";
1694 break;
1695 case 0x906:
1696 type = "Coresight CTI";
1697 full = "(Cross Trigger)";
1698 break;
1699 case 0x907:
1700 type = "Coresight ETB";
1701 full = "(Trace Buffer)";
1702 break;
1703 case 0x908:
1704 type = "Coresight CSTF";
1705 full = "(Trace Funnel)";
1706 break;
1707 case 0x910:
1708 type = "CoreSight ETM9";
1709 full = "(Embedded Trace)";
1710 break;
1711 case 0x912:
1712 type = "Coresight TPIU";
1713 full = "(Trace Port Interface Unit)";
1714 break;
1715 case 0x921:
1716 type = "Cortex-A8 ETM";
1717 full = "(Embedded Trace)";
1718 break;
1719 case 0x922:
1720 type = "Cortex-A8 CTI";
1721 full = "(Cross Trigger)";
1722 break;
1723 case 0x923:
1724 type = "Cortex-M3 TPIU";
1725 full = "(Trace Port Interface Unit)";
1726 break;
1727 case 0x924:
1728 type = "Cortex-M3 ETM";
1729 full = "(Embedded Trace)";
1730 break;
1731 case 0x930:
1732 type = "Cortex-R4 ETM";
1733 full = "(Embedded Trace)";
1734 break;
1735 case 0xc08:
1736 type = "Cortex-A8 Debug";
1737 full = "(Debug Unit)";
1738 break;
1739 default:
1740 type = "-*- unrecognized -*-";
1741 full = "";
1742 break;
1743 }
1744 command_print(cmd_ctx, "\t\tPart is %s %s",
1745 type, full);
1746 }
1747 else
1748 {
1749 if (romentry)
1750 command_print(cmd_ctx, "\t\tComponent not present");
1751 else
1752 command_print(cmd_ctx, "\t\tEnd of ROM table");
1753 }
1754 entry_offset += 4;
1755 } while (romentry > 0);
1756 }
1757 else
1758 {
1759 command_print(cmd_ctx, "\tNo ROM table present");
1760 }
1761 dap_ap_select(dap, ap_old);
1762
1763 return ERROR_OK;
1764 }
1765
1766 COMMAND_HANDLER(handle_dap_info_command)
1767 {
1768 struct target *target = get_current_target(CMD_CTX);
1769 struct arm *arm = target_to_arm(target);
1770 struct adiv5_dap *dap = arm->dap;
1771 uint32_t apsel;
1772
1773 switch (CMD_ARGC) {
1774 case 0:
1775 apsel = dap->apsel;
1776 break;
1777 case 1:
1778 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1779 break;
1780 default:
1781 return ERROR_COMMAND_SYNTAX_ERROR;
1782 }
1783
1784 return dap_info_command(CMD_CTX, dap, apsel);
1785 }
1786
1787 COMMAND_HANDLER(dap_baseaddr_command)
1788 {
1789 struct target *target = get_current_target(CMD_CTX);
1790 struct arm *arm = target_to_arm(target);
1791 struct adiv5_dap *dap = arm->dap;
1792
1793 uint32_t apsel, baseaddr;
1794 int retval;
1795
1796 switch (CMD_ARGC) {
1797 case 0:
1798 apsel = dap->apsel;
1799 break;
1800 case 1:
1801 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1802 /* AP address is in bits 31:24 of DP_SELECT */
1803 if (apsel >= 256)
1804 return ERROR_INVALID_ARGUMENTS;
1805 break;
1806 default:
1807 return ERROR_COMMAND_SYNTAX_ERROR;
1808 }
1809
1810 dap_ap_select(dap, apsel);
1811
1812 /* NOTE: assumes we're talking to a MEM-AP, which
1813 * has a base address. There are other kinds of AP,
1814 * though they're not common for now. This should
1815 * use the ID register to verify it's a MEM-AP.
1816 */
1817 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1818 if (retval != ERROR_OK)
1819 return retval;
1820 retval = dap_run(dap);
1821 if (retval != ERROR_OK)
1822 return retval;
1823
1824 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1825
1826 return retval;
1827 }
1828
1829 COMMAND_HANDLER(dap_memaccess_command)
1830 {
1831 struct target *target = get_current_target(CMD_CTX);
1832 struct arm *arm = target_to_arm(target);
1833 struct adiv5_dap *dap = arm->dap;
1834
1835 uint32_t memaccess_tck;
1836
1837 switch (CMD_ARGC) {
1838 case 0:
1839 memaccess_tck = dap->memaccess_tck;
1840 break;
1841 case 1:
1842 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1843 break;
1844 default:
1845 return ERROR_COMMAND_SYNTAX_ERROR;
1846 }
1847 dap->memaccess_tck = memaccess_tck;
1848
1849 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1850 dap->memaccess_tck);
1851
1852 return ERROR_OK;
1853 }
1854
1855 COMMAND_HANDLER(dap_apsel_command)
1856 {
1857 struct target *target = get_current_target(CMD_CTX);
1858 struct arm *arm = target_to_arm(target);
1859 struct adiv5_dap *dap = arm->dap;
1860
1861 uint32_t apsel, apid;
1862 int retval;
1863
1864 switch (CMD_ARGC) {
1865 case 0:
1866 apsel = 0;
1867 break;
1868 case 1:
1869 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1870 /* AP address is in bits 31:24 of DP_SELECT */
1871 if (apsel >= 256)
1872 return ERROR_INVALID_ARGUMENTS;
1873 break;
1874 default:
1875 return ERROR_COMMAND_SYNTAX_ERROR;
1876 }
1877
1878 dap->apsel = apsel;
1879 dap_ap_select(dap, apsel);
1880
1881 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1882 if (retval != ERROR_OK)
1883 return retval;
1884 retval = dap_run(dap);
1885 if (retval != ERROR_OK)
1886 return retval;
1887
1888 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1889 apsel, apid);
1890
1891 return retval;
1892 }
1893
1894 COMMAND_HANDLER(dap_apid_command)
1895 {
1896 struct target *target = get_current_target(CMD_CTX);
1897 struct arm *arm = target_to_arm(target);
1898 struct adiv5_dap *dap = arm->dap;
1899
1900 uint32_t apsel, apid;
1901 int retval;
1902
1903 switch (CMD_ARGC) {
1904 case 0:
1905 apsel = dap->apsel;
1906 break;
1907 case 1:
1908 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1909 /* AP address is in bits 31:24 of DP_SELECT */
1910 if (apsel >= 256)
1911 return ERROR_INVALID_ARGUMENTS;
1912 break;
1913 default:
1914 return ERROR_COMMAND_SYNTAX_ERROR;
1915 }
1916
1917 dap_ap_select(dap, apsel);
1918
1919 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1920 if (retval != ERROR_OK)
1921 return retval;
1922 retval = dap_run(dap);
1923 if (retval != ERROR_OK)
1924 return retval;
1925
1926 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1927
1928 return retval;
1929 }
1930
1931 static const struct command_registration dap_commands[] = {
1932 {
1933 .name = "info",
1934 .handler = handle_dap_info_command,
1935 .mode = COMMAND_EXEC,
1936 .help = "display ROM table for MEM-AP "
1937 "(default currently selected AP)",
1938 .usage = "[ap_num]",
1939 },
1940 {
1941 .name = "apsel",
1942 .handler = dap_apsel_command,
1943 .mode = COMMAND_EXEC,
1944 .help = "Set the currently selected AP (default 0) "
1945 "and display the result",
1946 .usage = "[ap_num]",
1947 },
1948 {
1949 .name = "apid",
1950 .handler = dap_apid_command,
1951 .mode = COMMAND_EXEC,
1952 .help = "return ID register from AP "
1953 "(default currently selected AP)",
1954 .usage = "[ap_num]",
1955 },
1956 {
1957 .name = "baseaddr",
1958 .handler = dap_baseaddr_command,
1959 .mode = COMMAND_EXEC,
1960 .help = "return debug base address from MEM-AP "
1961 "(default currently selected AP)",
1962 .usage = "[ap_num]",
1963 },
1964 {
1965 .name = "memaccess",
1966 .handler = dap_memaccess_command,
1967 .mode = COMMAND_EXEC,
1968 .help = "set/get number of extra tck for MEM-AP memory "
1969 "bus access [0-255]",
1970 .usage = "[cycles]",
1971 },
1972 COMMAND_REGISTRATION_DONE
1973 };
1974
1975 const struct command_registration dap_command_handlers[] = {
1976 {
1977 .name = "dap",
1978 .mode = COMMAND_EXEC,
1979 .help = "DAP command group",
1980 .chain = dap_commands,
1981 },
1982 COMMAND_REGISTRATION_DONE
1983 };
1984
1985
Spen's Unofficial Testing Repository