src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011-2012 by Tomasz Boleslaw CEDRO                      *
   9  *   cederom@tlen.pl, http://www.tomek.cedro.info                          *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifndef ARM_ADI_V5_H
  28 #define ARM_ADI_V5_H
  29
  30 /**
  31  * @file
  32  * This defines formats and data structures used to talk to ADIv5 entities.
  33  * Those include a DAP, different types of Debug Port (DP), and memory mapped
  34  * resources accessed through a MEM-AP.
  35  */
  36
  37 #include "arm_jtag.h"
  38 #include <interface/feature.h>
  39
  40 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
  41  * is no longer JTAG-specific
  42  */
  43 #define JTAG_DP_DPACC           0xA
  44 #define JTAG_DP_APACC           0xB
  45
  46 /* three-bit ACK values for SWD access (sent LSB first) */
  47 #define SWD_ACK_OK              0x4
  48 #define SWD_ACK_WAIT            0x2
  49 #define SWD_ACK_FAULT           0x1
  50
  51 #define DPAP_WRITE              0
  52 #define DPAP_READ               1
  53
  54 /* A[3:0] for DP registers; A[1:0] are always zero.
  55  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  56  *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
  57  * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
  58  */
  59 #define DP_IDCODE               0               /* SWD: read */
  60 #define DP_ABORT                0               /* SWD: write */
  61 #define DP_CTRL_STAT            0x4             /* r/w */
  62 #define DP_WCR                  0x4             /* SWD: r/w (mux CTRLSEL) */
  63 #define DP_RESEND               0x8             /* SWD: read */
  64 #define DP_SELECT               0x8             /* JTAG: r/w; SWD: write */
  65 #define DP_RDBUFF               0xC             /* read-only */
  66
  67 #define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8))        /* 1..4 clocks */
  68 #define WCR_TO_PRESCALE(wcr) (7 & ((wcr)))              /* impl defined */
  69
  70 /* Fields of the DP's AP ABORT register */
  71 #define DAPABORT                (1 << 0)
  72 #define STKCMPCLR               (1 << 1)        /* SWD-only */
  73 #define STKERRCLR               (1 << 2)        /* SWD-only */
  74 #define WDERRCLR                (1 << 3)        /* SWD-only */
  75 #define ORUNERRCLR              (1 << 4)        /* SWD-only */
  76
  77 /* Fields of the DP's CTRL/STAT register */
  78 #define CORUNDETECT             (1 << 0)
  79 #define SSTICKYORUN             (1 << 1)
  80 /* 3:2 - transaction mode (e.g. pushed compare) */
  81 #define SSTICKYCMP              (1 << 4)
  82 #define SSTICKYERR              (1 << 5)
  83 #define READOK                  (1 << 6)        /* SWD-only */
  84 #define WDATAERR                (1 << 7)        /* SWD-only */
  85 /* 11:8 - mask lanes for pushed compare or verify ops */
  86 /* 21:12 - transaction counter */
  87 #define CDBGRSTREQ              (1 << 26)
  88 #define CDBGRSTACK              (1 << 27)
  89 #define CDBGPWRUPREQ    (1 << 28)
  90 #define CDBGPWRUPACK    (1 << 29)
  91 #define CSYSPWRUPREQ    (1 << 30)
  92 #define CSYSPWRUPACK    (1 << 31)
  93
  94 /* MEM-AP register addresses */
  95 /* TODO: rename as MEM_AP_REG_* */
  96 #define AP_REG_CSW              0x00
  97 #define AP_REG_TAR              0x04
  98 #define AP_REG_DRW              0x0C
  99 #define AP_REG_BD0              0x10
 100 #define AP_REG_BD1              0x14
 101 #define AP_REG_BD2              0x18
 102 #define AP_REG_BD3              0x1C
 103 #define AP_REG_CFG              0xF4            /* big endian? */
 104 #define AP_REG_BASE             0xF8
 105
 106 /* Generic AP register address */
 107 #define AP_REG_IDR              0xFC
 108
 109 /* Fields of the MEM-AP's CSW register */
 110 #define CSW_8BIT                0
 111 #define CSW_16BIT               1
 112 #define CSW_32BIT               2
 113 #define CSW_ADDRINC_MASK        (3 << 4)
 114 #define CSW_ADDRINC_OFF         0
 115 #define CSW_ADDRINC_SINGLE      (1 << 4)
 116 #define CSW_ADDRINC_PACKED      (2 << 4)
 117 #define CSW_DEVICE_EN           (1 << 6)
 118 #define CSW_TRIN_PROG           (1 << 7)
 119 #define CSW_SPIDEN                      (1 << 23)
 120 /* 30:24 - implementation-defined! */
 121 #define CSW_HPROT                       (1 << 25)               /* ? */
 122 #define CSW_MASTER_DEBUG        (1 << 29)               /* ? */
 123 #define CSW_DBGSWENABLE         (1 << 31)
 124
 125 /**
 126  * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
 127  * A DAP has two types of component:  one Debug Port (DP), which is a
 128  * transport agent; and at least one Access Port (AP), controlling
 129  * resource access.  Most common is a MEM-AP, for memory access.
 130  *
 131  * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
 132  * Accordingly, this interface is responsible for hiding the transport
 133  * differences so upper layer code can largely ignore them.
 134  *
 135  * When the chip is implemented with JTAG-DP or SW-DP, the transport is
 136  * fixed as JTAG or SWD, respectively.  Chips incorporating SWJ-DP permit
 137  * a choice made at board design time (by only using the SWD pins), or
 138  * as part of setting up a debug session (if all the dual-role JTAG/SWD
 139  * signals are available).
 140  */
 141 struct adiv5_dap {
 142         const struct dap_ops *ops;
 143
 144         struct arm_jtag *jtag_info;
 145         /* Control config */
 146         uint32_t dp_ctrl_stat;
 147
 148         uint32_t apsel;
 149
 150         /** Context to store DAP specific information, settings, transport, etc.*/
 151         void *ctx;
 152
 153         /**
 154          * Cache for DP_SELECT bits identifying the current AP.  A DAP may
 155          * connect to multiple APs, such as one MEM-AP for general access,
 156          * another reserved for accessing debug modules, and a JTAG-DP.
 157          * "-1" indicates no cached value.
 158          */
 159         uint32_t ap_current;
 160
 161         /**
 162          * Cache for DP_SELECT bits identifying the current four-word AP
 163          * register bank.  This caches AP register addresss bits 7:4; JTAG
 164          * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
 165          * "-1" indicates no cached value.
 166          */
 167         uint32_t ap_bank_value;
 168
 169         /**
 170          * Cache for (MEM-AP) AP_REG_CSW register value.  This is written to
 171          * configure an access mode, such as autoincrementing AP_REG_TAR during
 172          * word access.  "-1" indicates no cached value.
 173          */
 174         uint32_t ap_csw_value;
 175
 176         /**
 177          * Cache for (MEM-AP) AP_REG_TAR register value This is written to
 178          * configure the address being read or written
 179          * "-1" indicates no cached value.
 180          */
 181         uint32_t ap_tar_value;
 182
 183         /* information about current pending SWjDP-AHBAP transaction */
 184         uint8_t  ack;
 185
 186         /**
 187          * Configures how many extra tck clocks are added after starting a
 188          * MEM-AP access before we try to read its status (and/or result).
 189          */
 190         uint32_t        memaccess_tck;
 191
 192         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 193         uint32_t tar_autoincr_block;
 194 };
 195
 196 /**
 197  * Transport-neutral representation of queued DAP transactions, supporting
 198  * both JTAG and SWD transports.  All submitted transactions are logically
 199  * queued, until the queue is executed by run().  Some implementations might
 200  * execute transactions as soon as they're submitted, but no status is made
 201  * availablue until run().
 202  */
 203 struct dap_ops {
 204         /** If the DAP transport isn't SWD, it must be JTAG.  Upper level
 205          * code may need to care about the difference in some cases.
 206          */
 207         bool    is_swd;
 208
 209         /** Transport dependent selection routine, setup mainly. */
 210         int (*select)(struct command_context *ctx);
 211
 212         /** Transport dependent DAP initialization and detection routine. */
 213         int (*init)(struct command_context *ctx);
 214
 215         /** Reads the DAP's IDCODe register. */
 216         int (*queue_idcode_read)(struct adiv5_dap *dap,
 217                         uint8_t *ack, uint32_t *data);
 218
 219         /** DP register read. */
 220         int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
 221                         uint32_t *data);
 222         /** DP register write. */
 223         int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
 224                         uint32_t data);
 225
 226         /** AP register read. */
 227         int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
 228                         uint32_t *data);
 229         /** AP register write. */
 230         int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
 231                         uint32_t data);
 232
 233         /** AP operation abort. */
 234         int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
 235
 236         /** Executes all queued DAP operations. */
 237         int (*run)(struct adiv5_dap *dap);
 238 };
 239
 240 extern oocd_feature_t oocd_transport_jtag_arm_dap_feature;
 241
 242 /**
 243  * Queue an IDCODE register read.  This is primarily useful for SWD
 244  * transports, where it is required as part of link initialization.
 245  * (For JTAG, this register is read as part of scan chain setup.)
 246  *
 247  * @param dap The DAP used for reading.
 248  * @param ack Pointer to where transaction status will be stored.
 249  * @param data Pointer saying where to store the IDCODE value.
 250  *
 251  * @return ERROR_OK for success, else a fault code.
 252  */
 253 static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
 254                 uint8_t *ack, uint32_t *data)
 255 {
 256         assert(dap->ops != NULL);
 257         return dap->ops->queue_idcode_read(dap, ack, data);
 258 }
 259
 260 /**
 261  * Queue a DP register read.
 262  * Note that not all DP registers are readable; also, that JTAG and SWD
 263  * have slight differences in DP register support.
 264  *
 265  * @param dap The DAP used for reading.
 266  * @param reg The two-bit number of the DP register being read.
 267  * @param data Pointer saying where to store the register's value
 268  * (in host endianness).
 269  *
 270  * @return ERROR_OK for success, else a fault code.
 271  */
 272 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
 273                 unsigned reg, uint32_t *data)
 274 {
 275         assert(dap->ops != NULL);
 276         return dap->ops->queue_dp_read(dap, reg, data);
 277 }
 278
 279 /**
 280  * Queue a DP register write.
 281  * Note that not all DP registers are writable; also, that JTAG and SWD
 282  * have slight differences in DP register support.
 283  *
 284  * @param dap The DAP used for writing.
 285  * @param reg The two-bit number of the DP register being written.
 286  * @param data Value being written (host endianness)
 287  *
 288  * @return ERROR_OK for success, else a fault code.
 289  */
 290 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
 291                 unsigned reg, uint32_t data)
 292 {
 293         assert(dap->ops != NULL);
 294         return dap->ops->queue_dp_write(dap, reg, data);
 295 }
 296
 297 /**
 298  * Queue an AP register read.
 299  *
 300  * @param dap The DAP used for reading.
 301  * @param reg The number of the AP register being read.
 302  * @param data Pointer saying where to store the register's value
 303  * (in host endianness).
 304  *
 305  * @return ERROR_OK for success, else a fault code.
 306  */
 307 static inline int dap_queue_ap_read(struct adiv5_dap *dap,
 308                 unsigned reg, uint32_t *data)
 309 {
 310         assert(dap->ops != NULL);
 311         return dap->ops->queue_ap_read(dap, reg, data);
 312 }
 313
 314 /**
 315  * Queue an AP register write.
 316  *
 317  * @param dap The DAP used for writing.
 318  * @param reg The number of the AP register being written.
 319  * @param data Value being written (host endianness)
 320  *
 321  * @return ERROR_OK for success, else a fault code.
 322  */
 323 static inline int dap_queue_ap_write(struct adiv5_dap *dap,
 324                 unsigned reg, uint32_t data)
 325 {
 326         assert(dap->ops != NULL);
 327         return dap->ops->queue_ap_write(dap, reg, data);
 328 }
 329
 330 /**
 331  * Queue an AP abort operation.  The current AP transaction is aborted,
 332  * including any update of the transaction counter.  The AP is left in
 333  * an unknown state (so it must be re-initialized).  For use only after
 334  * the AP has reported WAIT status for an extended period.
 335  *
 336  * @param dap The DAP used for writing.
 337  * @param ack Pointer to where transaction status will be stored.
 338  *
 339  * @return ERROR_OK for success, else a fault code.
 340  */
 341 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 342 {
 343         assert(dap->ops != NULL);
 344         return dap->ops->queue_ap_abort(dap, ack);
 345 }
 346
 347 /**
 348  * Perform all queued DAP operations, and clear any errors posted in the
 349  * CTRL_STAT register when they are done.  Note that if more than one AP
 350  * operation will be queued, one of the first operations in the queue
 351  * should probably enable CORUNDETECT in the CTRL/STAT register.
 352  *
 353  * @param dap The DAP used.
 354  *
 355  * @return ERROR_OK for success, else a fault code.
 356  */
 357 static inline int dap_run(struct adiv5_dap *dap)
 358 {
 359         assert(dap->ops != NULL);
 360         return dap->ops->run(dap);
 361 }
 362
 363 /** Accessor for currently selected DAP-AP number (0..255) */
 364 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
 365 {
 366         return (uint8_t)(swjdp->ap_current >> 24);
 367 }
 368
 369 /* AP selection applies to future AP transactions */
 370 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
 371
 372 /* Queued AP transactions */
 373 int dap_setup_accessport(struct adiv5_dap *swjdp,
 374                 uint32_t csw, uint32_t tar);
 375
 376 /* Queued MEM-AP memory mapped single word transfers */
 377 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
 378 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
 379
 380 /* Synchronous MEM-AP memory mapped single word transfers */
 381 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
 382                 uint32_t address, uint32_t *value);
 383 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
 384                 uint32_t address, uint32_t value);
 385
 386 /* MEM-AP memory mapped bus block transfers */
 387 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
 388                 uint8_t *buffer, int count, uint32_t address);
 389 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
 390                 uint8_t *buffer, int count, uint32_t address);
 391 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
 392                 uint8_t *buffer, int count, uint32_t address);
 393
 394 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
 395                 const uint8_t *buffer, int count, uint32_t address);
 396 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
 397                 const uint8_t *buffer, int count, uint32_t address);
 398 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
 399                 const uint8_t *buffer, int count, uint32_t address);
 400
 401 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
 402 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 403                 uint32_t address, uint32_t *value);
 404 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 405                 uint32_t address, uint32_t value);
 406
 407 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
 408 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 409                 uint32_t address, uint32_t *value);
 410 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 411                 uint32_t address, uint32_t value);
 412
 413 /* MEM-AP memory mapped bus block transfers with selection of ap */
 414 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 415                 uint8_t *buffer, int count, uint32_t address);
 416 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 417                 uint8_t *buffer, int count, uint32_t address);
 418 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 419                 uint8_t *buffer, int count, uint32_t address);
 420
 421 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 422                 const uint8_t *buffer, int count, uint32_t address);
 423 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 424                 const uint8_t *buffer, int count, uint32_t address);
 425 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 426                 const uint8_t *buffer, int count, uint32_t address);
 427
 428 /* Initialisation of the debug system, power domains and registers */
 429 int ahbap_debugport_init(struct adiv5_dap *swjdp);
 430
 431 /* Probe the AP for ROM Table location */
 432 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 433                         uint32_t *dbgbase, uint32_t *apid);
 434
 435 /* Lookup CoreSight component */
 436 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 437                         uint32_t dbgbase, uint8_t type, uint32_t *addr);
 438
 439 struct target;
 440
 441 /* Put debug link into SWD mode */
 442 int dap_to_swd(struct target *target);
 443 extern oocd_transport_t swd_transport;
 444
 445 /* Put debug link into JTAG mode */
 446 int dap_to_jtag(struct target *target);
 447
 448 extern const struct command_registration dap_command_handlers[];
 449
 450 #endif