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dsp5680xx - match page erase with mass erase
[openocd/dsp568013.git] / src / flash / nor / stm32f1x.c
blob8e0fda7e8a43118b494141d2b4f1f4eb6be117a9
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "imp.h"
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
33 #include <target/armv7m.h>
34
35 /* stm32x register locations */
36
37 #define FLASH_REG_BASE_B0 0x40022000
38 #define FLASH_REG_BASE_B1 0x40022040
39
40 #define STM32_FLASH_ACR 0x00
41 #define STM32_FLASH_KEYR 0x04
42 #define STM32_FLASH_OPTKEYR 0x08
43 #define STM32_FLASH_SR 0x0C
44 #define STM32_FLASH_CR 0x10
45 #define STM32_FLASH_AR 0x14
46 #define STM32_FLASH_OBR 0x1C
47 #define STM32_FLASH_WRPR 0x20
48
49 /* TODO: Check if code using these really should be hard coded to bank 0.
50 * There are valid cases, on dual flash devices the protection of the
51 * second bank is done on the bank0 reg's. */
52 #define STM32_FLASH_ACR_B0 0x40022000
53 #define STM32_FLASH_KEYR_B0 0x40022004
54 #define STM32_FLASH_OPTKEYR_B0 0x40022008
55 #define STM32_FLASH_SR_B0 0x4002200C
56 #define STM32_FLASH_CR_B0 0x40022010
57 #define STM32_FLASH_AR_B0 0x40022014
58 #define STM32_FLASH_OBR_B0 0x4002201C
59 #define STM32_FLASH_WRPR_B0 0x40022020
60
61 /* option byte location */
62
63 #define STM32_OB_RDP 0x1FFFF800
64 #define STM32_OB_USER 0x1FFFF802
65 #define STM32_OB_DATA0 0x1FFFF804
66 #define STM32_OB_DATA1 0x1FFFF806
67 #define STM32_OB_WRP0 0x1FFFF808
68 #define STM32_OB_WRP1 0x1FFFF80A
69 #define STM32_OB_WRP2 0x1FFFF80C
70 #define STM32_OB_WRP3 0x1FFFF80E
71
72 /* FLASH_CR register bits */
73
74 #define FLASH_PG (1 << 0)
75 #define FLASH_PER (1 << 1)
76 #define FLASH_MER (1 << 2)
77 #define FLASH_OPTPG (1 << 4)
78 #define FLASH_OPTER (1 << 5)
79 #define FLASH_STRT (1 << 6)
80 #define FLASH_LOCK (1 << 7)
81 #define FLASH_OPTWRE (1 << 9)
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 struct stm32x_options
105 {
106 uint16_t RDP;
107 uint16_t user_options;
108 uint16_t protection[4];
109 };
110
111 struct stm32x_flash_bank
112 {
113 struct stm32x_options option_bytes;
114 struct working_area *write_algorithm;
115 int ppage_size;
116 int probed;
117
118 bool has_dual_banks;
119 /* used to access dual flash bank stm32xl */
120 uint32_t register_base;
121 };
122
123 static int stm32x_mass_erase(struct flash_bank *bank);
124
125 /* flash bank stm32x <base> <size> 0 0 <target#>
126 */
127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
128 {
129 struct stm32x_flash_bank *stm32x_info;
130
131 if (CMD_ARGC < 6)
132 {
133 LOG_WARNING("incomplete flash_bank stm32x configuration");
134 return ERROR_FLASH_BANK_INVALID;
135 }
136
137 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
138 bank->driver_priv = stm32x_info;
139
140 stm32x_info->write_algorithm = NULL;
141 stm32x_info->probed = 0;
142 stm32x_info->has_dual_banks = false;
143 stm32x_info->register_base = FLASH_REG_BASE_B0;
144
145 return ERROR_OK;
146 }
147
148 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
149 {
150 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
151 return reg + stm32x_info->register_base;
152 }
153
154 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
155 {
156 struct target *target = bank->target;
157 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
158 }
159
160 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
161 {
162 struct target *target = bank->target;
163 uint32_t status;
164 int retval = ERROR_OK;
165
166 /* wait for busy to clear */
167 for (;;)
168 {
169 retval = stm32x_get_flash_status(bank, &status);
170 if (retval != ERROR_OK)
171 return retval;
172 LOG_DEBUG("status: 0x%" PRIx32 "", status);
173 if ((status & FLASH_BSY) == 0)
174 break;
175 if (timeout-- <= 0)
176 {
177 LOG_ERROR("timed out waiting for flash");
178 return ERROR_FAIL;
179 }
180 alive_sleep(1);
181 }
182
183 if (status & FLASH_WRPRTERR)
184 {
185 LOG_ERROR("stm32x device protected");
186 retval = ERROR_FAIL;
187 }
188
189 if (status & FLASH_PGERR)
190 {
191 LOG_ERROR("stm32x device programming failed");
192 retval = ERROR_FAIL;
193 }
194
195 /* Clear but report errors */
196 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
197 {
198 /* If this operation fails, we ignore it and report the original
199 * retval
200 */
201 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
202 FLASH_WRPRTERR | FLASH_PGERR);
203 }
204 return retval;
205 }
206
207 int stm32x_check_operation_supported(struct flash_bank *bank)
208 {
209 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
210
211 /* if we have a dual flash bank device then
212 * we need to perform option byte stuff on bank0 only */
213 if (stm32x_info->register_base != FLASH_REG_BASE_B0)
214 {
215 LOG_ERROR("Option Byte Operation's must use bank0");
216 return ERROR_FLASH_OPERATION_FAILED;
217 }
218
219 return ERROR_OK;
220 }
221
222 static int stm32x_read_options(struct flash_bank *bank)
223 {
224 uint32_t optiondata;
225 struct stm32x_flash_bank *stm32x_info = NULL;
226 struct target *target = bank->target;
227
228 stm32x_info = bank->driver_priv;
229
230 /* read current option bytes */
231 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
232 if (retval != ERROR_OK)
233 return retval;
234
235 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
236 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
237
238 if (optiondata & (1 << OPT_READOUT))
239 LOG_INFO("Device Security Bit Set");
240
241 /* each bit refers to a 4bank protection */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
243 if (retval != ERROR_OK)
244 return retval;
245
246 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
247 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
248 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
249 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
250
251 return ERROR_OK;
252 }
253
254 static int stm32x_erase_options(struct flash_bank *bank)
255 {
256 struct stm32x_flash_bank *stm32x_info = NULL;
257 struct target *target = bank->target;
258
259 stm32x_info = bank->driver_priv;
260
261 /* read current options */
262 stm32x_read_options(bank);
263
264 /* unlock flash registers */
265 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
266 if (retval != ERROR_OK)
267 return retval;
268
269 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
270 if (retval != ERROR_OK)
271 return retval;
272
273 /* unlock option flash registers */
274 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
275 if (retval != ERROR_OK)
276 return retval;
277 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
278 if (retval != ERROR_OK)
279 return retval;
280
281 /* erase option bytes */
282 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
283 if (retval != ERROR_OK)
284 return retval;
285 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
286 if (retval != ERROR_OK)
287 return retval;
288
289 retval = stm32x_wait_status_busy(bank, 10);
290 if (retval != ERROR_OK)
291 return retval;
292
293 /* clear readout protection and complementary option bytes
294 * this will also force a device unlock if set */
295 stm32x_info->option_bytes.RDP = 0x5AA5;
296
297 return ERROR_OK;
298 }
299
300 static int stm32x_write_options(struct flash_bank *bank)
301 {
302 struct stm32x_flash_bank *stm32x_info = NULL;
303 struct target *target = bank->target;
304
305 stm32x_info = bank->driver_priv;
306
307 /* unlock flash registers */
308 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
309 if (retval != ERROR_OK)
310 return retval;
311 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
312 if (retval != ERROR_OK)
313 return retval;
314
315 /* unlock option flash registers */
316 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
317 if (retval != ERROR_OK)
318 return retval;
319 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
320 if (retval != ERROR_OK)
321 return retval;
322
323 /* program option bytes */
324 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
325 if (retval != ERROR_OK)
326 return retval;
327
328 /* write user option byte */
329 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
330 if (retval != ERROR_OK)
331 return retval;
332
333 retval = stm32x_wait_status_busy(bank, 10);
334 if (retval != ERROR_OK)
335 return retval;
336
337 /* write protection byte 1 */
338 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
339 if (retval != ERROR_OK)
340 return retval;
341
342 retval = stm32x_wait_status_busy(bank, 10);
343 if (retval != ERROR_OK)
344 return retval;
345
346 /* write protection byte 2 */
347 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
348 if (retval != ERROR_OK)
349 return retval;
350
351 retval = stm32x_wait_status_busy(bank, 10);
352 if (retval != ERROR_OK)
353 return retval;
354
355 /* write protection byte 3 */
356 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
357 if (retval != ERROR_OK)
358 return retval;
359
360 retval = stm32x_wait_status_busy(bank, 10);
361 if (retval != ERROR_OK)
362 return retval;
363
364 /* write protection byte 4 */
365 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
366 if (retval != ERROR_OK)
367 return retval;
368
369 retval = stm32x_wait_status_busy(bank, 10);
370 if (retval != ERROR_OK)
371 return retval;
372
373 /* write readout protection bit */
374 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
375 if (retval != ERROR_OK)
376 return retval;
377
378 retval = stm32x_wait_status_busy(bank, 10);
379 if (retval != ERROR_OK)
380 return retval;
381
382 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
383 if (retval != ERROR_OK)
384 return retval;
385
386 return ERROR_OK;
387 }
388
389 static int stm32x_protect_check(struct flash_bank *bank)
390 {
391 struct target *target = bank->target;
392 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
393
394 uint32_t protection;
395 int i, s;
396 int num_bits;
397 int set;
398
399 if (target->state != TARGET_HALTED)
400 {
401 LOG_ERROR("Target not halted");
402 return ERROR_TARGET_NOT_HALTED;
403 }
404
405 int retval = stm32x_check_operation_supported(bank);
406 if (ERROR_OK != retval)
407 return retval;
408
409 /* medium density - each bit refers to a 4bank protection
410 * high density - each bit refers to a 2bank protection */
411 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
412 if (retval != ERROR_OK)
413 return retval;
414
415 /* medium density - each protection bit is for 4 * 1K pages
416 * high density - each protection bit is for 2 * 2K pages */
417 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
418
419 if (stm32x_info->ppage_size == 2)
420 {
421 /* high density flash/connectivity line protection */
422
423 set = 1;
424
425 if (protection & (1 << 31))
426 set = 0;
427
428 /* bit 31 controls sector 62 - 255 protection for high density
429 * bit 31 controls sector 62 - 127 protection for connectivity line */
430 for (s = 62; s < bank->num_sectors; s++)
431 {
432 bank->sectors[s].is_protected = set;
433 }
434
435 if (bank->num_sectors > 61)
436 num_bits = 31;
437
438 for (i = 0; i < num_bits; i++)
439 {
440 set = 1;
441
442 if (protection & (1 << i))
443 set = 0;
444
445 for (s = 0; s < stm32x_info->ppage_size; s++)
446 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
447 }
448 }
449 else
450 {
451 /* low/medium density flash protection */
452 for (i = 0; i < num_bits; i++)
453 {
454 set = 1;
455
456 if (protection & (1 << i))
457 set = 0;
458
459 for (s = 0; s < stm32x_info->ppage_size; s++)
460 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
461 }
462 }
463
464 return ERROR_OK;
465 }
466
467 static int stm32x_erase(struct flash_bank *bank, int first, int last)
468 {
469 struct target *target = bank->target;
470 int i;
471
472 if (bank->target->state != TARGET_HALTED)
473 {
474 LOG_ERROR("Target not halted");
475 return ERROR_TARGET_NOT_HALTED;
476 }
477
478 if ((first == 0) && (last == (bank->num_sectors - 1)))
479 {
480 return stm32x_mass_erase(bank);
481 }
482
483 /* unlock flash registers */
484 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
485 if (retval != ERROR_OK)
486 return retval;
487 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
488 if (retval != ERROR_OK)
489 return retval;
490
491 for (i = first; i <= last; i++)
492 {
493 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
494 if (retval != ERROR_OK)
495 return retval;
496 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
497 bank->base + bank->sectors[i].offset);
498 if (retval != ERROR_OK)
499 return retval;
500 retval = target_write_u32(target,
501 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
502 if (retval != ERROR_OK)
503 return retval;
504
505 retval = stm32x_wait_status_busy(bank, 100);
506 if (retval != ERROR_OK)
507 return retval;
508
509 bank->sectors[i].is_erased = 1;
510 }
511
512 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
513 if (retval != ERROR_OK)
514 return retval;
515
516 return ERROR_OK;
517 }
518
519 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
520 {
521 struct stm32x_flash_bank *stm32x_info = NULL;
522 struct target *target = bank->target;
523 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
524 int i, reg, bit;
525 int status;
526 uint32_t protection;
527
528 stm32x_info = bank->driver_priv;
529
530 if (target->state != TARGET_HALTED)
531 {
532 LOG_ERROR("Target not halted");
533 return ERROR_TARGET_NOT_HALTED;
534 }
535
536 int retval = stm32x_check_operation_supported(bank);
537 if (ERROR_OK != retval)
538 return retval;
539
540 if ((first % stm32x_info->ppage_size) != 0)
541 {
542 LOG_WARNING("aligned start protect sector to a %d sector boundary",
543 stm32x_info->ppage_size);
544 first = first - (first % stm32x_info->ppage_size);
545 }
546 if (((last + 1) % stm32x_info->ppage_size) != 0)
547 {
548 LOG_WARNING("aligned end protect sector to a %d sector boundary",
549 stm32x_info->ppage_size);
550 last++;
551 last = last - (last % stm32x_info->ppage_size);
552 last--;
553 }
554
555 /* medium density - each bit refers to a 4bank protection
556 * high density - each bit refers to a 2bank protection */
557 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
558 if (retval != ERROR_OK)
559 return retval;
560
561 prot_reg[0] = (uint16_t)protection;
562 prot_reg[1] = (uint16_t)(protection >> 8);
563 prot_reg[2] = (uint16_t)(protection >> 16);
564 prot_reg[3] = (uint16_t)(protection >> 24);
565
566 if (stm32x_info->ppage_size == 2)
567 {
568 /* high density flash */
569
570 /* bit 7 controls sector 62 - 255 protection */
571 if (last > 61)
572 {
573 if (set)
574 prot_reg[3] &= ~(1 << 7);
575 else
576 prot_reg[3] |= (1 << 7);
577 }
578
579 if (first > 61)
580 first = 62;
581 if (last > 61)
582 last = 61;
583
584 for (i = first; i <= last; i++)
585 {
586 reg = (i / stm32x_info->ppage_size) / 8;
587 bit = (i / stm32x_info->ppage_size) - (reg * 8);
588
589 if (set)
590 prot_reg[reg] &= ~(1 << bit);
591 else
592 prot_reg[reg] |= (1 << bit);
593 }
594 }
595 else
596 {
597 /* medium density flash */
598 for (i = first; i <= last; i++)
599 {
600 reg = (i / stm32x_info->ppage_size) / 8;
601 bit = (i / stm32x_info->ppage_size) - (reg * 8);
602
603 if (set)
604 prot_reg[reg] &= ~(1 << bit);
605 else
606 prot_reg[reg] |= (1 << bit);
607 }
608 }
609
610 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
611 return status;
612
613 stm32x_info->option_bytes.protection[0] = prot_reg[0];
614 stm32x_info->option_bytes.protection[1] = prot_reg[1];
615 stm32x_info->option_bytes.protection[2] = prot_reg[2];
616 stm32x_info->option_bytes.protection[3] = prot_reg[3];
617
618 return stm32x_write_options(bank);
619 }
620
621 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
622 uint32_t offset, uint32_t count)
623 {
624 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
625 struct target *target = bank->target;
626 uint32_t buffer_size = 16384;
627 struct working_area *source;
628 uint32_t address = bank->base + offset;
629 struct reg_param reg_params[5];
630 struct armv7m_algorithm armv7m_info;
631 int retval = ERROR_OK;
632
633 /* see contrib/loaders/flash/stm32f1x.S for src */
634
635 static const uint8_t stm32x_flash_write_code[] = {
636 /* #define STM32_FLASH_CR_OFFSET 0x10 */
637 /* #define STM32_FLASH_SR_OFFSET 0x0C */
638 /* wait_fifo: */
639 0x16, 0x68, /* ldr r6, [r2, #0] */
640 0x00, 0x2e, /* cmp r6, #0 */
641 0x1a, 0xd0, /* beq exit */
642 0x55, 0x68, /* ldr r5, [r2, #4] */
643 0xb5, 0x42, /* cmp r5, r6 */
644 0xf9, 0xd0, /* beq wait_fifo */
645 0x01, 0x26, /* movs r6, #1 */
646 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
647 0x35, 0xf8, 0x02, 0x6b, /* ldrh r6, [r5], #2 */
648 0x24, 0xf8, 0x02, 0x6b, /* strh r6, [r4], #2 */
649 /* busy: */
650 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
651 0x16, 0xf0, 0x01, 0x0f, /* tst r6, #1 */
652 0xfb, 0xd1, /* bne busy */
653 0x16, 0xf0, 0x14, 0x0f, /* tst r6, #0x14 */
654 0x07, 0xd1, /* bne error */
655 0x9d, 0x42, /* cmp r5, r3 */
656 0x28, 0xbf, /* it cs */
657 0x02, 0xf1, 0x08, 0x05, /* addcs r5, r2, #8 */
658 0x55, 0x60, /* str r5, [r2, #4] */
659 0x01, 0x39, /* subs r1, r1, #1 */
660 0x19, 0xb1, /* cbz r1, exit */
661 0xe4, 0xe7, /* b wait_fifo */
662 /* error: */
663 0x00, 0x20, /* movs r0, #0 */
664 0xc2, 0xf8, 0x02, 0x00, /* str r0, [r2, #2] */
665 /* exit: */
666 0x30, 0x46, /* mov r0, r6 */
667 0x00, 0xbe, /* bkpt #0 */
668 };
669
670 /* flash write code */
671 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
672 &stm32x_info->write_algorithm) != ERROR_OK)
673 {
674 LOG_WARNING("no working area available, can't do block memory writes");
675 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
676 };
677
678 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
679 sizeof(stm32x_flash_write_code),
680 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
681 return retval;
682
683 /* memory buffer */
684 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
685 {
686 buffer_size /= 2;
687 buffer_size &= ~3UL; // Make sure it's 4 byte aligned
688 if (buffer_size <= 256)
689 {
690 /* if we already allocated the writing code, but failed to get a
691 * buffer, free the algorithm */
692 if (stm32x_info->write_algorithm)
693 target_free_working_area(target, stm32x_info->write_algorithm);
694
695 LOG_WARNING("no large enough working area available, can't do block memory writes");
696 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
697 }
698 };
699
700 /* Set up working area. First word is write pointer, second word is read pointer,
701 * rest is fifo data area. */
702 uint32_t wp_addr = source->address;
703 uint32_t rp_addr = source->address + 4;
704 uint32_t fifo_start_addr = source->address + 8;
705 uint32_t fifo_end_addr = source->address + source->size;
706
707 uint32_t wp = fifo_start_addr;
708 uint32_t rp = fifo_start_addr;
709
710 retval = target_write_u32(target, wp_addr, wp);
711 if (retval != ERROR_OK)
712 return retval;
713 retval = target_write_u32(target, rp_addr, rp);
714 if (retval != ERROR_OK)
715 return retval;
716
717 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
718 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
719 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
720 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
721 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
722
723 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
724 buf_set_u32(reg_params[1].value, 0, 32, count);
725 buf_set_u32(reg_params[2].value, 0, 32, source->address);
726 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
727 buf_set_u32(reg_params[4].value, 0, 32, address);
728
729 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
730 armv7m_info.core_mode = ARMV7M_MODE_ANY;
731
732 /* Start up algorithm on target and let it idle while writing the first chunk */
733 if ((retval = target_start_algorithm(target, 0, NULL, 5, reg_params,
734 stm32x_info->write_algorithm->address,
735 0,
736 &armv7m_info)) != ERROR_OK)
737 {
738 LOG_ERROR("error starting stm32x flash write algorithm");
739 goto cleanup;
740 }
741
742 while (count > 0)
743 {
744 retval = target_read_u32(target, rp_addr, &rp);
745 if (retval != ERROR_OK)
746 {
747 LOG_ERROR("failed to get read pointer");
748 break;
749 }
750
751 LOG_DEBUG("count 0x%"PRIx32" wp 0x%"PRIx32" rp 0x%"PRIx32, count, wp, rp);
752
753 if (rp == 0)
754 {
755 LOG_ERROR("flash write algorithm aborted by target");
756 retval = ERROR_FLASH_OPERATION_FAILED;
757 break;
758 }
759
760 if ((rp & 1) || rp < fifo_start_addr || rp >= fifo_end_addr)
761 {
762 LOG_ERROR("corrupted fifo read pointer 0x%"PRIx32, rp);
763 break;
764 }
765
766 /* Count the number of bytes available in the fifo without
767 * crossing the wrap around. Make sure to not fill it completely,
768 * because that would make wp == rp and that's the empty condition. */
769 uint32_t thisrun_bytes;
770 if (rp > wp)
771 thisrun_bytes = rp - wp - 2;
772 else if (rp > fifo_start_addr)
773 thisrun_bytes = fifo_end_addr - wp;
774 else
775 thisrun_bytes = fifo_end_addr - wp - 2;
776
777 if (thisrun_bytes == 0)
778 {
779 /* Throttle polling a bit if transfer is (much) faster than flash
780 * programming. The exact delay shouldn't matter as long as it's
781 * less than buffer size / flash speed. This is very unlikely to
782 * run when using high latency connections such as USB. */
783 alive_sleep(10);
784 continue;
785 }
786
787 /* Limit to the amount of data we actually want to write */
788 if (thisrun_bytes > count * 2)
789 thisrun_bytes = count * 2;
790
791 /* Write data to fifo */
792 retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
793 if (retval != ERROR_OK)
794 break;
795
796 /* Update counters and wrap write pointer */
797 buffer += thisrun_bytes;
798 count -= thisrun_bytes / 2;
799 wp += thisrun_bytes;
800 if (wp >= fifo_end_addr)
801 wp = fifo_start_addr;
802
803 /* Store updated write pointer to target */
804 retval = target_write_u32(target, wp_addr, wp);
805 if (retval != ERROR_OK)
806 break;
807 }
808
809 if (retval != ERROR_OK)
810 {
811 /* abort flash write algorithm on target */
812 target_write_u32(target, wp_addr, 0);
813 }
814
815 int retval2;
816 if ((retval2 = target_wait_algorithm(target, 0, NULL, 5, reg_params,
817 0,
818 10000,
819 &armv7m_info)) != ERROR_OK)
820 {
821 LOG_ERROR("error waiting for stm32x flash write algorithm");
822 retval = retval2;
823 }
824
825 if (retval == ERROR_FLASH_OPERATION_FAILED)
826 {
827 LOG_ERROR("flash write failed at address 0x%"PRIx32,
828 buf_get_u32(reg_params[4].value, 0, 32));
829
830 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR)
831 {
832 LOG_ERROR("flash memory not erased before writing");
833 /* Clear but report errors */
834 target_write_u32(target, STM32_FLASH_SR_B0, FLASH_PGERR);
835 }
836
837 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR)
838 {
839 LOG_ERROR("flash memory write protected");
840 /* Clear but report errors */
841 target_write_u32(target, STM32_FLASH_SR_B0, FLASH_WRPRTERR);
842 }
843 }
844
845 cleanup:
846 target_free_working_area(target, source);
847 target_free_working_area(target, stm32x_info->write_algorithm);
848
849 destroy_reg_param(&reg_params[0]);
850 destroy_reg_param(&reg_params[1]);
851 destroy_reg_param(&reg_params[2]);
852 destroy_reg_param(&reg_params[3]);
853 destroy_reg_param(&reg_params[4]);
854
855 return retval;
856 }
857
858 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
859 uint32_t offset, uint32_t count)
860 {
861 struct target *target = bank->target;
862 uint32_t words_remaining = (count / 2);
863 uint32_t bytes_remaining = (count & 0x00000001);
864 uint32_t address = bank->base + offset;
865 uint32_t bytes_written = 0;
866 int retval;
867
868 if (bank->target->state != TARGET_HALTED)
869 {
870 LOG_ERROR("Target not halted");
871 return ERROR_TARGET_NOT_HALTED;
872 }
873
874 if (offset & 0x1)
875 {
876 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
877 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
878 }
879
880 /* unlock flash registers */
881 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
882 if (retval != ERROR_OK)
883 return retval;
884 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
885 if (retval != ERROR_OK)
886 return retval;
887
888 /* multiple half words (2-byte) to be programmed? */
889 if (words_remaining > 0)
890 {
891 /* try using a block write */
892 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
893 {
894 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
895 {
896 /* if block write failed (no sufficient working area),
897 * we use normal (slow) single dword accesses */
898 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
899 }
900 }
901 else
902 {
903 buffer += words_remaining * 2;
904 address += words_remaining * 2;
905 words_remaining = 0;
906 }
907 }
908
909 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
910 return retval;
911
912 while (words_remaining > 0)
913 {
914 uint16_t value;
915 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
916
917 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
918 if (retval != ERROR_OK)
919 return retval;
920 retval = target_write_u16(target, address, value);
921 if (retval != ERROR_OK)
922 return retval;
923
924 retval = stm32x_wait_status_busy(bank, 5);
925 if (retval != ERROR_OK)
926 return retval;
927
928 bytes_written += 2;
929 words_remaining--;
930 address += 2;
931 }
932
933 if (bytes_remaining)
934 {
935 uint16_t value = 0xffff;
936 memcpy(&value, buffer + bytes_written, bytes_remaining);
937
938 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
939 if (retval != ERROR_OK)
940 return retval;
941 retval = target_write_u16(target, address, value);
942 if (retval != ERROR_OK)
943 return retval;
944
945 retval = stm32x_wait_status_busy(bank, 5);
946 if (retval != ERROR_OK)
947 return retval;
948 }
949
950 return target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
951 }
952
953 static int stm32x_probe(struct flash_bank *bank)
954 {
955 struct target *target = bank->target;
956 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
957 int i;
958 uint16_t flash_size_in_kb;
959 uint32_t device_id;
960 int page_size;
961 uint32_t base_address = 0x08000000;
962
963 stm32x_info->probed = 0;
964 stm32x_info->register_base = FLASH_REG_BASE_B0;
965
966 /* read stm32 device id register */
967 int retval = target_read_u32(target, 0xE0042000, &device_id);
968 if (retval != ERROR_OK)
969 return retval;
970 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
971
972 /* get flash size from target. */
973 retval = target_read_u16(target, 0x1FFFF7E0, &flash_size_in_kb);
974 if (retval != ERROR_OK)
975 {
976 LOG_WARNING("failed reading flash size, default to max target family");
977 /* failed reading flash size, default to max target family */
978 flash_size_in_kb = 0xffff;
979 }
980
981 if ((device_id & 0x7ff) == 0x410)
982 {
983 /* medium density - we have 1k pages
984 * 4 pages for a protection area */
985 page_size = 1024;
986 stm32x_info->ppage_size = 4;
987
988 /* check for early silicon */
989 if (flash_size_in_kb == 0xffff)
990 {
991 /* number of sectors incorrect on revA */
992 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
993 flash_size_in_kb = 128;
994 }
995 }
996 else if ((device_id & 0x7ff) == 0x412)
997 {
998 /* low density - we have 1k pages
999 * 4 pages for a protection area */
1000 page_size = 1024;
1001 stm32x_info->ppage_size = 4;
1002
1003 /* check for early silicon */
1004 if (flash_size_in_kb == 0xffff)
1005 {
1006 /* number of sectors incorrect on revA */
1007 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
1008 flash_size_in_kb = 32;
1009 }
1010 }
1011 else if ((device_id & 0x7ff) == 0x414)
1012 {
1013 /* high density - we have 2k pages
1014 * 2 pages for a protection area */
1015 page_size = 2048;
1016 stm32x_info->ppage_size = 2;
1017
1018 /* check for early silicon */
1019 if (flash_size_in_kb == 0xffff)
1020 {
1021 /* number of sectors incorrect on revZ */
1022 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
1023 flash_size_in_kb = 512;
1024 }
1025 }
1026 else if ((device_id & 0x7ff) == 0x418)
1027 {
1028 /* connectivity line density - we have 2k pages
1029 * 2 pages for a protection area */
1030 page_size = 2048;
1031 stm32x_info->ppage_size = 2;
1032
1033 /* check for early silicon */
1034 if (flash_size_in_kb == 0xffff)
1035 {
1036 /* number of sectors incorrect on revZ */
1037 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
1038 flash_size_in_kb = 256;
1039 }
1040 }
1041 else if ((device_id & 0x7ff) == 0x420)
1042 {
1043 /* value line density - we have 1k pages
1044 * 4 pages for a protection area */
1045 page_size = 1024;
1046 stm32x_info->ppage_size = 4;
1047
1048 /* check for early silicon */
1049 if (flash_size_in_kb == 0xffff)
1050 {
1051 /* number of sectors may be incorrrect on early silicon */
1052 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
1053 flash_size_in_kb = 128;
1054 }
1055 }
1056 else if ((device_id & 0x7ff) == 0x428)
1057 {
1058 /* value line High density - we have 2k pages
1059 * 4 pages for a protection area */
1060 page_size = 2048;
1061 stm32x_info->ppage_size = 4;
1062
1063 /* check for early silicon */
1064 if (flash_size_in_kb == 0xffff)
1065 {
1066 /* number of sectors may be incorrrect on early silicon */
1067 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
1068 flash_size_in_kb = 128;
1069 }
1070 }
1071
1072 else if ((device_id & 0x7ff) == 0x430)
1073 {
1074 /* xl line density - we have 2k pages
1075 * 2 pages for a protection area */
1076 page_size = 2048;
1077 stm32x_info->ppage_size = 2;
1078 stm32x_info->has_dual_banks = true;
1079
1080 /* check for early silicon */
1081 if (flash_size_in_kb == 0xffff)
1082 {
1083 /* number of sectors may be incorrrect on early silicon */
1084 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
1085 flash_size_in_kb = 1024;
1086 }
1087
1088 /* split reported size into matching bank */
1089 if (bank->base != 0x08080000)
1090 {
1091 /* bank 0 will be fixed 512k */
1092 flash_size_in_kb = 512;
1093 }
1094 else
1095 {
1096 flash_size_in_kb -= 512;
1097 /* bank1 also uses a register offset */
1098 stm32x_info->register_base = FLASH_REG_BASE_B1;
1099 base_address = 0x08080000;
1100 }
1101 }
1102 else
1103 {
1104 LOG_WARNING("Cannot identify target as a STM32 family.");
1105 return ERROR_FAIL;
1106 }
1107
1108 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
1109
1110 /* did we assign flash size? */
1111 assert(flash_size_in_kb != 0xffff);
1112
1113 /* calculate numbers of pages */
1114 int num_pages = flash_size_in_kb * 1024 / page_size;
1115
1116 /* check that calculation result makes sense */
1117 assert(num_pages > 0);
1118
1119 if (bank->sectors)
1120 {
1121 free(bank->sectors);
1122 bank->sectors = NULL;
1123 }
1124
1125 bank->base = base_address;
1126 bank->size = (num_pages * page_size);
1127 bank->num_sectors = num_pages;
1128 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1129
1130 for (i = 0; i < num_pages; i++)
1131 {
1132 bank->sectors[i].offset = i * page_size;
1133 bank->sectors[i].size = page_size;
1134 bank->sectors[i].is_erased = -1;
1135 bank->sectors[i].is_protected = 1;
1136 }
1137
1138 stm32x_info->probed = 1;
1139
1140 return ERROR_OK;
1141 }
1142
1143 static int stm32x_auto_probe(struct flash_bank *bank)
1144 {
1145 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1146 if (stm32x_info->probed)
1147 return ERROR_OK;
1148 return stm32x_probe(bank);
1149 }
1150
1151 #if 0
1152 COMMAND_HANDLER(stm32x_handle_part_id_command)
1153 {
1154 return ERROR_OK;
1155 }
1156 #endif
1157
1158 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1159 {
1160 struct target *target = bank->target;
1161 uint32_t device_id;
1162 int printed;
1163
1164 /* read stm32 device id register */
1165 int retval = target_read_u32(target, 0xE0042000, &device_id);
1166 if (retval != ERROR_OK)
1167 return retval;
1168
1169 if ((device_id & 0x7ff) == 0x410)
1170 {
1171 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1172 buf += printed;
1173 buf_size -= printed;
1174
1175 switch (device_id >> 16)
1176 {
1177 case 0x0000:
1178 snprintf(buf, buf_size, "A");
1179 break;
1180
1181 case 0x2000:
1182 snprintf(buf, buf_size, "B");
1183 break;
1184
1185 case 0x2001:
1186 snprintf(buf, buf_size, "Z");
1187 break;
1188
1189 case 0x2003:
1190 snprintf(buf, buf_size, "Y");
1191 break;
1192
1193 default:
1194 snprintf(buf, buf_size, "unknown");
1195 break;
1196 }
1197 }
1198 else if ((device_id & 0x7ff) == 0x412)
1199 {
1200 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1201 buf += printed;
1202 buf_size -= printed;
1203
1204 switch (device_id >> 16)
1205 {
1206 case 0x1000:
1207 snprintf(buf, buf_size, "A");
1208 break;
1209
1210 default:
1211 snprintf(buf, buf_size, "unknown");
1212 break;
1213 }
1214 }
1215 else if ((device_id & 0x7ff) == 0x414)
1216 {
1217 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1218 buf += printed;
1219 buf_size -= printed;
1220
1221 switch (device_id >> 16)
1222 {
1223 case 0x1000:
1224 snprintf(buf, buf_size, "A");
1225 break;
1226
1227 case 0x1001:
1228 snprintf(buf, buf_size, "Z");
1229 break;
1230
1231 default:
1232 snprintf(buf, buf_size, "unknown");
1233 break;
1234 }
1235 }
1236 else if ((device_id & 0x7ff) == 0x418)
1237 {
1238 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1239 buf += printed;
1240 buf_size -= printed;
1241
1242 switch (device_id >> 16)
1243 {
1244 case 0x1000:
1245 snprintf(buf, buf_size, "A");
1246 break;
1247
1248 case 0x1001:
1249 snprintf(buf, buf_size, "Z");
1250 break;
1251
1252 default:
1253 snprintf(buf, buf_size, "unknown");
1254 break;
1255 }
1256 }
1257 else if ((device_id & 0x7ff) == 0x420)
1258 {
1259 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1260 buf += printed;
1261 buf_size -= printed;
1262
1263 switch (device_id >> 16)
1264 {
1265 case 0x1000:
1266 snprintf(buf, buf_size, "A");
1267 break;
1268
1269 case 0x1001:
1270 snprintf(buf, buf_size, "Z");
1271 break;
1272
1273 default:
1274 snprintf(buf, buf_size, "unknown");
1275 break;
1276 }
1277 }
1278 else if ((device_id & 0x7ff) == 0x428)
1279 {
1280 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1281 buf += printed;
1282 buf_size -= printed;
1283
1284 switch (device_id >> 16)
1285 {
1286 case 0x1000:
1287 snprintf(buf, buf_size, "A");
1288 break;
1289
1290 case 0x1001:
1291 snprintf(buf, buf_size, "Z");
1292 break;
1293
1294 default:
1295 snprintf(buf, buf_size, "unknown");
1296 break;
1297 }
1298 }
1299 else if ((device_id & 0x7ff) == 0x430)
1300 {
1301 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1302 buf += printed;
1303 buf_size -= printed;
1304
1305 switch (device_id >> 16)
1306 {
1307 case 0x1000:
1308 snprintf(buf, buf_size, "A");
1309 break;
1310
1311 default:
1312 snprintf(buf, buf_size, "unknown");
1313 break;
1314 }
1315 }
1316 else
1317 {
1318 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1319 return ERROR_FAIL;
1320 }
1321
1322 return ERROR_OK;
1323 }
1324
1325 COMMAND_HANDLER(stm32x_handle_lock_command)
1326 {
1327 struct target *target = NULL;
1328 struct stm32x_flash_bank *stm32x_info = NULL;
1329
1330 if (CMD_ARGC < 1)
1331 {
1332 command_print(CMD_CTX, "stm32x lock <bank>");
1333 return ERROR_OK;
1334 }
1335
1336 struct flash_bank *bank;
1337 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1338 if (ERROR_OK != retval)
1339 return retval;
1340
1341 stm32x_info = bank->driver_priv;
1342
1343 target = bank->target;
1344
1345 if (target->state != TARGET_HALTED)
1346 {
1347 LOG_ERROR("Target not halted");
1348 return ERROR_TARGET_NOT_HALTED;
1349 }
1350
1351 retval = stm32x_check_operation_supported(bank);
1352 if (ERROR_OK != retval)
1353 return retval;
1354
1355 if (stm32x_erase_options(bank) != ERROR_OK)
1356 {
1357 command_print(CMD_CTX, "stm32x failed to erase options");
1358 return ERROR_OK;
1359 }
1360
1361 /* set readout protection */
1362 stm32x_info->option_bytes.RDP = 0;
1363
1364 if (stm32x_write_options(bank) != ERROR_OK)
1365 {
1366 command_print(CMD_CTX, "stm32x failed to lock device");
1367 return ERROR_OK;
1368 }
1369
1370 command_print(CMD_CTX, "stm32x locked");
1371
1372 return ERROR_OK;
1373 }
1374
1375 COMMAND_HANDLER(stm32x_handle_unlock_command)
1376 {
1377 struct target *target = NULL;
1378
1379 if (CMD_ARGC < 1)
1380 {
1381 command_print(CMD_CTX, "stm32x unlock <bank>");
1382 return ERROR_OK;
1383 }
1384
1385 struct flash_bank *bank;
1386 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1387 if (ERROR_OK != retval)
1388 return retval;
1389
1390 target = bank->target;
1391
1392 if (target->state != TARGET_HALTED)
1393 {
1394 LOG_ERROR("Target not halted");
1395 return ERROR_TARGET_NOT_HALTED;
1396 }
1397
1398 retval = stm32x_check_operation_supported(bank);
1399 if (ERROR_OK != retval)
1400 return retval;
1401
1402 if (stm32x_erase_options(bank) != ERROR_OK)
1403 {
1404 command_print(CMD_CTX, "stm32x failed to unlock device");
1405 return ERROR_OK;
1406 }
1407
1408 if (stm32x_write_options(bank) != ERROR_OK)
1409 {
1410 command_print(CMD_CTX, "stm32x failed to lock device");
1411 return ERROR_OK;
1412 }
1413
1414 command_print(CMD_CTX, "stm32x unlocked.\n"
1415 "INFO: a reset or power cycle is required "
1416 "for the new settings to take effect.");
1417
1418 return ERROR_OK;
1419 }
1420
1421 COMMAND_HANDLER(stm32x_handle_options_read_command)
1422 {
1423 uint32_t optionbyte;
1424 struct target *target = NULL;
1425 struct stm32x_flash_bank *stm32x_info = NULL;
1426
1427 if (CMD_ARGC < 1)
1428 {
1429 command_print(CMD_CTX, "stm32x options_read <bank>");
1430 return ERROR_OK;
1431 }
1432
1433 struct flash_bank *bank;
1434 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1435 if (ERROR_OK != retval)
1436 return retval;
1437
1438 stm32x_info = bank->driver_priv;
1439
1440 target = bank->target;
1441
1442 if (target->state != TARGET_HALTED)
1443 {
1444 LOG_ERROR("Target not halted");
1445 return ERROR_TARGET_NOT_HALTED;
1446 }
1447
1448 retval = stm32x_check_operation_supported(bank);
1449 if (ERROR_OK != retval)
1450 return retval;
1451
1452 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1453 if (retval != ERROR_OK)
1454 return retval;
1455 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1456
1457 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1458 command_print(CMD_CTX, "Option Byte Complement Error");
1459
1460 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1461 command_print(CMD_CTX, "Readout Protection On");
1462 else
1463 command_print(CMD_CTX, "Readout Protection Off");
1464
1465 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1466 command_print(CMD_CTX, "Software Watchdog");
1467 else
1468 command_print(CMD_CTX, "Hardware Watchdog");
1469
1470 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1471 command_print(CMD_CTX, "Stop: No reset generated");
1472 else
1473 command_print(CMD_CTX, "Stop: Reset generated");
1474
1475 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1476 command_print(CMD_CTX, "Standby: No reset generated");
1477 else
1478 command_print(CMD_CTX, "Standby: Reset generated");
1479
1480 if (stm32x_info->has_dual_banks)
1481 {
1482 if (buf_get_u32((uint8_t*)&optionbyte, OPT_BFB2, 1))
1483 command_print(CMD_CTX, "Boot: Bank 0");
1484 else
1485 command_print(CMD_CTX, "Boot: Bank 1");
1486 }
1487
1488 return ERROR_OK;
1489 }
1490
1491 COMMAND_HANDLER(stm32x_handle_options_write_command)
1492 {
1493 struct target *target = NULL;
1494 struct stm32x_flash_bank *stm32x_info = NULL;
1495 uint16_t optionbyte = 0xF8;
1496
1497 if (CMD_ARGC < 4)
1498 {
1499 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> "
1500 "<RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP> <BOOT0 | BOOT1>");
1501 return ERROR_OK;
1502 }
1503
1504 struct flash_bank *bank;
1505 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1506 if (ERROR_OK != retval)
1507 return retval;
1508
1509 stm32x_info = bank->driver_priv;
1510
1511 target = bank->target;
1512
1513 if (target->state != TARGET_HALTED)
1514 {
1515 LOG_ERROR("Target not halted");
1516 return ERROR_TARGET_NOT_HALTED;
1517 }
1518
1519 retval = stm32x_check_operation_supported(bank);
1520 if (ERROR_OK != retval)
1521 return retval;
1522
1523 /* REVISIT: ignores some options which we will display...
1524 * and doesn't insist on the specified syntax.
1525 */
1526
1527 /* OPT_RDWDGSW */
1528 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1529 {
1530 optionbyte |= (1 << 0);
1531 }
1532 else /* REVISIT must be "HWWDG" then ... */
1533 {
1534 optionbyte &= ~(1 << 0);
1535 }
1536
1537 /* OPT_RDRSTSTOP */
1538 if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1539 {
1540 optionbyte |= (1 << 1);
1541 }
1542 else /* REVISIT must be "RSTSTNDBY" then ... */
1543 {
1544 optionbyte &= ~(1 << 1);
1545 }
1546
1547 /* OPT_RDRSTSTDBY */
1548 if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1549 {
1550 optionbyte |= (1 << 2);
1551 }
1552 else /* REVISIT must be "RSTSTOP" then ... */
1553 {
1554 optionbyte &= ~(1 << 2);
1555 }
1556
1557 if (CMD_ARGC > 4 && stm32x_info->has_dual_banks)
1558 {
1559 /* OPT_BFB2 */
1560 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1561 {
1562 optionbyte |= (1 << 3);
1563 }
1564 else
1565 {
1566 optionbyte &= ~(1 << 3);
1567 }
1568 }
1569
1570 if (stm32x_erase_options(bank) != ERROR_OK)
1571 {
1572 command_print(CMD_CTX, "stm32x failed to erase options");
1573 return ERROR_OK;
1574 }
1575
1576 stm32x_info->option_bytes.user_options = optionbyte;
1577
1578 if (stm32x_write_options(bank) != ERROR_OK)
1579 {
1580 command_print(CMD_CTX, "stm32x failed to write options");
1581 return ERROR_OK;
1582 }
1583
1584 command_print(CMD_CTX, "stm32x write options complete.\n"
1585 "INFO: a reset or power cycle is required "
1586 "for the new settings to take effect.");
1587
1588 return ERROR_OK;
1589 }
1590
1591 static int stm32x_mass_erase(struct flash_bank *bank)
1592 {
1593 struct target *target = bank->target;
1594
1595 if (target->state != TARGET_HALTED)
1596 {
1597 LOG_ERROR("Target not halted");
1598 return ERROR_TARGET_NOT_HALTED;
1599 }
1600
1601 /* unlock option flash registers */
1602 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1603 if (retval != ERROR_OK)
1604 return retval;
1605 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1606 if (retval != ERROR_OK)
1607 return retval;
1608
1609 /* mass erase flash memory */
1610 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1611 if (retval != ERROR_OK)
1612 return retval;
1613 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
1614 if (retval != ERROR_OK)
1615 return retval;
1616
1617 retval = stm32x_wait_status_busy(bank, 100);
1618 if (retval != ERROR_OK)
1619 return retval;
1620
1621 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1622 if (retval != ERROR_OK)
1623 return retval;
1624
1625 return ERROR_OK;
1626 }
1627
1628 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1629 {
1630 int i;
1631
1632 if (CMD_ARGC < 1)
1633 {
1634 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1635 return ERROR_OK;
1636 }
1637
1638 struct flash_bank *bank;
1639 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1640 if (ERROR_OK != retval)
1641 return retval;
1642
1643 retval = stm32x_mass_erase(bank);
1644 if (retval == ERROR_OK)
1645 {
1646 /* set all sectors as erased */
1647 for (i = 0; i < bank->num_sectors; i++)
1648 {
1649 bank->sectors[i].is_erased = 1;
1650 }
1651
1652 command_print(CMD_CTX, "stm32x mass erase complete");
1653 }
1654 else
1655 {
1656 command_print(CMD_CTX, "stm32x mass erase failed");
1657 }
1658
1659 return retval;
1660 }
1661
1662 static const struct command_registration stm32x_exec_command_handlers[] = {
1663 {
1664 .name = "lock",
1665 .handler = stm32x_handle_lock_command,
1666 .mode = COMMAND_EXEC,
1667 .usage = "bank_id",
1668 .help = "Lock entire flash device.",
1669 },
1670 {
1671 .name = "unlock",
1672 .handler = stm32x_handle_unlock_command,
1673 .mode = COMMAND_EXEC,
1674 .usage = "bank_id",
1675 .help = "Unlock entire protected flash device.",
1676 },
1677 {
1678 .name = "mass_erase",
1679 .handler = stm32x_handle_mass_erase_command,
1680 .mode = COMMAND_EXEC,
1681 .usage = "bank_id",
1682 .help = "Erase entire flash device.",
1683 },
1684 {
1685 .name = "options_read",
1686 .handler = stm32x_handle_options_read_command,
1687 .mode = COMMAND_EXEC,
1688 .usage = "bank_id",
1689 .help = "Read and display device option byte.",
1690 },
1691 {
1692 .name = "options_write",
1693 .handler = stm32x_handle_options_write_command,
1694 .mode = COMMAND_EXEC,
1695 .usage = "bank_id ('SWWDG'|'HWWDG') "
1696 "('RSTSTNDBY'|'NORSTSTNDBY') "
1697 "('RSTSTOP'|'NORSTSTOP')",
1698 .help = "Replace bits in device option byte.",
1699 },
1700 COMMAND_REGISTRATION_DONE
1701 };
1702
1703 static const struct command_registration stm32x_command_handlers[] = {
1704 {
1705 .name = "stm32f1x",
1706 .mode = COMMAND_ANY,
1707 .help = "stm32f1x flash command group",
1708 .chain = stm32x_exec_command_handlers,
1709 },
1710 COMMAND_REGISTRATION_DONE
1711 };
1712
1713 struct flash_driver stm32f1x_flash = {
1714 .name = "stm32f1x",
1715 .commands = stm32x_command_handlers,
1716 .flash_bank_command = stm32x_flash_bank_command,
1717 .erase = stm32x_erase,
1718 .protect = stm32x_protect,
1719 .write = stm32x_write,
1720 .read = default_flash_read,
1721 .probe = stm32x_probe,
1722 .auto_probe = stm32x_auto_probe,
1723 .erase_check = default_flash_mem_blank_check,
1724 .protect_check = stm32x_protect_check,
1725 .info = get_stm32x_info,
1726 };