?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'dsp5680xx_cherry' into merging__dsp5680xx_cherry__into__ft2232_gpio_danger
[openocd/dsp568013.git] / src / target / arm_adi_v5.c
blobd6c0e2735fd79a093dc2aa23e45544514324d71b
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2011 Tomasz Boleslaw CEDRO *
14 * cederom@tlen.pl *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "arm.h"
76 #include "arm_adi_v5.h"
77 #include <helper/time_support.h>
78 #include <jtag/interface.h>
79
80 //We need to have access to information on other layers such as transport etc
81 //these are kept in global interface structure for now. Change ASAP.
82 extern struct jtag_interface *jtag_interface;
83
84 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
85
86 /*
87 uint32_t tar_block_size(uint32_t address)
88 Return the largest block starting at address that does not cross a tar block size alignment boundary
89 */
90 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
91 {
92 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
93 }
94
95 /***************************************************************************
96 * *
97 * DP and MEM-AP register access through APACC and DPACC *
98 * *
99 ***************************************************************************/
100
101 /**
102 * Select one of the APs connected to the specified DAP. The
103 * selection is implicitly used with future AP transactions.
104 * This is a NOP if the specified AP is already selected.
105 *
106 * @param dap The DAP
107 * @param apsel Number of the AP to (implicitly) use with further
108 * transactions. This normally identifies a MEM-AP.
109 */
110 void dap_ap_select(struct adiv5_dap *dap,uint8_t ap)
111 {
112 uint32_t new_ap = (ap << 24) & 0xFF000000;
113
114 if (new_ap != dap->ap_current)
115 {
116 dap->ap_current = new_ap;
117 /* Switching AP invalidates cached values.
118 * Values MUST BE UPDATED BEFORE AP ACCESS.
119 */
120 dap->ap_bank_value = -1;
121 dap->ap_csw_value = -1;
122 dap->ap_tar_value = -1;
123 }
124 }
125
126 /**
127 * Queue transactions setting up transfer parameters for the
128 * currently selected MEM-AP.
129 *
130 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
131 * initiate data reads or writes using memory or peripheral addresses.
132 * If the CSW is configured for it, the TAR may be automatically
133 * incremented after each transfer.
134 *
135 * @todo Rename to reflect it being specifically a MEM-AP function.
136 *
137 * @param dap The DAP connected to the MEM-AP.
138 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
139 * matches the cached value, the register is not changed.
140 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
141 * matches the cached address, the register is not changed.
142 *
143 * @return ERROR_OK if the transaction was properly queued, else a fault code.
144 */
145 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
146 {
147 int retval;
148
149 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
150 if (csw != dap->ap_csw_value)
151 {
152 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
153 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
154 if (retval != ERROR_OK)
155 return retval;
156 dap->ap_csw_value = csw;
157 }
158 if (tar != dap->ap_tar_value)
159 {
160 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
161 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
162 if (retval != ERROR_OK)
163 return retval;
164 dap->ap_tar_value = tar;
165 }
166 /* Disable TAR cache when autoincrementing */
167 if (csw & CSW_ADDRINC_MASK)
168 dap->ap_tar_value = -1;
169 return ERROR_OK;
170 }
171
172 /**
173 * Asynchronous (queued) read of a word from memory or a system register.
174 *
175 * @param dap The DAP connected to the MEM-AP performing the read.
176 * @param address Address of the 32-bit word to read; it must be
177 * readable by the currently selected MEM-AP.
178 * @param value points to where the word will be stored when the
179 * transaction queue is flushed (assuming no errors).
180 *
181 * @return ERROR_OK for success. Otherwise a fault code.
182 */
183 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
184 uint32_t *value)
185 {
186 int retval;
187
188 /* Use banked addressing (REG_BDx) to avoid some link traffic
189 * (updating TAR) when reading several consecutive addresses.
190 */
191 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
192 address & 0xFFFFFFF0);
193 if (retval != ERROR_OK)
194 return retval;
195
196 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
197 }
198
199 /**
200 * Synchronous read of a word from memory or a system register.
201 * As a side effect, this flushes any queued transactions.
202 *
203 * @param dap The DAP connected to the MEM-AP performing the read.
204 * @param address Address of the 32-bit word to read; it must be
205 * readable by the currently selected MEM-AP.
206 * @param value points to where the result will be stored.
207 *
208 * @return ERROR_OK for success; *value holds the result.
209 * Otherwise a fault code.
210 */
211 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
212 uint32_t *value)
213 {
214 int retval;
215
216 retval = mem_ap_read_u32(dap, address, value);
217 if (retval != ERROR_OK)
218 return retval;
219
220 return dap_run(dap);
221 }
222
223 /**
224 * Asynchronous (queued) write of a word to memory or a system register.
225 *
226 * @param dap The DAP connected to the MEM-AP.
227 * @param address Address to be written; it must be writable by
228 * the currently selected MEM-AP.
229 * @param value Word that will be written to the address when transaction
230 * queue is flushed (assuming no errors).
231 *
232 * @return ERROR_OK for success. Otherwise a fault code.
233 */
234 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
235 uint32_t value)
236 {
237 int retval;
238
239 /* Use banked addressing (REG_BDx) to avoid some link traffic
240 * (updating TAR) when writing several consecutive addresses.
241 */
242 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
243 address & 0xFFFFFFF0);
244 if (retval != ERROR_OK)
245 return retval;
246
247 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
248 value);
249 }
250
251 /**
252 * Synchronous write of a word to memory or a system register.
253 * As a side effect, this flushes any queued transactions.
254 *
255 * @param dap The DAP connected to the MEM-AP.
256 * @param address Address to be written; it must be writable by
257 * the currently selected MEM-AP.
258 * @param value Word that will be written.
259 *
260 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
261 */
262 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
263 uint32_t value)
264 {
265 int retval = mem_ap_write_u32(dap, address, value);
266
267 if (retval != ERROR_OK)
268 return retval;
269
270 return dap_run(dap);
271 }
272
273 /*****************************************************************************
274 * *
275 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
276 * *
277 * Write a buffer in target order (little endian) *
278 * *
279 *****************************************************************************/
280 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
281 {
282 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
283 uint32_t adr = address;
284 const uint8_t* pBuffer = buffer;
285
286 count >>= 2;
287 wcount = count;
288
289 /* if we have an unaligned access - reorder data */
290 if (adr & 0x3u)
291 {
292 for (writecount = 0; writecount < count; writecount++)
293 {
294 int i;
295 uint32_t outvalue;
296 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
297
298 for (i = 0; i < 4; i++)
299 {
300 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
301 outvalue >>= 8;
302 adr++;
303 }
304 pBuffer += sizeof(uint32_t);
305 }
306 }
307
308 while (wcount > 0)
309 {
310 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
311 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
312 if (wcount < blocksize)
313 blocksize = wcount;
314
315 /* handle unaligned data at 4k boundary */
316 if (blocksize == 0)
317 blocksize = 1;
318
319 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
320 if (retval != ERROR_OK)
321 return retval;
322
323 for (writecount = 0; writecount < blocksize; writecount++)
324 {
325 retval = dap_queue_ap_write(dap, AP_REG_DRW,
326 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
327 if (retval != ERROR_OK)
328 break;
329 }
330
331 if ((retval = dap_run(dap)) == ERROR_OK)
332 {
333 wcount = wcount - blocksize;
334 address = address + 4 * blocksize;
335 buffer = buffer + 4 * blocksize;
336 }
337 else
338 {
339 errorcount++;
340 }
341
342 if (errorcount > 1)
343 {
344 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
345 return retval;
346 }
347 }
348
349 return retval;
350 }
351
352 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
353 const uint8_t *buffer, int count, uint32_t address)
354 {
355 int retval = ERROR_OK;
356 int wcount, blocksize, writecount, i;
357
358 wcount = count >> 1;
359
360 while (wcount > 0)
361 {
362 int nbytes;
363
364 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
365 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
366
367 if (wcount < blocksize)
368 blocksize = wcount;
369
370 /* handle unaligned data at 4k boundary */
371 if (blocksize == 0)
372 blocksize = 1;
373
374 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
375 if (retval != ERROR_OK)
376 return retval;
377 writecount = blocksize;
378
379 do
380 {
381 nbytes = MIN((writecount << 1), 4);
382
383 if (nbytes < 4)
384 {
385 retval = mem_ap_write_buf_u16(dap, buffer,
386 nbytes, address);
387 if (retval != ERROR_OK)
388 {
389 LOG_WARNING("Block write error address "
390 "0x%" PRIx32 ", count 0x%x",
391 address, count);
392 return retval;
393 }
394
395 address += nbytes >> 1;
396 }
397 else
398 {
399 uint32_t outvalue;
400 memcpy(&outvalue, buffer, sizeof(uint32_t));
401
402 for (i = 0; i < nbytes; i++)
403 {
404 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
405 outvalue >>= 8;
406 address++;
407 }
408
409 memcpy(&outvalue, buffer, sizeof(uint32_t));
410 retval = dap_queue_ap_write(dap,
411 AP_REG_DRW, outvalue);
412 if (retval != ERROR_OK)
413 break;
414
415 if ((retval = dap_run(dap)) != ERROR_OK)
416 {
417 LOG_WARNING("Block write error address "
418 "0x%" PRIx32 ", count 0x%x",
419 address, count);
420 return retval;
421 }
422 }
423
424 buffer += nbytes >> 1;
425 writecount -= nbytes >> 1;
426
427 } while (writecount);
428 wcount -= blocksize;
429 }
430
431 return retval;
432 }
433
434 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
435 {
436 int retval = ERROR_OK;
437
438 if (count >= 4)
439 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
440
441 while (count > 0)
442 {
443 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
444 if (retval != ERROR_OK)
445 return retval;
446 uint16_t svalue;
447 memcpy(&svalue, buffer, sizeof(uint16_t));
448 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
449 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
450 if (retval != ERROR_OK)
451 break;
452
453 retval = dap_run(dap);
454 if (retval != ERROR_OK)
455 break;
456
457 count -= 2;
458 address += 2;
459 buffer += 2;
460 }
461
462 return retval;
463 }
464
465 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
466 const uint8_t *buffer, int count, uint32_t address)
467 {
468 int retval = ERROR_OK;
469 int wcount, blocksize, writecount, i;
470
471 wcount = count;
472
473 while (wcount > 0)
474 {
475 int nbytes;
476
477 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
478 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
479
480 if (wcount < blocksize)
481 blocksize = wcount;
482
483 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
484 if (retval != ERROR_OK)
485 return retval;
486 writecount = blocksize;
487
488 do
489 {
490 nbytes = MIN(writecount, 4);
491
492 if (nbytes < 4)
493 {
494 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
495 if (retval != ERROR_OK)
496 {
497 LOG_WARNING("Block write error address "
498 "0x%" PRIx32 ", count 0x%x",
499 address, count);
500 return retval;
501 }
502
503 address += nbytes;
504 }
505 else
506 {
507 uint32_t outvalue;
508 memcpy(&outvalue, buffer, sizeof(uint32_t));
509
510 for (i = 0; i < nbytes; i++)
511 {
512 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
513 outvalue >>= 8;
514 address++;
515 }
516
517 memcpy(&outvalue, buffer, sizeof(uint32_t));
518 retval = dap_queue_ap_write(dap,
519 AP_REG_DRW, outvalue);
520 if (retval != ERROR_OK)
521 break;
522
523 if ((retval = dap_run(dap)) != ERROR_OK)
524 {
525 LOG_WARNING("Block write error address "
526 "0x%" PRIx32 ", count 0x%x",
527 address, count);
528 return retval;
529 }
530 }
531
532 buffer += nbytes;
533 writecount -= nbytes;
534
535 } while (writecount);
536 wcount -= blocksize;
537 }
538
539 return retval;
540 }
541
542 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
543 {
544 int retval = ERROR_OK;
545
546 if (count >= 4)
547 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
548
549 while (count > 0)
550 {
551 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
552 if (retval != ERROR_OK)
553 return retval;
554 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
555 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
556 if (retval != ERROR_OK)
557 break;
558
559 retval = dap_run(dap);
560 if (retval != ERROR_OK)
561 break;
562
563 count--;
564 address++;
565 buffer++;
566 }
567
568 return retval;
569 }
570
571 /* FIXME don't import ... this is a temporary workaround for the
572 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
573 */
574 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
575 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
576 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
577
578 /**
579 * Synchronously read a block of 32-bit words into a buffer
580 * @param dap The DAP connected to the MEM-AP.
581 * @param buffer where the words will be stored (in host byte order).
582 * @param count How many words to read.
583 * @param address Memory address from which to read words; all the
584 * words must be readable by the currently selected MEM-AP.
585 */
586 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
587 int count, uint32_t address)
588 {
589 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
590 uint32_t adr = address;
591 uint8_t* pBuffer = buffer;
592
593 count >>= 2;
594 wcount = count;
595
596 while (wcount > 0)
597 {
598 /* Adjust to read blocks within boundaries aligned to the
599 * TAR autoincrement size (at least 2^10). Autoincrement
600 * mode avoids an extra per-word roundtrip to update TAR.
601 */
602 blocksize = max_tar_block_size(dap->tar_autoincr_block,
603 address);
604 if (wcount < blocksize)
605 blocksize = wcount;
606
607 /* handle unaligned data at 4k boundary */
608 if (blocksize == 0)
609 blocksize = 1;
610
611 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
612 address);
613 if (retval != ERROR_OK)
614 return retval;
615
616 /* FIXME remove these three calls to adi_jtag_dp_scan(),
617 * so this routine becomes transport-neutral. Be careful
618 * not to cause performance problems with JTAG; would it
619 * suffice to loop over dap_queue_ap_read(), or would that
620 * be slower when JTAG is the chosen transport?
621 */
622
623 /* Scan out first read */
624 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
625 DPAP_READ, 0, NULL, NULL);
626 if (retval != ERROR_OK)
627 return retval;
628 for (readcount = 0; readcount < blocksize - 1; readcount++)
629 {
630 /* Scan out next read; scan in posted value for the
631 * previous one. Assumes read is acked "OK/FAULT",
632 * and CTRL_STAT says that meant "OK".
633 */
634 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
635 DPAP_READ, 0, buffer + 4 * readcount,
636 &dap->ack);
637 if (retval != ERROR_OK)
638 return retval;
639 }
640
641 /* Scan in last posted value; RDBUFF has no other effect,
642 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
643 */
644 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
645 DPAP_READ, 0, buffer + 4 * readcount,
646 &dap->ack);
647 if (retval != ERROR_OK)
648 return retval;
649
650 retval = dap_run(dap);
651 if (retval != ERROR_OK)
652 {
653 errorcount++;
654 if (errorcount <= 1)
655 {
656 /* try again */
657 continue;
658 }
659 LOG_WARNING("Block read error address 0x%" PRIx32, address);
660 return retval;
661 }
662 wcount = wcount - blocksize;
663 address += 4 * blocksize;
664 buffer += 4 * blocksize;
665 }
666
667 /* if we have an unaligned access - reorder data */
668 if (adr & 0x3u)
669 {
670 for (readcount = 0; readcount < count; readcount++)
671 {
672 int i;
673 uint32_t data;
674 memcpy(&data, pBuffer, sizeof(uint32_t));
675
676 for (i = 0; i < 4; i++)
677 {
678 *((uint8_t*)pBuffer) =
679 (data >> 8 * (adr & 0x3));
680 pBuffer++;
681 adr++;
682 }
683 }
684 }
685
686 return retval;
687 }
688
689 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
690 uint8_t *buffer, int count, uint32_t address)
691 {
692 uint32_t invalue;
693 int retval = ERROR_OK;
694 int wcount, blocksize, readcount, i;
695
696 wcount = count >> 1;
697
698 while (wcount > 0)
699 {
700 int nbytes;
701
702 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
703 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
704 if (wcount < blocksize)
705 blocksize = wcount;
706
707 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
708 if (retval != ERROR_OK)
709 return retval;
710
711 /* handle unaligned data at 4k boundary */
712 if (blocksize == 0)
713 blocksize = 1;
714 readcount = blocksize;
715
716 do
717 {
718 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
719 if (retval != ERROR_OK)
720 return retval;
721 if ((retval = dap_run(dap)) != ERROR_OK)
722 {
723 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
724 return retval;
725 }
726
727 nbytes = MIN((readcount << 1), 4);
728
729 for (i = 0; i < nbytes; i++)
730 {
731 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
732 buffer++;
733 address++;
734 }
735
736 readcount -= (nbytes >> 1);
737 } while (readcount);
738 wcount -= blocksize;
739 }
740
741 return retval;
742 }
743
744 /**
745 * Synchronously read a block of 16-bit halfwords into a buffer
746 * @param dap The DAP connected to the MEM-AP.
747 * @param buffer where the halfwords will be stored (in host byte order).
748 * @param count How many halfwords to read.
749 * @param address Memory address from which to read words; all the
750 * words must be readable by the currently selected MEM-AP.
751 */
752 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
753 int count, uint32_t address)
754 {
755 uint32_t invalue, i;
756 int retval = ERROR_OK;
757
758 if (count >= 4)
759 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
760
761 while (count > 0)
762 {
763 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
764 if (retval != ERROR_OK)
765 return retval;
766 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
767 if (retval != ERROR_OK)
768 break;
769
770 retval = dap_run(dap);
771 if (retval != ERROR_OK)
772 break;
773
774 if (address & 0x1)
775 {
776 for (i = 0; i < 2; i++)
777 {
778 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
779 buffer++;
780 address++;
781 }
782 }
783 else
784 {
785 uint16_t svalue = (invalue >> 8 * (address & 0x3));
786 memcpy(buffer, &svalue, sizeof(uint16_t));
787 address += 2;
788 buffer += 2;
789 }
790 count -= 2;
791 }
792
793 return retval;
794 }
795
796 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
797 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
798 *
799 * The solution is to arrange for a large out/in scan in this loop and
800 * and convert data afterwards.
801 */
802 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
803 uint8_t *buffer, int count, uint32_t address)
804 {
805 uint32_t invalue;
806 int retval = ERROR_OK;
807 int wcount, blocksize, readcount, i;
808
809 wcount = count;
810
811 while (wcount > 0)
812 {
813 int nbytes;
814
815 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
816 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
817
818 if (wcount < blocksize)
819 blocksize = wcount;
820
821 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
822 if (retval != ERROR_OK)
823 return retval;
824 readcount = blocksize;
825
826 do
827 {
828 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
829 if (retval != ERROR_OK)
830 return retval;
831 if ((retval = dap_run(dap)) != ERROR_OK)
832 {
833 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
834 return retval;
835 }
836
837 nbytes = MIN(readcount, 4);
838
839 for (i = 0; i < nbytes; i++)
840 {
841 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
842 buffer++;
843 address++;
844 }
845
846 readcount -= nbytes;
847 } while (readcount);
848 wcount -= blocksize;
849 }
850
851 return retval;
852 }
853
854 /**
855 * Synchronously read a block of bytes into a buffer
856 * @param dap The DAP connected to the MEM-AP.
857 * @param buffer where the bytes will be stored.
858 * @param count How many bytes to read.
859 * @param address Memory address from which to read data; all the
860 * data must be readable by the currently selected MEM-AP.
861 */
862 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
863 int count, uint32_t address)
864 {
865 uint32_t invalue;
866 int retval = ERROR_OK;
867
868 if (count >= 4)
869 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
870
871 while (count > 0)
872 {
873 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
874 if (retval != ERROR_OK)
875 return retval;
876 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
877 if (retval != ERROR_OK)
878 return retval;
879 retval = dap_run(dap);
880 if (retval != ERROR_OK)
881 break;
882
883 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
884 count--;
885 address++;
886 buffer++;
887 }
888
889 return retval;
890 }
891
892 /*--------------------------------------------------------------------*/
893 /* Wrapping function with selection of AP */
894 /*--------------------------------------------------------------------*/
895 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
896 uint32_t address, uint32_t *value)
897 {
898 dap_ap_select(swjdp, ap);
899 return mem_ap_read_u32(swjdp, address, value);
900 }
901
902 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
903 uint32_t address, uint32_t value)
904 {
905 dap_ap_select(swjdp, ap);
906 return mem_ap_write_u32(swjdp, address, value);
907 }
908
909 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
910 uint32_t address, uint32_t *value)
911 {
912 dap_ap_select(swjdp, ap);
913 return mem_ap_read_atomic_u32(swjdp, address, value);
914 }
915
916 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
917 uint32_t address, uint32_t value)
918 {
919 dap_ap_select(swjdp, ap);
920 return mem_ap_write_atomic_u32(swjdp, address, value);
921 }
922
923 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
924 uint8_t *buffer, int count, uint32_t address)
925 {
926 dap_ap_select(swjdp, ap);
927 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
928 }
929
930 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
931 uint8_t *buffer, int count, uint32_t address)
932 {
933 dap_ap_select(swjdp, ap);
934 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
935 }
936
937 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
938 uint8_t *buffer, int count, uint32_t address)
939 {
940 dap_ap_select(swjdp, ap);
941 return mem_ap_read_buf_u32(swjdp, buffer, count, address);
942 }
943
944 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
945 const uint8_t *buffer, int count, uint32_t address)
946 {
947 dap_ap_select(swjdp, ap);
948 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
949 }
950
951 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
952 const uint8_t *buffer, int count, uint32_t address)
953 {
954 dap_ap_select(swjdp, ap);
955 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
956 }
957
958 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
959 const uint8_t *buffer, int count, uint32_t address)
960 {
961 dap_ap_select(swjdp, ap);
962 return mem_ap_write_buf_u32(swjdp, buffer, count, address);
963 }
964
965 #define MDM_REG_STAT 0x00
966 #define MDM_REG_CTRL 0x04
967 #define MDM_REG_ID 0xfc
968
969 #define MDM_STAT_FMEACK (1<<0)
970 #define MDM_STAT_FREADY (1<<1)
971 #define MDM_STAT_SYSSEC (1<<2)
972 #define MDM_STAT_SYSRES (1<<3)
973 #define MDM_STAT_FMEEN (1<<5)
974 #define MDM_STAT_BACKDOOREN (1<<6)
975 #define MDM_STAT_LPEN (1<<7)
976 #define MDM_STAT_VLPEN (1<<8)
977 #define MDM_STAT_LLSMODEXIT (1<<9)
978 #define MDM_STAT_VLLSXMODEXIT (1<<10)
979 #define MDM_STAT_CORE_HALTED (1<<16)
980 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
981 #define MDM_STAT_CORESLEEPING (1<<18)
982
983 #define MEM_CTRL_FMEIP (1<<0)
984 #define MEM_CTRL_DBG_DIS (1<<1)
985 #define MEM_CTRL_DBG_REQ (1<<2)
986 #define MEM_CTRL_SYS_RES_REQ (1<<3)
987 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
988 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
989 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
990 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
991
992 /**
993 *
994 */
995 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
996 {
997 uint32_t val;
998 int retval;
999 enum reset_types jtag_reset_config = jtag_get_reset_config();
1000
1001 dap_ap_select(dap, 1);
1002
1003 /* first check mdm-ap id register */
1004 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
1005 if (retval != ERROR_OK)
1006 return retval;
1007 dap_run(dap);
1008
1009 if ( val != 0x001C0000 )
1010 {
1011 LOG_DEBUG("id doesn't match %08X != 0x001C0000",val);
1012 dap_ap_select(dap, 0);
1013 return ERROR_FAIL;
1014 }
1015
1016 /* read and parse status register
1017 * it's important that the device is out of
1018 * reset here
1019 */
1020 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1021 if (retval != ERROR_OK)
1022 return retval;
1023 dap_run(dap);
1024
1025 LOG_DEBUG("MDM_REG_STAT %08X",val);
1026
1027 if ( (val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY) )
1028 {
1029 LOG_DEBUG("MDMAP: system is secured, masserase needed");
1030
1031 if ( !(val & MDM_STAT_FMEEN) )
1032 {
1033 LOG_DEBUG("MDMAP: masserase is disabled");
1034 }
1035 else
1036 {
1037 /* we need to assert reset */
1038 if ( jtag_reset_config & RESET_HAS_SRST )
1039 {
1040 /* default to asserting srst */
1041 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1042 {
1043 jtag_add_reset(1, 1);
1044 }
1045 else
1046 {
1047 jtag_add_reset(0, 1);
1048 }
1049 }
1050 else
1051 {
1052 LOG_DEBUG("SRST not configured");
1053 dap_ap_select(dap, 0);
1054 return ERROR_FAIL;
1055 }
1056
1057 while(1)
1058 {
1059 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
1060 if (retval != ERROR_OK)
1061 return retval;
1062 dap_run(dap);
1063 /* read status register and wait for ready */
1064 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1065 if (retval != ERROR_OK)
1066 return retval;
1067 dap_run(dap);
1068 LOG_DEBUG("MDM_REG_STAT %08X",val);
1069
1070 if ( (val&1))
1071 break;
1072 }
1073
1074 while(1)
1075 {
1076 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1077 if (retval != ERROR_OK)
1078 return retval;
1079 dap_run(dap);
1080 /* read status register */
1081 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1082 if (retval != ERROR_OK)
1083 return retval;
1084 dap_run(dap);
1085 LOG_DEBUG("MDM_REG_STAT %08X",val);
1086 /* read control register and wait for ready */
1087 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1088 if (retval != ERROR_OK)
1089 return retval;
1090 dap_run(dap);
1091 LOG_DEBUG("MDM_REG_CTRL %08X",val);
1092
1093 if ( val == 0x00 )
1094 break;
1095 }
1096 }
1097 }
1098
1099 dap_ap_select(dap, 0);
1100
1101 return ERROR_OK;
1102 }
1103
1104 /** */
1105 struct dap_syssec_filter {
1106 /** */
1107 uint32_t idcode;
1108 /** */
1109 int (*dap_init)(struct adiv5_dap *dap);
1110 };
1111
1112 /** */
1113 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1114 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1115 };
1116
1117
1118 /**
1119 *
1120 */
1121 int dap_syssec(struct adiv5_dap *dap)
1122 {
1123 unsigned int i;
1124 struct jtag_tap *tap;
1125
1126 for(i=0;i<sizeof(dap_syssec_filter_data);i++)
1127 {
1128 tap = dap->jtag_info->tap;
1129
1130 while (tap != NULL)
1131 {
1132 if ( tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode) )
1133 {
1134 LOG_DEBUG("DAP: mdmap_init for idcode: %08x",tap->idcode);
1135 dap_syssec_filter_data[i].dap_init(dap);
1136 }
1137 tap = tap->next_tap;
1138 }
1139 }
1140
1141 return ERROR_OK;
1142 }
1143
1144 /*--------------------------------------------------------------------------*/
1145
1146
1147 /* FIXME don't import ... just initialize as
1148 * part of DAP transport setup
1149 */
1150 extern const struct dap_ops jtag_dp_ops;
1151
1152 extern const struct dap_ops swd_dap_ops;
1153
1154 /*--------------------------------------------------------------------------*/
1155
1156 /**
1157 * Initialize a DAP. This sets up the power domains, prepares the DP
1158 * for further use, and arranges to use AP #0 for all AP operations
1159 * until dap_ap-select() changes that policy.
1160 *
1161 * @param dap The DAP being initialized.
1162 *
1163 * @todo Rename this. We also need an initialization scheme which account
1164 * for SWD transports not just JTAG; that will need to address differences
1165 * in layering. (JTAG is useful without any debug target; but not SWD.)
1166 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1167 */
1168 int ahbap_debugport_init(struct adiv5_dap *dap)
1169 {
1170 uint32_t ctrlstat;
1171 int cnt = 0;
1172 int retval;
1173
1174 LOG_DEBUG(" ");
1175
1176 /* JTAG-DP or SWJ-DP, in JTAG mode
1177 * ... for SWD mode this is patched as part
1178 * of link switchover
1179 *
1180 * if (!dap->ops)
1181 * dap->ops = &jtag_dp_ops;
1182 */
1183
1184 /** TC@20110601: Now we must select DAP function set based on transport type.
1185 * Transport selection is part of interface initialization.
1186 * Interface and target are initialized separately.
1187 * Transport fills global structure with functions to operate on target.
1188 * If transport SWD is not selected JTAG is set as default (old behavior).
1189 */
1190 #if 0
1191 struct jtag_interface *interface=jtag_interface; //OMFG!
1192
1193 if ((strncmp(interface->transport->name, "swd", 3)==0)) {
1194 LOG_INFO("Selecting SWD transport command set.");
1195 dap->ops = &swd_dap_ops;
1196 } else {
1197 LOG_INFO("Selecting JTAG transport command set.");
1198 dap->ops = &jtag_dp_ops;
1199 }
1200 #endif
1201
1202
1203
1204
1205
1206 /* Default MEM-AP setup.
1207 *
1208 * REVISIT AP #0 may be an inappropriate default for this.
1209 * Should we probe, or take a hint from the caller?
1210 * Presumably we can ignore the possibility of multiple APs.
1211 */
1212 dap->ap_current = !0;
1213 dap_ap_select(dap, 0);
1214
1215 /* DP initialization */
1216
1217 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1218 if (retval != ERROR_OK)
1219 return retval;
1220
1221 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1222 if (retval != ERROR_OK)
1223 return retval;
1224
1225 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1226 if (retval != ERROR_OK)
1227 return retval;
1228
1229 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1230 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1231 if (retval != ERROR_OK)
1232 return retval;
1233
1234 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1235 if (retval != ERROR_OK)
1236 return retval;
1237 if ((retval = dap_run(dap)) != ERROR_OK)
1238 return retval;
1239
1240 /* Check that we have debug power domains activated */
1241 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1242 {
1243 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1244 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1245 if (retval != ERROR_OK)
1246 return retval;
1247 if ((retval = dap_run(dap)) != ERROR_OK)
1248 return retval;
1249 alive_sleep(10);
1250 }
1251
1252 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1253 {
1254 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1255 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1256 if (retval != ERROR_OK)
1257 return retval;
1258 if ((retval = dap_run(dap)) != ERROR_OK)
1259 return retval;
1260 alive_sleep(10);
1261 }
1262
1263 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1264 if (retval != ERROR_OK)
1265 return retval;
1266 /* With debug power on we can activate OVERRUN checking */
1267 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1268 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1269 if (retval != ERROR_OK)
1270 return retval;
1271 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1272 if (retval != ERROR_OK)
1273 return retval;
1274
1275 dap_syssec(dap);
1276
1277 return ERROR_OK;
1278 }
1279
1280 /* CID interpretation -- see ARM IHI 0029B section 3
1281 * and ARM IHI 0031A table 13-3.
1282 */
1283 static const char *class_description[16] ={
1284 "Reserved", "ROM table", "Reserved", "Reserved",
1285 "Reserved", "Reserved", "Reserved", "Reserved",
1286 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1287 "Reserved", "OptimoDE DESS",
1288 "Generic IP component", "PrimeCell or System component"
1289 };
1290
1291 static bool
1292 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1293 {
1294 return cid3 == 0xb1 && cid2 == 0x05
1295 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1296 }
1297
1298 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1299 uint32_t *out_dbgbase, uint32_t *out_apid)
1300 {
1301 uint32_t ap_old;
1302 int retval;
1303 uint32_t dbgbase, apid;
1304
1305 /* AP address is in bits 31:24 of DP_SELECT */
1306 if (ap >= 256)
1307 return ERROR_INVALID_ARGUMENTS;
1308
1309 ap_old = dap->ap_current;
1310 dap_ap_select(dap, ap);
1311
1312 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1313 if (retval != ERROR_OK)
1314 return retval;
1315 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1316 if (retval != ERROR_OK)
1317 return retval;
1318 retval = dap_run(dap);
1319 if (retval != ERROR_OK)
1320 return retval;
1321
1322 /* Excavate the device ID code */
1323 struct jtag_tap *tap = dap->jtag_info->tap;
1324 while (tap != NULL) {
1325 if (tap->hasidcode)
1326 break;
1327 tap = tap->next_tap;
1328 }
1329 if (tap == NULL || !tap->hasidcode)
1330 return ERROR_OK;
1331
1332 dap_ap_select(dap, ap_old);
1333
1334 /* The asignment happens only here to prevent modification of these
1335 * values before they are certain. */
1336 *out_dbgbase = dbgbase;
1337 *out_apid = apid;
1338
1339 return ERROR_OK;
1340 }
1341
1342 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1343 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1344 {
1345 uint32_t ap_old;
1346 uint32_t romentry, entry_offset = 0, component_base, devtype;
1347 int retval = ERROR_FAIL;
1348
1349 if (ap >= 256)
1350 return ERROR_INVALID_ARGUMENTS;
1351
1352 ap_old = dap->ap_current;
1353 dap_ap_select(dap, ap);
1354
1355 do
1356 {
1357 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1358 entry_offset, &romentry);
1359 if (retval != ERROR_OK)
1360 return retval;
1361
1362 component_base = (dbgbase & 0xFFFFF000)
1363 + (romentry & 0xFFFFF000);
1364
1365 if (romentry & 0x1) {
1366 retval = mem_ap_read_atomic_u32(dap,
1367 (component_base & 0xfffff000) | 0xfcc,
1368 &devtype);
1369 if ((devtype & 0xff) == type) {
1370 *addr = component_base;
1371 retval = ERROR_OK;
1372 break;
1373 }
1374 }
1375 entry_offset += 4;
1376 } while (romentry > 0);
1377
1378 dap_ap_select(dap, ap_old);
1379
1380 return retval;
1381 }
1382
1383 static int dap_info_command(struct command_context *cmd_ctx,
1384 struct adiv5_dap *dap, int ap)
1385 {
1386 int retval;
1387 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1388 int romtable_present = 0;
1389 uint8_t mem_ap;
1390 uint32_t ap_old;
1391
1392 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1393 if (retval != ERROR_OK)
1394 return retval;
1395
1396 ap_old = dap->ap_current;
1397 dap_ap_select(dap, ap);
1398
1399 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1400 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1401 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1402 if (apid)
1403 {
1404 switch (apid&0x0F)
1405 {
1406 case 0:
1407 command_print(cmd_ctx, "\tType is JTAG-AP");
1408 break;
1409 case 1:
1410 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1411 break;
1412 case 2:
1413 command_print(cmd_ctx, "\tType is MEM-AP APB");
1414 break;
1415 default:
1416 command_print(cmd_ctx, "\tUnknown AP type");
1417 break;
1418 }
1419
1420 /* NOTE: a MEM-AP may have a single CoreSight component that's
1421 * not a ROM table ... or have no such components at all.
1422 */
1423 if (mem_ap)
1424 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1425 dbgbase);
1426 }
1427 else
1428 {
1429 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1430 }
1431
1432 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1433 if (romtable_present)
1434 {
1435 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1436 uint16_t entry_offset;
1437
1438 /* bit 16 of apid indicates a memory access port */
1439 if (dbgbase & 0x02)
1440 command_print(cmd_ctx, "\tValid ROM table present");
1441 else
1442 command_print(cmd_ctx, "\tROM table in legacy format");
1443
1444 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1445 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1446 if (retval != ERROR_OK)
1447 return retval;
1448 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1449 if (retval != ERROR_OK)
1450 return retval;
1451 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1452 if (retval != ERROR_OK)
1453 return retval;
1454 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1455 if (retval != ERROR_OK)
1456 return retval;
1457 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1458 if (retval != ERROR_OK)
1459 return retval;
1460 retval = dap_run(dap);
1461 if (retval != ERROR_OK)
1462 return retval;
1463
1464 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1465 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1466 ", CID2 0x%2.2x"
1467 ", CID1 0x%2.2x"
1468 ", CID0 0x%2.2x",
1469 (unsigned) cid3, (unsigned)cid2,
1470 (unsigned) cid1, (unsigned) cid0);
1471 if (memtype & 0x01)
1472 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1473 else
1474 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1475 "Dedicated debug bus.");
1476
1477 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1478 entry_offset = 0;
1479 do
1480 {
1481 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1482 if (retval != ERROR_OK)
1483 return retval;
1484 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1485 if (romentry&0x01)
1486 {
1487 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1488 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1489 uint32_t component_base;
1490 unsigned part_num;
1491 char *type, *full;
1492
1493 component_base = (dbgbase & 0xFFFFF000)
1494 + (romentry & 0xFFFFF000);
1495
1496 /* IDs are in last 4K section */
1497
1498
1499 retval = mem_ap_read_atomic_u32(dap,
1500 component_base + 0xFE0, &c_pid0);
1501 if (retval != ERROR_OK)
1502 return retval;
1503 c_pid0 &= 0xff;
1504 retval = mem_ap_read_atomic_u32(dap,
1505 component_base + 0xFE4, &c_pid1);
1506 if (retval != ERROR_OK)
1507 return retval;
1508 c_pid1 &= 0xff;
1509 retval = mem_ap_read_atomic_u32(dap,
1510 component_base + 0xFE8, &c_pid2);
1511 if (retval != ERROR_OK)
1512 return retval;
1513 c_pid2 &= 0xff;
1514 retval = mem_ap_read_atomic_u32(dap,
1515 component_base + 0xFEC, &c_pid3);
1516 if (retval != ERROR_OK)
1517 return retval;
1518 c_pid3 &= 0xff;
1519 retval = mem_ap_read_atomic_u32(dap,
1520 component_base + 0xFD0, &c_pid4);
1521 if (retval != ERROR_OK)
1522 return retval;
1523 c_pid4 &= 0xff;
1524
1525 retval = mem_ap_read_atomic_u32(dap,
1526 component_base + 0xFF0, &c_cid0);
1527 if (retval != ERROR_OK)
1528 return retval;
1529 c_cid0 &= 0xff;
1530 retval = mem_ap_read_atomic_u32(dap,
1531 component_base + 0xFF4, &c_cid1);
1532 if (retval != ERROR_OK)
1533 return retval;
1534 c_cid1 &= 0xff;
1535 retval = mem_ap_read_atomic_u32(dap,
1536 component_base + 0xFF8, &c_cid2);
1537 if (retval != ERROR_OK)
1538 return retval;
1539 c_cid2 &= 0xff;
1540 retval = mem_ap_read_atomic_u32(dap,
1541 component_base + 0xFFC, &c_cid3);
1542 if (retval != ERROR_OK)
1543 return retval;
1544 c_cid3 &= 0xff;
1545
1546
1547 command_print(cmd_ctx,
1548 "\t\tComponent base address 0x%" PRIx32
1549 ", start address 0x%" PRIx32,
1550 component_base,
1551 /* component may take multiple 4K pages */
1552 component_base - 0x1000*(c_pid4 >> 4));
1553 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1554 (int) (c_cid1 >> 4) & 0xf,
1555 /* See ARM IHI 0029B Table 3-3 */
1556 class_description[(c_cid1 >> 4) & 0xf]);
1557
1558 /* CoreSight component? */
1559 if (((c_cid1 >> 4) & 0x0f) == 9) {
1560 uint32_t devtype;
1561 unsigned minor;
1562 char *major = "Reserved", *subtype = "Reserved";
1563
1564 retval = mem_ap_read_atomic_u32(dap,
1565 (component_base & 0xfffff000) | 0xfcc,
1566 &devtype);
1567 if (retval != ERROR_OK)
1568 return retval;
1569 minor = (devtype >> 4) & 0x0f;
1570 switch (devtype & 0x0f) {
1571 case 0:
1572 major = "Miscellaneous";
1573 switch (minor) {
1574 case 0:
1575 subtype = "other";
1576 break;
1577 case 4:
1578 subtype = "Validation component";
1579 break;
1580 }
1581 break;
1582 case 1:
1583 major = "Trace Sink";
1584 switch (minor) {
1585 case 0:
1586 subtype = "other";
1587 break;
1588 case 1:
1589 subtype = "Port";
1590 break;
1591 case 2:
1592 subtype = "Buffer";
1593 break;
1594 }
1595 break;
1596 case 2:
1597 major = "Trace Link";
1598 switch (minor) {
1599 case 0:
1600 subtype = "other";
1601 break;
1602 case 1:
1603 subtype = "Funnel, router";
1604 break;
1605 case 2:
1606 subtype = "Filter";
1607 break;
1608 case 3:
1609 subtype = "FIFO, buffer";
1610 break;
1611 }
1612 break;
1613 case 3:
1614 major = "Trace Source";
1615 switch (minor) {
1616 case 0:
1617 subtype = "other";
1618 break;
1619 case 1:
1620 subtype = "Processor";
1621 break;
1622 case 2:
1623 subtype = "DSP";
1624 break;
1625 case 3:
1626 subtype = "Engine/Coprocessor";
1627 break;
1628 case 4:
1629 subtype = "Bus";
1630 break;
1631 }
1632 break;
1633 case 4:
1634 major = "Debug Control";
1635 switch (minor) {
1636 case 0:
1637 subtype = "other";
1638 break;
1639 case 1:
1640 subtype = "Trigger Matrix";
1641 break;
1642 case 2:
1643 subtype = "Debug Auth";
1644 break;
1645 }
1646 break;
1647 case 5:
1648 major = "Debug Logic";
1649 switch (minor) {
1650 case 0:
1651 subtype = "other";
1652 break;
1653 case 1:
1654 subtype = "Processor";
1655 break;
1656 case 2:
1657 subtype = "DSP";
1658 break;
1659 case 3:
1660 subtype = "Engine/Coprocessor";
1661 break;
1662 }
1663 break;
1664 }
1665 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1666 (unsigned) (devtype & 0xff),
1667 major, subtype);
1668 /* REVISIT also show 0xfc8 DevId */
1669 }
1670
1671 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1672 command_print(cmd_ctx,
1673 "\t\tCID3 0%2.2x"
1674 ", CID2 0%2.2x"
1675 ", CID1 0%2.2x"
1676 ", CID0 0%2.2x",
1677 (int) c_cid3,
1678 (int) c_cid2,
1679 (int)c_cid1,
1680 (int)c_cid0);
1681 command_print(cmd_ctx,
1682 "\t\tPeripheral ID[4..0] = hex "
1683 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1684 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1685 (int) c_pid1, (int) c_pid0);
1686
1687 /* Part number interpretations are from Cortex
1688 * core specs, the CoreSight components TRM
1689 * (ARM DDI 0314H), CoreSight System Design
1690 * Guide (ARM DGI 0012D) and ETM specs; also
1691 * from chip observation (e.g. TI SDTI).
1692 */
1693 part_num = (c_pid0 & 0xff);
1694 part_num |= (c_pid1 & 0x0f) << 8;
1695 switch (part_num) {
1696 case 0x000:
1697 type = "Cortex-M3 NVIC";
1698 full = "(Interrupt Controller)";
1699 break;
1700 case 0x001:
1701 type = "Cortex-M3 ITM";
1702 full = "(Instrumentation Trace Module)";
1703 break;
1704 case 0x002:
1705 type = "Cortex-M3 DWT";
1706 full = "(Data Watchpoint and Trace)";
1707 break;
1708 case 0x003:
1709 type = "Cortex-M3 FBP";
1710 full = "(Flash Patch and Breakpoint)";
1711 break;
1712 case 0x00d:
1713 type = "CoreSight ETM11";
1714 full = "(Embedded Trace)";
1715 break;
1716 // case 0x113: what?
1717 case 0x120: /* from OMAP3 memmap */
1718 type = "TI SDTI";
1719 full = "(System Debug Trace Interface)";
1720 break;
1721 case 0x343: /* from OMAP3 memmap */
1722 type = "TI DAPCTL";
1723 full = "";
1724 break;
1725 case 0x906:
1726 type = "Coresight CTI";
1727 full = "(Cross Trigger)";
1728 break;
1729 case 0x907:
1730 type = "Coresight ETB";
1731 full = "(Trace Buffer)";
1732 break;
1733 case 0x908:
1734 type = "Coresight CSTF";
1735 full = "(Trace Funnel)";
1736 break;
1737 case 0x910:
1738 type = "CoreSight ETM9";
1739 full = "(Embedded Trace)";
1740 break;
1741 case 0x912:
1742 type = "Coresight TPIU";
1743 full = "(Trace Port Interface Unit)";
1744 break;
1745 case 0x921:
1746 type = "Cortex-A8 ETM";
1747 full = "(Embedded Trace)";
1748 break;
1749 case 0x922:
1750 type = "Cortex-A8 CTI";
1751 full = "(Cross Trigger)";
1752 break;
1753 case 0x923:
1754 type = "Cortex-M3 TPIU";
1755 full = "(Trace Port Interface Unit)";
1756 break;
1757 case 0x924:
1758 type = "Cortex-M3 ETM";
1759 full = "(Embedded Trace)";
1760 break;
1761 case 0x930:
1762 type = "Cortex-R4 ETM";
1763 full = "(Embedded Trace)";
1764 break;
1765 case 0xc08:
1766 type = "Cortex-A8 Debug";
1767 full = "(Debug Unit)";
1768 break;
1769 default:
1770 type = "-*- unrecognized -*-";
1771 full = "";
1772 break;
1773 }
1774 command_print(cmd_ctx, "\t\tPart is %s %s",
1775 type, full);
1776 }
1777 else
1778 {
1779 if (romentry)
1780 command_print(cmd_ctx, "\t\tComponent not present");
1781 else
1782 command_print(cmd_ctx, "\t\tEnd of ROM table");
1783 }
1784 entry_offset += 4;
1785 } while (romentry > 0);
1786 }
1787 else
1788 {
1789 command_print(cmd_ctx, "\tNo ROM table present");
1790 }
1791 dap_ap_select(dap, ap_old);
1792
1793 return ERROR_OK;
1794 }
1795
1796 COMMAND_HANDLER(handle_dap_info_command)
1797 {
1798 struct target *target = get_current_target(CMD_CTX);
1799 struct arm *arm = target_to_arm(target);
1800 struct adiv5_dap *dap = arm->dap;
1801 uint32_t apsel;
1802
1803 switch (CMD_ARGC) {
1804 case 0:
1805 apsel = dap->apsel;
1806 break;
1807 case 1:
1808 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1809 break;
1810 default:
1811 return ERROR_COMMAND_SYNTAX_ERROR;
1812 }
1813
1814 return dap_info_command(CMD_CTX, dap, apsel);
1815 }
1816
1817 COMMAND_HANDLER(dap_baseaddr_command)
1818 {
1819 struct target *target = get_current_target(CMD_CTX);
1820 struct arm *arm = target_to_arm(target);
1821 struct adiv5_dap *dap = arm->dap;
1822
1823 uint32_t apsel, baseaddr;
1824 int retval;
1825
1826 switch (CMD_ARGC) {
1827 case 0:
1828 apsel = dap->apsel;
1829 break;
1830 case 1:
1831 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1832 /* AP address is in bits 31:24 of DP_SELECT */
1833 if (apsel >= 256)
1834 return ERROR_INVALID_ARGUMENTS;
1835 break;
1836 default:
1837 return ERROR_COMMAND_SYNTAX_ERROR;
1838 }
1839
1840 dap_ap_select(dap, apsel);
1841
1842 /* NOTE: assumes we're talking to a MEM-AP, which
1843 * has a base address. There are other kinds of AP,
1844 * though they're not common for now. This should
1845 * use the ID register to verify it's a MEM-AP.
1846 */
1847 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1848 if (retval != ERROR_OK)
1849 return retval;
1850 retval = dap_run(dap);
1851 if (retval != ERROR_OK)
1852 return retval;
1853
1854 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1855
1856 return retval;
1857 }
1858
1859 COMMAND_HANDLER(dap_memaccess_command)
1860 {
1861 struct target *target = get_current_target(CMD_CTX);
1862 struct arm *arm = target_to_arm(target);
1863 struct adiv5_dap *dap = arm->dap;
1864
1865 uint32_t memaccess_tck;
1866
1867 switch (CMD_ARGC) {
1868 case 0:
1869 memaccess_tck = dap->memaccess_tck;
1870 break;
1871 case 1:
1872 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1873 break;
1874 default:
1875 return ERROR_COMMAND_SYNTAX_ERROR;
1876 }
1877 dap->memaccess_tck = memaccess_tck;
1878
1879 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1880 dap->memaccess_tck);
1881
1882 return ERROR_OK;
1883 }
1884
1885 COMMAND_HANDLER(dap_apsel_command)
1886 {
1887 struct target *target = get_current_target(CMD_CTX);
1888 struct arm *arm = target_to_arm(target);
1889 struct adiv5_dap *dap = arm->dap;
1890
1891 uint32_t apsel, apid;
1892 int retval;
1893
1894 switch (CMD_ARGC) {
1895 case 0:
1896 apsel = 0;
1897 break;
1898 case 1:
1899 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1900 /* AP address is in bits 31:24 of DP_SELECT */
1901 if (apsel >= 256)
1902 return ERROR_INVALID_ARGUMENTS;
1903 break;
1904 default:
1905 return ERROR_COMMAND_SYNTAX_ERROR;
1906 }
1907
1908 dap->apsel = apsel;
1909 dap_ap_select(dap, apsel);
1910
1911 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1912 if (retval != ERROR_OK)
1913 return retval;
1914 retval = dap_run(dap);
1915 if (retval != ERROR_OK)
1916 return retval;
1917
1918 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1919 apsel, apid);
1920
1921 return retval;
1922 }
1923
1924 COMMAND_HANDLER(dap_apid_command)
1925 {
1926 struct target *target = get_current_target(CMD_CTX);
1927 struct arm *arm = target_to_arm(target);
1928 struct adiv5_dap *dap = arm->dap;
1929
1930 uint32_t apsel, apid;
1931 int retval;
1932
1933 switch (CMD_ARGC) {
1934 case 0:
1935 apsel = dap->apsel;
1936 break;
1937 case 1:
1938 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1939 /* AP address is in bits 31:24 of DP_SELECT */
1940 if (apsel >= 256)
1941 return ERROR_INVALID_ARGUMENTS;
1942 break;
1943 default:
1944 return ERROR_COMMAND_SYNTAX_ERROR;
1945 }
1946
1947 dap_ap_select(dap, apsel);
1948
1949 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1950 if (retval != ERROR_OK)
1951 return retval;
1952 retval = dap_run(dap);
1953 if (retval != ERROR_OK)
1954 return retval;
1955
1956 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1957
1958 return retval;
1959 }
1960
1961 static const struct command_registration dap_commands[] = {
1962 {
1963 .name = "info",
1964 .handler = handle_dap_info_command,
1965 .mode = COMMAND_EXEC,
1966 .help = "display ROM table for MEM-AP "
1967 "(default currently selected AP)",
1968 .usage = "[ap_num]",
1969 },
1970 {
1971 .name = "apsel",
1972 .handler = dap_apsel_command,
1973 .mode = COMMAND_EXEC,
1974 .help = "Set the currently selected AP (default 0) "
1975 "and display the result",
1976 .usage = "[ap_num]",
1977 },
1978 {
1979 .name = "apid",
1980 .handler = dap_apid_command,
1981 .mode = COMMAND_EXEC,
1982 .help = "return ID register from AP "
1983 "(default currently selected AP)",
1984 .usage = "[ap_num]",
1985 },
1986 {
1987 .name = "baseaddr",
1988 .handler = dap_baseaddr_command,
1989 .mode = COMMAND_EXEC,
1990 .help = "return debug base address from MEM-AP "
1991 "(default currently selected AP)",
1992 .usage = "[ap_num]",
1993 },
1994 {
1995 .name = "memaccess",
1996 .handler = dap_memaccess_command,
1997 .mode = COMMAND_EXEC,
1998 .help = "set/get number of extra tck for MEM-AP memory "
1999 "bus access [0-255]",
2000 .usage = "[cycles]",
2001 },
2002 COMMAND_REGISTRATION_DONE
2003 };
2004
2005 const struct command_registration dap_command_handlers[] = {
2006 {
2007 .name = "dap",
2008 .mode = COMMAND_EXEC,
2009 .help = "DAP command group",
2010 .chain = dap_commands,
2011 },
2012 COMMAND_REGISTRATION_DONE
2013 };
2014
2015