1 /***************************************************************************
2 * Copyright (C) 2011 by Rodrigo L. Rosa *
3 * rodrigorosa.LG@gmail.com *
5 * Based on dsp563xx_once.h written by Mathias Kuester *
6 * mkdorg@users.sourceforge.net *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "target_type.h"
29 #include "dsp5680xx.h"
31 #define err_check(retval,err_msg) if(retval != ERROR_OK){LOG_ERROR("%s: %d %s.",__FUNCTION__,__LINE__,err_msg);return retval;}
32 #define err_check_propagate(retval) if(retval!=ERROR_OK){return retval;}
34 int dsp5680xx_execute_queue(void){
36 retval
= jtag_execute_queue();
37 err_check_propagate(retval
);
41 static int dsp5680xx_drscan(struct target
* target
, uint8_t * data_to_shift_into_dr
, uint8_t * data_shifted_out_of_dr
, int len
){
42 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
45 // - data_to_shift_into_dr: This is the data that will be shifted into the JTAG DR reg.
46 // - data_shifted_out_of_dr: The data that will be shifted out of the JTAG DR reg will stored here
47 // - len: Length of the data to be shifted to JTAG DR.
49 // Note: If data_shifted_out_of_dr == NULL, discard incoming bits.
51 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
52 int retval
= ERROR_OK
;
53 if (NULL
== target
->tap
){
55 err_check(retval
,"Invalid tap");
59 err_check(retval
,"dr_len overflow, maxium is 32");
61 //TODO what values of len are valid for jtag_add_plain_dr_scan?
62 //can i send as many bits as i want?
63 //is the casting necessary?
64 jtag_add_plain_dr_scan(len
,data_to_shift_into_dr
,data_shifted_out_of_dr
, TAP_IDLE
);
66 retval
= dsp5680xx_execute_queue();
67 err_check_propagate(retval
);
69 if(data_shifted_out_of_dr
!=NULL
){
70 LOG_DEBUG("Data read (%d bits): 0x%04X",len
,*data_shifted_out_of_dr
);
72 LOG_DEBUG("Data read was discarded.");
76 static int dsp5680xx_irscan(struct target
* target
, uint32_t * data_to_shift_into_ir
, uint32_t * data_shifted_out_of_ir
, uint8_t ir_len
){
77 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
79 // - data_to_shift_into_ir: This is the data that will be shifted into the JTAG IR reg.
80 // - data_shifted_out_of_ir: The data that will be shifted out of the JTAG IR reg will stored here
81 // - len: Length of the data to be shifted to JTAG IR.
83 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
84 int retval
= ERROR_OK
;
85 if (NULL
== target
->tap
){
87 err_check(retval
,"Invalid tap");
89 if (ir_len
!= target
->tap
->ir_length
){
90 LOG_WARNING("%s: Invalid ir_len of core tap. If you are removing protection on flash then do not worry about this warninig.",__FUNCTION__
);
91 //return ERROR_FAIL;//TODO this was commented out to enable unlocking using the master tap. did not find a way to enable the master tap without using tcl.
93 //TODO what values of len are valid for jtag_add_plain_ir_scan?
94 //can i send as many bits as i want?
95 //is the casting necessary?
96 jtag_add_plain_ir_scan(ir_len
,(uint8_t *)data_to_shift_into_ir
,(uint8_t *)data_shifted_out_of_ir
, TAP_IDLE
);
98 retval
= dsp5680xx_execute_queue();
99 err_check_propagate(retval
);
104 static int dsp5680xx_jtag_status(struct target
*target
, uint8_t * status
){
105 uint32_t read_from_ir
;
108 instr
= JTAG_INSTR_ENABLE_ONCE
;
109 retval
= dsp5680xx_irscan(target
,& instr
, & read_from_ir
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
110 err_check_propagate(retval
);
112 *status
= (uint8_t)read_from_ir
;
116 static int jtag_data_read(struct target
* target
, uint32_t * data_read
, int num_bits
){
117 uint32_t bogus_instr
;
118 int retval
= dsp5680xx_drscan(target
,(uint8_t *) & bogus_instr
,(uint8_t *) data_read
,num_bits
);
119 LOG_DEBUG("Data read (%d bits): 0x%04X",num_bits
,*data_read
);//TODO remove this or move to jtagio?
123 #define jtag_data_read8(target,data_read) jtag_data_read(target,data_read,8)
124 #define jtag_data_read16(target,data_read) jtag_data_read(target,data_read,16)
125 #define jtag_data_read32(target,data_read) jtag_data_read(target,data_read,32)
127 static int jtag_data_write(struct target
* target
, uint32_t instr
,int num_bits
, uint32_t * data_read
){
129 uint32_t data_read_dummy
;
130 retval
= dsp5680xx_drscan(target
,(uint8_t *) & instr
,(uint8_t *) & data_read_dummy
,num_bits
);
131 err_check_propagate(retval
);
132 if(data_read
!= NULL
)
133 *data_read
= data_read_dummy
;
137 #define jtag_data_write8(target,instr,data_read) jtag_data_write(target,instr,8,data_read)
138 #define jtag_data_write16(target,instr,data_read) jtag_data_write(target,instr,16,data_read)
139 #define jtag_data_write24(target,instr,data_read) jtag_data_write(target,instr,24,data_read)
140 #define jtag_data_write32(target,instr,data_read) jtag_data_write(target,instr,32,data_read)
143 * Executes DSP instruction.
146 * @param instr Instruction to execute.
150 * @param eonce_status Value read from the EOnCE status register.
155 static int eonce_instruction_exec(struct target
* target
, uint8_t instr
, uint8_t rw
, uint8_t go
, uint8_t ex
,uint8_t * eonce_status
){
158 uint8_t instr_with_flags
= instr
|(rw
<<7)|(go
<<6)|(ex
<<5);
159 retval
= jtag_data_write(target
,instr_with_flags
,8,&dr_out_tmp
);
160 err_check_propagate(retval
);
161 if(eonce_status
!= NULL
)
162 *eonce_status
= (uint8_t) dr_out_tmp
;
166 ///wrappers for parameter conversion between eonce_execute_instruction and eonce_execute_instructionX
168 #define eonce_execute_instruction_1(target,opcode1,opcode2,opcode3) eonce_execute_instruction1(target,opcode1)
169 #define eonce_execute_instruction_2(target,opcode1,opcode2,opcode3) eonce_execute_instruction2(target,opcode1,opcode2)
170 #define eonce_execute_instruction_3(target,opcode1,opcode2,opcode3) eonce_execute_instruction3(target,opcode1,opcode2,opcode3)
171 #define eonce_execute_instruction(target,words,opcode1,opcode2,opcode3) eonce_execute_instruction_##words(target,opcode1,opcode2,opcode3)
173 /// Executes one word DSP instruction
174 static int eonce_execute_instruction1(struct target
* target
, uint16_t opcode
){
176 retval
= eonce_instruction_exec(target
,0x04,0,1,0,NULL
);
177 err_check_propagate(retval
);
178 retval
= jtag_data_write16(target
,opcode
,NULL
);
179 err_check_propagate(retval
);
183 /// Executes two word DSP instruction
184 static int eonce_execute_instruction2(struct target
* target
,uint16_t opcode1
, uint16_t opcode2
){
186 retval
= eonce_instruction_exec(target
,0x04,0,0,0,NULL
);
187 err_check_propagate(retval
);
188 retval
= jtag_data_write16(target
,opcode1
,NULL
);
189 err_check_propagate(retval
);
190 retval
= eonce_instruction_exec(target
,0x04,0,1,0,NULL
);
191 err_check_propagate(retval
);
192 retval
= jtag_data_write16(target
,opcode2
,NULL
);
193 err_check_propagate(retval
);
197 /// Executes three word DSP instruction
198 static int eonce_execute_instruction3(struct target
* target
, uint16_t opcode1
,uint16_t opcode2
,uint16_t opcode3
){
200 retval
= eonce_instruction_exec(target
,0x04,0,0,0,NULL
);
201 err_check_propagate(retval
);
202 retval
= jtag_data_write16(target
,opcode1
,NULL
);
203 err_check_propagate(retval
);
204 retval
= eonce_instruction_exec(target
,0x04,0,0,0,NULL
);
205 err_check_propagate(retval
);
206 retval
= jtag_data_write16(target
,opcode2
,NULL
);
207 err_check_propagate(retval
);
208 retval
= eonce_instruction_exec(target
,0x04,0,1,0,NULL
);
209 err_check_propagate(retval
);
210 retval
= jtag_data_write16(target
,opcode3
,NULL
);
211 err_check_propagate(retval
);
216 * --------------- Real-time data exchange ---------------
217 * The EOnCE Transmit (OTX) and Receive (ORX) registers are data memory mapped, each with an upper and lower 16 bit word.
218 * Transmit and receive directions are defined from the core’s perspective.
219 * The core writes to the Transmit register and reads the Receive register, and the host through JTAG writes to the Receive register and reads the Transmit register.
220 * Both registers have a combined data memory mapped OTXRXSR which provides indication when each may be accessed.
221 *ref: eonce_rev.1.0_0208081.pdf@36
224 /// writes data into upper ORx register of the target
225 static int eonce_tx_upper_data(struct target
* target
, uint16_t data
, uint32_t * eonce_status_low
){
227 retval
= eonce_instruction_exec(target
,DSP5680XX_ONCE_ORX1
,0,0,0,NULL
);
228 err_check_propagate(retval
);
229 retval
= jtag_data_write16(target
,data
,eonce_status_low
);
230 err_check_propagate(retval
);
234 /// writes data into lower ORx register of the target
235 #define eonce_tx_lower_data(target,data) eonce_instruction_exec(target,DSP5680XX_ONCE_ORX,0,0,0,NULL);\
236 jtag_data_write16(target,data)
241 * @param data_read: Returns the data read from the upper OTX register via JTAG.
242 * @return: Returns an error code (see error code documentation)
244 static int eonce_rx_upper_data(struct target
* target
, uint16_t * data_read
)
247 retval
= eonce_instruction_exec(target
,DSP5680XX_ONCE_OTX1
,1,0,0,NULL
);
248 err_check_propagate(retval
);
249 retval
= jtag_data_read16(target
,(uint32_t *)data_read
);
250 err_check_propagate(retval
);
257 * @param data_read: Returns the data read from the lower OTX register via JTAG.
258 * @return: Returns an error code (see error code documentation)
260 static int eonce_rx_lower_data(struct target
* target
,uint16_t * data_read
)
263 retval
= eonce_instruction_exec(target
,DSP5680XX_ONCE_OTX
,1,0,0,NULL
);
264 err_check_propagate(retval
);
265 retval
= jtag_data_read16(target
,(uint32_t *)data_read
);
266 err_check_propagate(retval
);
271 * -- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- --
272 * -- -- -- -- --- -- -- -Core Instructions- -- -- -- --- -- -- -- --- --
273 * -- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- -- -- -- --- --
277 #define eonce_move_long_to_r0(target,value) eonce_execute_instruction(target,3,0xe418,value&0xffff,value>>16)
280 #define eonce_move_long_to_n(target,value) eonce_execute_instruction(target,3,0xe41e,value&0xffff,value>>16)
283 #define eonce_move_at_r0_to_y0(target) eonce_execute_instruction(target,1,0xF514,0,0)
286 #define eonce_move_at_r0_to_y1(target) eonce_execute_instruction(target,1,0xF714,0,0)
289 #define eonce_move_long_at_r0_y(target) eonce_execute_instruction(target,1,0xF734,0,0)
292 #define eonce_move_y0_at_r0(target) eonce_execute_instruction(target,1,0xd514,0,0)
294 /// bfclr #value,x:(r0)
295 #define eonce_bfclr_at_r0(target,value) eonce_execute_instruction(target,2,0x8040,value,0)
298 #define eonce_move_value_to_y0(target,value) eonce_execute_instruction(target,2,0x8745,value,0)
300 /// move.w y0,x:(r0)+
301 #define eonce_move_y0_at_r0_inc(target) eonce_execute_instruction(target,1,0xd500,0,0)
303 /// move.w y0,p:(r0)+
304 #define eonce_move_y0_at_pr0_inc(target) eonce_execute_instruction(target,1,0x8560,0,0)
306 /// move.w p:(r0)+,y0
307 #define eonce_move_at_pr0_inc_to_y0(target) eonce_execute_instruction(target,1,0x8568,0,0)
309 /// move.w p:(r0)+,y1
310 #define eonce_move_at_pr0_inc_to_y1(target) eonce_execute_instruction(target,1,0x8768,0,0)
313 #define eonce_move_long_to_r2(target,value) eonce_execute_instruction(target,3,0xe41A,value&0xffff,value>>16)
316 #define eonce_move_y0_at_r2(target) eonce_execute_instruction(target,1,0xd516,0,0)
318 /// move.w #<value>,x:(r2)
319 #define eonce_move_value_at_r2(target,value) eonce_execute_instruction(target,2,0x8642,value,0)
321 /// move.w #<value>,x:(r0)
322 #define eonce_move_value_at_r0(target,value) eonce_execute_instruction(target,2,0x8640,value,0)
324 /// move.w #<value>,x:(R2+<disp>)
325 #define eonce_move_value_at_r2_disp(target,value,disp) eonce_execute_instruction(target,3,0x8646,value,disp)
328 #define eonce_move_at_r2_to_y0(target) eonce_execute_instruction(target,1,0xF516,0,0)
330 /// move.w p:(r2)+,y0
331 #define eonce_move_at_pr2_inc_to_y0(target) eonce_execute_instruction(target,1,0x856A,0,0)
334 #define eonce_move_long_to_r1(target,value) eonce_execute_instruction(target,3,0xE419,value&0xffff,value>>16)
337 #define eonce_move_long_to_r3(target,value) eonce_execute_instruction(target,3,0xE41B,value&0xffff,value>>16)
339 /// move.w y0,p:(r3)+
340 #define eonce_move_y0_at_pr3_inc(target) eonce_execute_instruction(target,1,0x8563,0,0)
343 #define eonce_move_y0_at_r3(target) eonce_execute_instruction(target,1,0xD503,0,0)
346 #define eonce_move_long_to_r4(target,value) eonce_execute_instruction(target,3,0xE41C,value&0xffff,value>>16)
349 #define eonce_move_pc_to_r4(target) eonce_execute_instruction(target,1,0xE716,0,0)
352 #define eonce_move_r4_to_y(target) eonce_execute_instruction(target,1,0xe764,0,0)
354 /// move.w p:(r0)+,y0
355 #define eonce_move_at_pr0_inc_to_y0(target) eonce_execute_instruction(target,1,0x8568,0,0)
357 /// move.w x:(r0)+,y0
358 #define eonce_move_at_r0_inc_to_y0(target) eonce_execute_instruction(target,1,0xf500,0,0)
361 #define eonce_move_at_r0_y0(target) eonce_execute_instruction(target,1,0xF514,0,0)
364 #define eonce_nop(target) eonce_execute_instruction(target,1,0xe700,0,0)
366 /// move.w x:(R2+<disp>),Y0
367 #define eonce_move_at_r2_disp_to_y0(target,disp) eonce_execute_instruction(target,2,0xF542,disp,0)
370 #define eonce_move_y1_at_r2(target) eonce_execute_instruction(target,1,0xd716,0,0)
373 #define eonce_move_y1_at_r0(target) eonce_execute_instruction(target,1,0xd714,0,0)
375 /// move.bp y0,x:(r0)+
376 #define eonce_move_byte_y0_at_r0(target) eonce_execute_instruction(target,1,0xd5a0,0,0)
378 /// move.w y1,p:(r0)+
379 #define eonce_move_y1_at_pr0_inc(target) eonce_execute_instruction(target,1,0x8760,0,0)
381 /// move.w y1,x:(r0)+
382 #define eonce_move_y1_at_r0_inc(target) eonce_execute_instruction(target,1,0xD700,0,0)
385 #define eonce_move_long_to_y(target,value) eonce_execute_instruction(target,3,0xe417,value&0xffff,value>>16)
387 static int eonce_move_value_to_pc(struct target
* target
, uint32_t value
){
388 if (!(target
->state
== TARGET_HALTED
)){
389 LOG_ERROR("Target must be halted to move PC. Target state = %d.",target
->state
);
390 return ERROR_TARGET_NOT_HALTED
;
393 retval
= eonce_execute_instruction(target
,3,0xE71E,value
&0xffff,value
>>16);
394 err_check_propagate(retval
);
398 static int eonce_load_TX_RX_to_r0(struct target
* target
)
401 retval
= eonce_move_long_to_r0(target
,((MC568013_EONCE_TX_RX_ADDR
)+(MC568013_EONCE_OBASE_ADDR
<<16)));
405 static int eonce_load_TX_RX_high_to_r0(struct target
* target
)
408 retval
= eonce_move_long_to_r0(target
,((MC568013_EONCE_TX1_RX1_HIGH_ADDR
)+(MC568013_EONCE_OBASE_ADDR
<<16)));
412 static int dsp5680xx_read_core_reg(struct target
* target
, uint8_t reg_addr
, uint16_t * data_read
)
414 //TODO implement a general version of this which matches what openocd uses.
416 uint32_t dummy_data_to_shift_into_dr
;
417 retval
= eonce_instruction_exec(target
,reg_addr
,1,0,0,NULL
);
418 err_check_propagate(retval
);
419 retval
= dsp5680xx_drscan(target
,(uint8_t *)& dummy_data_to_shift_into_dr
,(uint8_t *) data_read
, 8);
420 err_check_propagate(retval
);
421 LOG_DEBUG("Reg. data: 0x%02X.",*data_read
);
425 static int eonce_read_status_reg(struct target
* target
, uint16_t * data
){
427 retval
= dsp5680xx_read_core_reg(target
,DSP5680XX_ONCE_OSR
,data
);
428 err_check_propagate(retval
);
433 * Takes the core out of debug mode.
436 * @param eonce_status Data read from the EOnCE status register.
440 static int eonce_exit_debug_mode(struct target
* target
,uint8_t * eonce_status
){
442 retval
= eonce_instruction_exec(target
,0x1F,0,0,1,eonce_status
);
443 err_check_propagate(retval
);
448 * Puts the core into debug mode, enabling the EOnCE module.
451 * @param eonce_status Data read from the EOnCE status register.
455 static int eonce_enter_debug_mode(struct target
* target
, uint16_t * eonce_status
){
457 uint32_t instr
= JTAG_INSTR_DEBUG_REQUEST
;
458 uint32_t ir_out
;//not used, just to make jtag happy.
460 retval
= dsp5680xx_irscan(target
,& instr
,& ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
461 err_check_propagate(retval
);
463 // Enable EOnCE module
464 instr
= JTAG_INSTR_ENABLE_ONCE
;
465 //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
466 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
467 err_check_propagate(retval
);
468 retval
= dsp5680xx_irscan(target
, & instr
, & ir_out
,DSP5680XX_JTAG_CORE_TAP_IRLEN
);
469 err_check_propagate(retval
);
470 // Verify that debug mode is enabled
471 uint16_t data_read_from_dr
;
472 retval
= eonce_read_status_reg(target
,&data_read_from_dr
);
473 err_check_propagate(retval
);
474 if((data_read_from_dr
&0x30) == 0x30){
475 LOG_DEBUG("EOnCE successfully entered debug mode.");
476 target
->state
= TARGET_HALTED
;
479 retval
= ERROR_TARGET_FAILURE
;
480 err_check(retval
,"Failed to set EOnCE module to debug mode.");
482 if(eonce_status
!=NULL
)
483 *eonce_status
= data_read_from_dr
;
488 * Reads the current value of the program counter and stores it.
494 static int eonce_pc_store(struct target
* target
){
497 retval
= eonce_move_pc_to_r4(target
);
498 err_check_propagate(retval
);
499 retval
= eonce_move_r4_to_y(target
);
500 err_check_propagate(retval
);
501 retval
= eonce_load_TX_RX_to_r0(target
);
502 err_check_propagate(retval
);
503 retval
= eonce_move_y0_at_r0(target
);
504 err_check_propagate(retval
);
505 retval
= eonce_rx_lower_data(target
,(uint16_t *)&tmp
);
506 err_check_propagate(retval
);
507 LOG_USER("PC value: 0x%06X\n",tmp
);
508 context
.stored_pc
= (uint32_t)tmp
;
512 static int dsp5680xx_target_create(struct target
*target
, Jim_Interp
* interp
){
513 struct dsp5680xx_common
*dsp5680xx
= calloc(1, sizeof(struct dsp5680xx_common
));
514 target
->arch_info
= dsp5680xx
;
518 static int dsp5680xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
){
519 context
.stored_pc
= 0;
521 LOG_DEBUG("target initiated!");
522 //TODO core tap must be enabled before running these commands, currently this is done in the .cfg tcl script.
526 static int dsp5680xx_arch_state(struct target
*target
){
527 LOG_USER("%s not implemented yet.",__FUNCTION__
);
531 int dsp5680xx_target_status(struct target
* target
, uint8_t * jtag_st
, uint16_t * eonce_st
){
532 return target
->state
;
535 static int dsp5680xx_assert_reset(struct target
*target
){
536 target
->state
= TARGET_RESET
;
540 static int dsp5680xx_deassert_reset(struct target
*target
){
541 target
->state
= TARGET_RUNNING
;
545 static int dsp5680xx_halt(struct target
*target
){
547 uint16_t eonce_status
;
548 if(target
->state
== TARGET_HALTED
){
549 LOG_USER("Target already halted.");
552 retval
= eonce_enter_debug_mode(target
,&eonce_status
);
553 err_check_propagate(retval
);
554 retval
= eonce_pc_store(target
);
555 err_check_propagate(retval
);
556 //TODO is it useful to store the pc?
560 static int dsp5680xx_poll(struct target
*target
){
563 uint8_t eonce_status
;
565 retval
= dsp5680xx_jtag_status(target
,&jtag_status
);
566 err_check_propagate(retval
);
567 LOG_DEBUG("%02X",jtag_status
);
568 if (jtag_status
== JTAG_STATUS_DEBUG
)
569 if (target
->state
!= TARGET_HALTED
){
570 retval
= eonce_enter_debug_mode(target
,&read_tmp
);
571 err_check_propagate(retval
);
572 eonce_status
= (uint8_t) read_tmp
;
573 if((eonce_status
&EONCE_STAT_MASK
) != DSP5680XX_ONCE_OSCR_DEBUG_M
){
574 LOG_WARNING("%s: Failed to put EOnCE in debug mode. Is flash locked?...",__FUNCTION__
);
575 return ERROR_TARGET_FAILURE
;
577 target
->state
= TARGET_HALTED
;
581 if (jtag_status
== JTAG_STATUS_NORMAL
){
582 if(target
->state
== TARGET_RESET
){
583 retval
= dsp5680xx_halt(target
);
584 err_check_propagate(retval
);
585 retval
= eonce_exit_debug_mode(target
,&eonce_status
);
586 err_check_propagate(retval
);
587 if((eonce_status
&EONCE_STAT_MASK
) != DSP5680XX_ONCE_OSCR_NORMAL_M
){
588 LOG_WARNING("%s: JTAG running, but cannot make EOnCE run. Try resetting...",__FUNCTION__
);
589 return ERROR_TARGET_FAILURE
;
591 target
->state
= TARGET_RUNNING
;
595 if(target
->state
!= TARGET_RUNNING
){
596 retval
= eonce_read_status_reg(target
,&read_tmp
);
597 err_check_propagate(retval
);
598 eonce_status
= (uint8_t) read_tmp
;
599 if((eonce_status
&EONCE_STAT_MASK
) != DSP5680XX_ONCE_OSCR_NORMAL_M
){
600 LOG_WARNING("Inconsistent target status. Restart!");
601 return ERROR_TARGET_FAILURE
;
604 target
->state
= TARGET_RUNNING
;
607 if(jtag_status
== JTAG_STATUS_DEAD
){
608 LOG_ERROR("%s: Cannot communicate with JTAG. Check connection...",__FUNCTION__
);
609 target
->state
= TARGET_UNKNOWN
;
610 return ERROR_TARGET_FAILURE
;
612 if (target
->state
== TARGET_UNKNOWN
){
613 LOG_ERROR("%s: Target status invalid - communication failure",__FUNCTION__
);
614 return ERROR_TARGET_FAILURE
;
619 static int dsp5680xx_resume(struct target
*target
, int current
, uint32_t address
,int handle_breakpoints
, int debug_execution
){
620 if(target
->state
== TARGET_RUNNING
){
621 LOG_USER("Target already running.");
625 uint8_t eonce_status
;
627 retval
= eonce_move_value_to_pc(target
,address
);
628 err_check_propagate(retval
);
633 retval
= eonce_exit_debug_mode(target
,&eonce_status
);
634 err_check_propagate(retval
);
635 if(eonce_status
== DSP5680XX_ONCE_OSCR_NORMAL_M
)
639 retval
= ERROR_TARGET_FAILURE
;
640 err_check(retval
,"Failed to resume...");
642 target
->state
= TARGET_RUNNING
;
644 LOG_DEBUG("EOnCE status: 0x%02X.",eonce_status
);
654 * The value of @address determines if it corresponds to P: (program) or X: (data) memory. If the address is over 0x200000 then it is considered X: memory, and @pmem = 0.
655 * The special case of 0xFFXXXX is not modified, since it allows to read out the memory mapped EOnCE registers.
662 static int dsp5680xx_convert_address(uint32_t * address
, int * pmem
){
663 // Distinguish data memory (x:) from program memory (p:) by the address.
664 // Addresses over S_FILE_DATA_OFFSET are considered (x:) memory.
665 if(*address
>= S_FILE_DATA_OFFSET
){
667 if(((*address
)&0xff0000)!=0xff0000)
668 *address
-= S_FILE_DATA_OFFSET
;
673 static int dsp5680xx_read_16_single(struct target
* target
, uint32_t address
, uint16_t * data_read
, int r_pmem
){
674 //TODO add error control!
676 retval
= eonce_move_long_to_r0(target
,address
);
677 err_check_propagate(retval
);
679 retval
= eonce_move_at_pr0_inc_to_y0(target
);
681 retval
= eonce_move_at_r0_to_y0(target
);
682 err_check_propagate(retval
);
683 retval
= eonce_load_TX_RX_to_r0(target
);
684 err_check_propagate(retval
);
685 retval
= eonce_move_y0_at_r0(target
);
686 err_check_propagate(retval
);
687 // at this point the data i want is at the reg eonce can read
688 retval
= eonce_rx_lower_data(target
,data_read
);
689 err_check_propagate(retval
);
690 LOG_DEBUG("%s: Data read from 0x%06X: 0x%04X",__FUNCTION__
, address
,*data_read
);
694 static int dsp5680xx_read_32_single(struct target
* target
, uint32_t address
, uint32_t * data_read
, int r_pmem
){
696 address
= (address
& 0xFFFFFE);
697 // Get data to an intermediate register
698 retval
= eonce_move_long_to_r0(target
,address
);
699 err_check_propagate(retval
);
701 retval
= eonce_move_at_pr0_inc_to_y0(target
);
702 err_check_propagate(retval
);
703 retval
= eonce_move_at_pr0_inc_to_y1(target
);
704 err_check_propagate(retval
);
706 retval
= eonce_move_at_r0_inc_to_y0(target
);
707 err_check_propagate(retval
);
708 retval
= eonce_move_at_r0_to_y1(target
);
709 err_check_propagate(retval
);
711 // Get lower part of data to TX/RX
712 retval
= eonce_load_TX_RX_to_r0(target
);
713 err_check_propagate(retval
);
714 retval
= eonce_move_y0_at_r0_inc(target
); // This also load TX/RX high to r0
715 err_check_propagate(retval
);
716 // Get upper part of data to TX/RX
717 retval
= eonce_move_y1_at_r0(target
);
718 err_check_propagate(retval
);
719 // at this point the data i want is at the reg eonce can read
720 retval
= eonce_rx_lower_data(target
,(uint16_t * )data_read
);
721 err_check_propagate(retval
);
723 retval
= eonce_rx_upper_data(target
,&tmp
);
724 err_check_propagate(retval
);
725 *data_read
= ((tmp
<<16) | (*data_read
));//This enables OpenOCD crc to succeed (when it should)
729 static int dsp5680xx_read(struct target
* target
, uint32_t address
, unsigned size
, unsigned count
, uint8_t * buffer
){
730 if(target
->state
!= TARGET_HALTED
){
731 LOG_USER("Target must be halted.");
734 uint32_t * buff32
= (uint32_t *) buffer
;
735 uint16_t * buff16
= (uint16_t *) buffer
;
736 int retval
= ERROR_OK
;
740 retval
= dsp5680xx_convert_address(&address
, &pmem
);
741 err_check_propagate(retval
);
744 int counter
= FLUSH_COUNT_READ_WRITE
;
746 for (unsigned i
=0; i
<count
; i
++){
749 counter
= FLUSH_COUNT_FLASH
;
754 retval
= dsp5680xx_read_16_single(target
, address
+ i
/2, &tmp_wrd
, pmem
);
755 buffer
[i
] = (uint8_t) (tmp_wrd
>>8);
756 buffer
[i
+1] = (uint8_t) (tmp_wrd
&0xff);
760 retval
= dsp5680xx_read_16_single(target
, address
+ i
, buff16
+ i
, pmem
);
763 retval
= dsp5680xx_read_32_single(target
, address
+ 2*i
, buff32
+ i
, pmem
);
766 LOG_USER("%s: Invalid read size.",__FUNCTION__
);
769 err_check_propagate(retval
);
774 retval
= dsp5680xx_execute_queue();
775 err_check_propagate(retval
);
780 static int dsp5680xx_write_16_single(struct target
*target
, uint32_t address
, uint16_t data
, uint8_t w_pmem
){
782 retval
= eonce_move_long_to_r0(target
,address
);
783 err_check_propagate(retval
);
785 retval
= eonce_move_value_to_y0(target
,data
);
786 err_check_propagate(retval
);
787 retval
= eonce_move_y0_at_pr0_inc(target
);
788 err_check_propagate(retval
);
790 retval
= eonce_move_value_at_r0(target
,data
);
791 err_check_propagate(retval
);
796 static int dsp5680xx_write_32_single(struct target
*target
, uint32_t address
, uint32_t data
, int w_pmem
){
798 retval
= eonce_move_long_to_r0(target
,address
);
799 err_check_propagate(retval
);
800 retval
= eonce_move_long_to_y(target
,data
);
801 err_check_propagate(retval
);
803 retval
= eonce_move_y0_at_pr0_inc(target
);
805 retval
= eonce_move_y0_at_r0_inc(target
);
806 err_check_propagate(retval
);
808 retval
= eonce_move_y1_at_pr0_inc(target
);
810 retval
= eonce_move_y1_at_r0_inc(target
);
811 err_check_propagate(retval
);
815 static int dsp5680xx_write_8(struct target
* target
, uint32_t address
, uint32_t count
, uint8_t * data
, int pmem
){
816 if(target
->state
!= TARGET_HALTED
){
817 LOG_ERROR("%s: Target must be halted.",__FUNCTION__
);
821 uint16_t * data_w
= (uint16_t *)data
;
824 int counter
= FLUSH_COUNT_READ_WRITE
;
825 for(iter
= 0; iter
<count
/2; iter
++){
828 counter
= FLUSH_COUNT_READ_WRITE
;
830 retval
= dsp5680xx_write_16_single(target
,address
+iter
,data_w
[iter
], pmem
);
831 if(retval
!= ERROR_OK
){
832 LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__
,address
);
840 // Only one byte left, let's not overwrite the other byte (mem is 16bit)
841 // Need to retrieve the part we do not want to overwrite.
843 if((count
==1)||(count
%2)){
844 retval
= dsp5680xx_read(target
,address
+iter
,1,1,(uint8_t *)&data_old
);
845 err_check_propagate(retval
);
847 data_old
=(((data_old
&0xff)<<8)|data
[0]);// preserve upper byte
849 data_old
=(((data_old
&0xff)<<8)|data
[2*iter
+1]);
850 retval
= dsp5680xx_write_16_single(target
,address
+iter
,data_old
, pmem
);
851 err_check_propagate(retval
);
856 static int dsp5680xx_write_16(struct target
* target
, uint32_t address
, uint32_t count
, uint16_t * data
, int pmem
){
857 int retval
= ERROR_OK
;
858 if(target
->state
!= TARGET_HALTED
){
859 retval
= ERROR_TARGET_NOT_HALTED
;
860 err_check(retval
,"Target must be halted.");
863 int counter
= FLUSH_COUNT_READ_WRITE
;
865 for(iter
= 0; iter
<count
; iter
++){
868 counter
= FLUSH_COUNT_READ_WRITE
;
870 retval
= dsp5680xx_write_16_single(target
,address
+iter
,data
[iter
], pmem
);
871 if(retval
!= ERROR_OK
){
872 LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__
,address
);
882 static int dsp5680xx_write_32(struct target
* target
, uint32_t address
, uint32_t count
, uint32_t * data
, int pmem
){
883 int retval
= ERROR_OK
;
884 if(target
->state
!= TARGET_HALTED
){
885 retval
= ERROR_TARGET_NOT_HALTED
;
886 err_check(retval
,"Target must be halted.");
889 int counter
= FLUSH_COUNT_READ_WRITE
;
891 for(iter
= 0; iter
<count
; iter
++){
894 counter
= FLUSH_COUNT_READ_WRITE
;
896 retval
= dsp5680xx_write_32_single(target
,address
+(iter
<<1),data
[iter
], pmem
);
897 if(retval
!= ERROR_OK
){
898 LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__
,address
);
909 * Writes @buffer to memory.
910 * The parameter @address determines whether @buffer should be written to P: (program) memory or X: (data) memory.
914 * @param size Bytes (1), Half words (2), Words (4).
915 * @param count In bytes.
920 static int dsp5680xx_write(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t * buffer
){
921 //TODO Cannot write 32bit to odd address, will write 0x12345678 as 0x5678 0x0012
922 if(target
->state
!= TARGET_HALTED
){
923 LOG_USER("Target must be halted.");
928 retval
= dsp5680xx_convert_address(&address
, &p_mem
);
929 err_check_propagate(retval
);
933 retval
= dsp5680xx_write_8(target
, address
, count
,(uint8_t *) buffer
, p_mem
);
936 retval
= dsp5680xx_write_16(target
, address
, count
, (uint16_t *)buffer
, p_mem
);
939 retval
= dsp5680xx_write_32(target
, address
, count
, (uint32_t *)buffer
, p_mem
);
942 retval
= ERROR_TARGET_DATA_ABORT
;
943 err_check(retval
,"Invalid data size.");
949 static int dsp5680xx_bulk_write_memory(struct target
* target
,uint32_t address
, uint32_t aligned
, const uint8_t * buffer
){
950 LOG_ERROR("Not implemented yet.");
954 static int dsp5680xx_write_buffer(struct target
* target
, uint32_t address
, uint32_t size
, const uint8_t * buffer
){
955 if(target
->state
!= TARGET_HALTED
){
956 LOG_USER("Target must be halted.");
959 return dsp5680xx_write(target
, address
, 1, size
, buffer
);
963 * This function is called by verify_image, it is used to read data from memory.
966 * @param address Word addressing.
967 * @param size In bytes.
972 static int dsp5680xx_read_buffer(struct target
* target
, uint32_t address
, uint32_t size
, uint8_t * buffer
){
973 if(target
->state
!= TARGET_HALTED
){
974 LOG_USER("Target must be halted.");
977 // The "/2" solves the byte/word addressing issue.
978 return dsp5680xx_read(target
,address
,2,size
/2,buffer
);
982 * This function is not implemented.
983 * It returns an error in order to get OpenOCD to do read out the data and calculate the CRC, or try a binary comparison.
986 * @param address Start address of the image.
987 * @param size In bytes.
992 static int dsp5680xx_checksum_memory(struct target
* target
, uint32_t address
, uint32_t size
, uint32_t * checksum
){
997 * Calculates a signature over @word_count words in the data from @buff16. The algorithm used is the same the FM uses, so the @return may be used to compare with the one generated by the FM module, and check if flashing was successful.
998 * This algorithm is based on the perl script available from the Freescale website at FAQ 25630.
1005 static int perl_crc(uint16_t * buff16
,uint32_t word_count
){
1006 uint16_t checksum
= 0xffff;
1007 uint16_t data
,fbmisr
;
1009 for(i
=0;i
<word_count
;i
++){
1011 fbmisr
= (checksum
& 2)>>1 ^ (checksum
& 4)>>2 ^ (checksum
& 16)>>4 ^ (checksum
& 0x8000)>>15;
1012 checksum
= (data
^ ((checksum
<< 1) | fbmisr
));
1015 for(;!(i
&0x80000000);i
--){
1017 fbmisr
= (checksum
& 2)>>1 ^ (checksum
& 4)>>2 ^ (checksum
& 16)>>4 ^ (checksum
& 0x8000)>>15;
1018 checksum
= (data
^ ((checksum
<< 1) | fbmisr
));
1024 * Resets the SIM. (System Integration Module).
1030 int dsp5680xx_f_SIM_reset(struct target
* target
){
1031 int retval
= ERROR_OK
;
1032 uint16_t sim_cmd
= SIM_CMD_RESET
;
1034 if(strcmp(target
->tap
->chip
,"dsp568013")==0){
1035 sim_addr
= MC568013_SIM_BASE_ADDR
+S_FILE_DATA_OFFSET
;
1036 retval
= dsp5680xx_write(target
,sim_addr
,1,2,(const uint8_t *)&sim_cmd
);
1037 err_check_propagate(retval
);
1043 * Halts the core and resets the SIM. (System Integration Module).
1049 static int dsp5680xx_soft_reset_halt(struct target
*target
){
1050 //TODO is this what this function is expected to do...?
1052 retval
= dsp5680xx_halt(target
);
1053 err_check_propagate(retval
);
1054 retval
= dsp5680xx_f_SIM_reset(target
);
1055 err_check_propagate(retval
);
1059 int dsp5680xx_f_protect_check(struct target
* target
, uint16_t * protected) {
1062 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1063 retval
= dsp5680xx_halt(target
);
1064 err_check_propagate(retval
);
1066 if(protected == NULL
){
1067 err_check(ERROR_FAIL
,"NULL pointer not valid.");
1069 retval
= dsp5680xx_read_16_single(target
,HFM_BASE_ADDR
|HFM_PROT
,&aux
,0);
1070 err_check_propagate(retval
);
1076 * Executes a command on the FM module. Some commands use the parameters @address and @data, others ignore them.
1079 * @param command Command to execute.
1080 * @param address Command parameter.
1081 * @param data Command parameter.
1082 * @param hfm_ustat FM status register.
1083 * @param pmem Address is P: (program) memory (@pmem==1) or X: (data) memory (@pmem==0)
1087 static int dsp5680xx_f_execute_command(struct target
* target
, uint16_t command
, uint32_t address
, uint32_t data
, uint16_t * hfm_ustat
, int pmem
){
1089 retval
= eonce_load_TX_RX_high_to_r0(target
);
1090 err_check_propagate(retval
);
1091 retval
= eonce_move_long_to_r2(target
,HFM_BASE_ADDR
);
1092 err_check_propagate(retval
);
1096 retval
= eonce_move_at_r2_disp_to_y0(target
,HFM_USTAT
); // read HMF_USTAT
1097 err_check_propagate(retval
);
1098 retval
= eonce_move_y0_at_r0(target
);
1099 err_check_propagate(retval
);
1100 retval
= eonce_rx_upper_data(target
,&i
);
1101 err_check_propagate(retval
);
1102 if((watchdog
--)==1){
1103 retval
= ERROR_TARGET_FAILURE
;
1104 err_check(retval
,"FM execute command failed.");
1106 }while (!(i
&0x40)); // wait until current command is complete
1110 retval
= eonce_move_value_at_r2_disp(target
,0x00,HFM_CNFG
); // write to HFM_CNFG (lock=0, select bank) -- flash_desc.bank&0x03,0x01 == 0x00,0x01 ???
1111 err_check_propagate(retval
);
1112 retval
= eonce_move_value_at_r2_disp(target
,0x04,HFM_USTAT
); // write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
1113 err_check_propagate(retval
);
1114 retval
= eonce_move_value_at_r2_disp(target
,0x10,HFM_USTAT
); // clear only one bit at a time
1115 err_check_propagate(retval
);
1116 retval
= eonce_move_value_at_r2_disp(target
,0x20,HFM_USTAT
);
1117 err_check_propagate(retval
);
1118 retval
= eonce_move_value_at_r2_disp(target
,0x00,HFM_PROT
); // write to HMF_PROT, clear protection
1119 err_check_propagate(retval
);
1120 retval
= eonce_move_value_at_r2_disp(target
,0x00,HFM_PROTB
); // write to HMF_PROTB, clear protection
1121 err_check_propagate(retval
);
1122 retval
= eonce_move_value_to_y0(target
,data
);
1123 err_check_propagate(retval
);
1124 retval
= eonce_move_long_to_r3(target
,address
); // write to the flash block
1125 err_check_propagate(retval
);
1127 retval
= eonce_move_y0_at_pr3_inc(target
);
1128 err_check_propagate(retval
);
1130 retval
= eonce_move_y0_at_r3(target
);
1131 err_check_propagate(retval
);
1133 retval
= eonce_move_value_at_r2_disp(target
,command
,HFM_CMD
); // write command to the HFM_CMD reg
1134 err_check_propagate(retval
);
1135 retval
= eonce_move_value_at_r2_disp(target
,0x80,HFM_USTAT
); // start the command
1136 err_check_propagate(retval
);
1139 retval
= dsp5680xx_execute_queue();
1140 err_check_propagate(retval
);
1144 retval
= eonce_move_at_r2_disp_to_y0(target
,HFM_USTAT
); // read HMF_USTAT
1145 err_check_propagate(retval
);
1146 retval
= eonce_move_y0_at_r0(target
);
1147 err_check_propagate(retval
);
1148 retval
= eonce_rx_upper_data(target
,&i
);
1149 err_check_propagate(retval
);
1150 if((watchdog
--)==1){
1151 retval
= ERROR_TARGET_FAILURE
;
1152 err_check(retval
,"FM execution did not finish.");
1154 }while (!(i
&0x40)); // wait until the command is complete
1156 if (i
&HFM_USTAT_MASK_PVIOL_ACCER
){
1157 retval
= ERROR_TARGET_FAILURE
;
1158 err_check(retval
,"pviol and/or accer bits set. HFM command execution error");
1164 * Prior to the execution of any Flash module command, the Flash module Clock Divider (CLKDIV) register must be initialized. The values of this register determine the speed of the internal Flash Clock (FCLK). FCLK must be in the range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module. (Running FCLK too slowly wears out the module, while running it too fast under programs Flash leading to bit errors.)
1170 static int eonce_set_hfmdiv(struct target
* target
){
1173 retval
= eonce_move_long_to_r2(target
,HFM_BASE_ADDR
);
1174 err_check_propagate(retval
);
1175 retval
= eonce_load_TX_RX_high_to_r0(target
);
1176 err_check_propagate(retval
);
1177 retval
= eonce_move_at_r2_to_y0(target
);// read HFM_CLKD
1178 err_check_propagate(retval
);
1179 retval
= eonce_move_y0_at_r0(target
);
1180 err_check_propagate(retval
);
1181 retval
= eonce_rx_upper_data(target
,&i
);
1182 err_check_propagate(retval
);
1183 unsigned int hfm_at_wrong_value
= 0;
1184 if ((i
&0x7f)!=HFM_CLK_DEFAULT
) {
1185 LOG_DEBUG("HFM CLK divisor contained incorrect value (0x%02X).",i
&0x7f);
1186 hfm_at_wrong_value
= 1;
1188 LOG_DEBUG("HFM CLK divisor was already set to correct value (0x%02X).",i
&0x7f);
1191 retval
= eonce_move_value_at_r2(target
,HFM_CLK_DEFAULT
); // write HFM_CLKD
1192 err_check_propagate(retval
);
1193 retval
= eonce_move_at_r2_to_y0(target
); // verify HFM_CLKD
1194 err_check_propagate(retval
);
1195 retval
= eonce_move_y0_at_r0(target
);
1196 err_check_propagate(retval
);
1197 retval
= eonce_rx_upper_data(target
,&i
);
1198 err_check_propagate(retval
);
1199 if (i
!=(0x80|(HFM_CLK_DEFAULT
&0x7f))) {
1200 retval
= ERROR_TARGET_FAILURE
;
1201 err_check(retval
,"Unable to set HFM CLK divisor.");
1203 if(hfm_at_wrong_value
)
1204 LOG_DEBUG("HFM CLK divisor set to 0x%02x.",i
&0x7f);
1209 * Executes the FM calculate signature command. The FM will calculate over the data from @address to @address + @words -1. The result is written to a register, then read out by this function and returned in @signature. The value @signature may be compared to the the one returned by perl_crc to verify the flash was written correctly.
1212 * @param address Start of flash array where the signature should be calculated.
1213 * @param words Number of words over which the signature should be calculated.
1214 * @param signature Value calculated by the FM.
1218 static int dsp5680xx_f_signature(struct target
* target
, uint32_t address
, uint32_t words
, uint16_t * signature
){
1221 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1222 retval
= eonce_enter_debug_mode(target
,NULL
);
1223 err_check_propagate(retval
);
1225 retval
= dsp5680xx_f_execute_command(target
,HFM_CALCULATE_DATA_SIGNATURE
,address
,words
,&hfm_ustat
,1);
1226 err_check_propagate(retval
);
1227 retval
= dsp5680xx_read_16_single(target
, HFM_BASE_ADDR
|HFM_DATA
, signature
, 0);
1231 int dsp5680xx_f_erase_check(struct target
* target
, uint8_t * erased
,uint32_t sector
){
1234 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1235 retval
= dsp5680xx_halt(target
);
1236 err_check_propagate(retval
);
1238 // Check if chip is already erased.
1239 retval
= dsp5680xx_f_execute_command(target
,HFM_ERASE_VERIFY
,HFM_FLASH_BASE_ADDR
+sector
*HFM_SECTOR_SIZE
/2,0,&hfm_ustat
,1); // blank check
1240 err_check_propagate(retval
);
1242 *erased
= (uint8_t)(hfm_ustat
&HFM_USTAT_MASK_BLANK
);
1247 * Executes the FM page erase command.
1250 * @param sector Page to erase.
1251 * @param hfm_ustat FM module status register.
1255 static int erase_sector(struct target
* target
, int sector
, uint16_t * hfm_ustat
){
1257 retval
= dsp5680xx_f_execute_command(target
,HFM_PAGE_ERASE
,HFM_FLASH_BASE_ADDR
+sector
*HFM_SECTOR_SIZE
/2,0,hfm_ustat
,1);
1258 err_check_propagate(retval
);
1263 * Executes the FM mass erase command. Erases the flash array completely.
1266 * @param hfm_ustat FM module status register.
1270 static int mass_erase(struct target
* target
, uint16_t * hfm_ustat
){
1272 retval
= dsp5680xx_f_execute_command(target
,HFM_MASS_ERASE
,0,0,hfm_ustat
,1);
1276 int dsp5680xx_f_erase(struct target
* target
, int first
, int last
){
1278 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1279 retval
= dsp5680xx_halt(target
);
1280 err_check_propagate(retval
);
1282 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1284 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1285 retval
= dsp5680xx_f_SIM_reset(target
);
1286 err_check_propagate(retval
);
1287 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1289 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1290 retval
= eonce_set_hfmdiv(target
);
1291 err_check_propagate(retval
);
1294 int do_mass_erase
= ((!(first
|last
)) || ((first
==0)&&(last
== (HFM_SECTOR_COUNT
-1))));
1297 retval
= mass_erase(target
,&hfm_ustat
);
1298 err_check_propagate(retval
);
1299 last
= HFM_SECTOR_COUNT
-1;
1301 for(int i
= first
;i
<=last
;i
++){
1302 retval
= erase_sector(target
,i
,&hfm_ustat
);
1303 err_check_propagate(retval
);
1310 * Algorithm for programming normal p: flash
1311 * Follow state machine from "56F801x Peripheral Reference Manual"@163.
1312 * Registers to set up before calling:
1313 * r0: TX/RX high address.
1314 * r2: FM module base address.
1315 * r3: Destination address in flash.
1317 * hfm_wait: // wait for command to finish
1318 * brclr #0x40,x:(r2+0x13),hfm_wait
1319 * rx_check: // wait for input buffer full
1320 * brclr #0x01,x:(r0-2),rx_check
1321 * move.w x:(r0),y0 // read from Rx buffer
1323 * move.w #0x20,x:(r2+0x14) // write PGM command
1324 * move.w #0x80,x:(r2+0x13) // start the command
1325 * brclr #0x20,X:(R2+0x13),accerr_check // protection violation check
1326 * bfset #0x20,X:(R2+0x13) // clear pviol
1329 * brclr #0x10,X:(R2+0x13),hfm_wait // access error check
1330 * bfset #0x10,X:(R2+0x13) // clear accerr
1331 * bra hfm_wait // loop
1332 *0x00000073 0x8A460013407D brclr #0x40,X:(R2+0x13),*+0
1333 *0x00000076 0xE700 nop
1334 *0x00000077 0xE700 nop
1335 *0x00000078 0x8A44FFFE017B brclr #1,X:(R0-2),*-2
1336 *0x0000007B 0xE700 nop
1337 *0x0000007C 0xF514 move.w X:(R0),Y0
1338 *0x0000007D 0x8563 move.w Y0,P:(R3)+
1339 *0x0000007E 0x864600200014 move.w #0x20,X:(R2+0x14)
1340 *0x00000081 0x864600800013 move.w #0x80,X:(R2+0x13)
1341 *0x00000084 0x8A4600132004 brclr #0x20,X:(R2+0x13),*+7
1342 *0x00000087 0x824600130020 bfset #0x20,X:(R2+0x13)
1343 *0x0000008A 0xA968 bra *-23
1344 *0x0000008B 0x8A4600131065 brclr #0x10,X:(R2+0x13),*-24
1345 *0x0000008E 0x824600130010 bfset #0x10,X:(R2+0x13)
1346 *0x00000091 0xA961 bra *-30
1348 const uint16_t pgm_write_pflash
[] = {0x8A46,0x0013,0x407D,0xE700,0xE700,0x8A44,0xFFFE,0x017B,0xE700,0xF514,0x8563,0x8646,0x0020,0x0014,0x8646,0x0080,0x0013,0x8A46,0x0013,0x2004,0x8246,0x0013,0x0020,0xA968,0x8A46,0x0013,0x1065,0x8246,0x0013,0x0010,0xA961};
1349 const uint32_t pgm_write_pflash_length
= 31;
1351 static int shots
= 0;//TODO testing! remove!
1352 static int hits
= 0;//TODO testing! remove!
1354 int dsp5680xx_f_wr(struct target
* target
, uint8_t *buffer
, uint32_t address
, uint32_t count
){
1355 shots
++;//TODO testing! remove!
1356 int retval
= ERROR_OK
;
1357 uint16_t* buff16
= (uint16_t *) buffer
;
1358 if (dsp5680xx_target_status(target
,NULL
,NULL
) != TARGET_HALTED
){
1359 retval
= eonce_enter_debug_mode(target
,NULL
);
1360 err_check_propagate(retval
);
1362 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1363 // Download the pgm that flashes.
1364 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1365 uint32_t my_favourite_ram_address
= 0x8700; // This seems to be a safe address. This one is the one used by codewarrior in 56801x_flash.cfg
1366 retval
= dsp5680xx_write(target
, my_favourite_ram_address
, 1, pgm_write_pflash_length
*2,(uint8_t *) pgm_write_pflash
);
1367 err_check_propagate(retval
);
1368 retval
= dsp5680xx_execute_queue();
1369 err_check_propagate(retval
);
1370 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1372 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1373 retval
= eonce_set_hfmdiv(target
);
1374 err_check_propagate(retval
);
1375 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1376 // Setup registers needed by pgm_write_pflash
1377 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1381 retval
= eonce_move_long_to_r3(target
,address
); // Destination address to r3
1382 err_check_propagate(retval
);
1383 eonce_load_TX_RX_high_to_r0(target
); // TX/RX reg address to r0
1384 err_check_propagate(retval
);
1385 retval
= eonce_move_long_to_r2(target
,HFM_BASE_ADDR
);// FM base address to r2
1386 err_check_propagate(retval
);
1387 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1388 // Run flashing program.
1389 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1390 retval
= eonce_move_value_at_r2_disp(target
,0x00,HFM_CNFG
); // write to HFM_CNFG (lock=0, select bank)
1391 err_check_propagate(retval
);
1392 retval
= eonce_move_value_at_r2_disp(target
,0x04,HFM_USTAT
);// write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
1393 err_check_propagate(retval
);
1394 retval
= eonce_move_value_at_r2_disp(target
,0x10,HFM_USTAT
);// clear only one bit at a time
1395 err_check_propagate(retval
);
1396 retval
= eonce_move_value_at_r2_disp(target
,0x20,HFM_USTAT
);
1397 err_check_propagate(retval
);
1398 retval
= eonce_move_value_at_r2_disp(target
,0x00,HFM_PROT
);// write to HMF_PROT, clear protection
1399 err_check_propagate(retval
);
1400 retval
= eonce_move_value_at_r2_disp(target
,0x00,HFM_PROTB
);// write to HMF_PROTB, clear protection
1401 err_check_propagate(retval
);
1403 //TODO implement handling of odd number of words.
1404 retval
= ERROR_FAIL
;
1405 err_check(retval
,"Cannot handle odd number of words.");
1409 retval
= dsp5680xx_execute_queue();
1410 err_check_propagate(retval
);
1412 uint32_t drscan_data
;
1413 retval
= eonce_tx_upper_data(target
,buff16
[0],&drscan_data
);
1414 err_check_propagate(retval
);
1416 retval
= dsp5680xx_resume(target
,0,my_favourite_ram_address
,0,0);
1417 err_check_propagate(retval
);
1419 int counter
= FLUSH_COUNT_FLASH
;
1422 for(i
=1; (i
<count
/2)&&(i
<HFM_SIZE_WORDS
); i
++){
1425 counter
= FLUSH_COUNT_FLASH
;
1427 retval
= eonce_tx_upper_data(target
,buff16
[i
],&drscan_data
);
1428 if(retval
!=ERROR_OK
){
1430 err_check_propagate(retval
);
1435 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1437 // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1440 retval
= dsp5680xx_f_signature(target
,address
,i
,&signature
);
1441 err_check_propagate(retval
);
1442 pc_crc
= perl_crc(buff16
,i
);
1443 if(pc_crc
!= signature
){
1444 retval
= ERROR_FAIL
;
1445 err_check(retval
,"Flashed data failed CRC check, flash again!");
1447 hits
++;//TODO testing! remove!
1448 LOG_USER("Shots: %d\nHits: %d",shots
,hits
);//TODO testing! remove!
1452 int dsp5680xx_f_unlock(struct target
* target
){
1454 if(target
->tap
->enabled
){
1455 //TODO find a way to switch to the master tap here.
1456 LOG_ERROR("Master tap must be enabled to unlock flash.");
1457 return ERROR_TARGET_FAILURE
;
1459 uint32_t data_to_shift_in
= MASTER_TAP_CMD_FLASH_ERASE
;
1460 uint32_t data_shifted_out
;
1461 retval
= dsp5680xx_irscan(target
,&data_to_shift_in
,&data_shifted_out
,8);
1462 err_check_propagate(retval
);
1463 data_to_shift_in
= HFM_CLK_DEFAULT
;
1464 retval
= dsp5680xx_drscan(target
,((uint8_t *) & data_to_shift_in
),((uint8_t *)&data_shifted_out
),8);
1465 err_check_propagate(retval
);
1469 int dsp5680xx_f_lock(struct target
* target
){
1471 uint16_t lock_word
[] = {HFM_LOCK_FLASH
,HFM_LOCK_FLASH
};
1472 retval
= dsp5680xx_f_wr(target
,(uint8_t *)(lock_word
),HFM_LOCK_ADDR_L
,4);
1473 err_check_propagate(retval
);
1477 static int dsp5680xx_step(struct target
* target
,int current
, uint32_t address
, int handle_breakpoints
){
1479 FILE * log_results
= fopen("/home/rrosa/rrosa/test_logs/do_it_again.log","a");
1480 if (log_results
== NULL
)
1481 err_check(ERROR_FAIL
,"failed to open log");
1482 retval
= fprintf(log_results
,"%d\t%d\n",shots
,hits
);
1484 err_check(ERROR_FAIL
,"failed to write to log");
1485 retval
= fclose(log_results
);
1487 err_check(ERROR_FAIL
,"failed to close log");
1489 err_check(ERROR_FAIL
,"Not implemented yet.");
1492 /** Holds methods for dsp5680xx targets. */
1493 struct target_type dsp5680xx_target
= {
1494 .name
= "dsp5680xx",
1496 .poll
= dsp5680xx_poll
,
1497 .arch_state
= dsp5680xx_arch_state
,
1499 .target_request_data
= NULL
,
1501 .halt
= dsp5680xx_halt
,
1502 .resume
= dsp5680xx_resume
,
1503 .step
= dsp5680xx_step
,
1505 .write_buffer
= dsp5680xx_write_buffer
,
1506 .read_buffer
= dsp5680xx_read_buffer
,
1508 .assert_reset
= dsp5680xx_assert_reset
,
1509 .deassert_reset
= dsp5680xx_deassert_reset
,
1510 .soft_reset_halt
= dsp5680xx_soft_reset_halt
,
1512 .read_memory
= dsp5680xx_read
,
1513 .write_memory
= dsp5680xx_write
,
1514 .bulk_write_memory
= dsp5680xx_bulk_write_memory
,
1516 .checksum_memory
= dsp5680xx_checksum_memory
,
1518 .target_create
= dsp5680xx_target_create
,
1519 .init_target
= dsp5680xx_init_target
,