| blob | 38374ffe50ad0ed3f61cd9639c01b9178d080fe4 |
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
24 /***************************************************************************
25 * STELLARIS is tested on LM3S811, LM3S6965
26 ***************************************************************************/
27 #ifdef HAVE_CONFIG_H
29 #endif
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
37 #define DID0_VER(did0) ((did0 >> 28)&0x07)
46 {
215 };
218 {
223 "Tempest"
224 };
226 /***************************************************************************
227 * openocd command interface *
228 ***************************************************************************/
230 /* flash_bank stellaris <base> <size> 0 0 <target#>
231 */
233 {
237 {
240 }
248 /* part wasn't probed for info yet */
251 /* TODO Specify the main crystal speed in kHz using an optional
252 * argument; ditto, the speed of an external oscillator used
253 * instead of a crystal. Avoid programming flash using IOSC.
254 */
256 }
259 {
266 /* Read main and master clock freqency register */
270 {
272 }
273 else
274 {
276 }
278 buf_size,
281 device_class,
290 buf_size,
302 buf_size,
303 "master clock: %ikHz%s, "
313 {
315 buf_size,
324 }
326 }
328 /***************************************************************************
329 * chip identification and status *
330 ***************************************************************************/
332 /* Set the flash timimg register to match current clocking */
334 {
341 }
364 /* parts before DustDevil use just 4 bits for xtal spec */
374 };
376 /** Read clock configuration and set stellaris_info->usec_clocks. */
378 {
403 /* NOTE: post-Sandstorm parts have RCC2 which may override
404 * parts of RCC ... with more sysdiv options, option for
405 * 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
406 * as zero, so the "use RCC2" flag is always clear.
407 */
413 /* FIXME Tempest parts have an additional lsb for
414 * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
415 */
416 }
421 {
434 /* Sandstorm doesn't have this 30K +/- 30% osc */
439 /* not all parts support hibernation */
446 }
448 /* PLL is used if it's not bypassed; its output is 200 MHz
449 * even when it runs at 400 MHz (adds divide-by-two stage).
450 */
456 else
458 }
460 /* Read device id register, main clock frequency register and fill in driver info structure */
462 {
468 /* Read and parse chip identification register */
478 {
481 }
484 {
487 }
492 {
495 }
497 /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
498 * is 12 MHz, but some older parts have 15 MHz. A few data sheets
499 * even give _both_ numbers! We'll use current numbers; IOSC is
500 * always approximate.
501 *
502 * For Tempest: IOSC is calibrated, 16 MHz
503 */
510 /*
511 * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
512 * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
513 * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
514 */
518 }
527 /* FALL THROUGH */
533 }
538 }
541 {
544 }
556 /* REVISIT for at least Tempest parts, read NVMSTAT.FWB too.
557 * That exposes a 32-word Flash Write Buffer ... enabling
558 * writes of more than one word at a time.
559 */
562 }
564 /***************************************************************************
565 * flash operations *
566 ***************************************************************************/
569 {
581 /* Read each Flash Memory Protection Program Enable (FMPPE) register
582 * to report any pages that we can't write. Ignore the Read Enable
583 * register (FMPRE).
584 */
587 i++) {
606 }
607 }
608 }
610 done:
612 }
615 {
622 {
625 }
631 {
633 }
636 {
638 }
640 /* Refresh flash controller timing */
644 /* Clear and disable flash programming interrupts */
648 /* REVISIT this clobbers state set by any halted firmware ...
649 * it might want to process those IRQs.
650 */
653 {
654 /* Address is first word in page */
656 /* Write erase command */
658 /* Wait until erase complete */
659 do
660 {
662 }
665 /* Check acess violations */
668 {
672 }
675 }
678 }
681 {
689 {
692 }
695 {
699 }
704 /* lockregions are 2 pages ... must protect [even..odd] */
708 {
711 }
713 /* Refresh flash controller timing */
717 /* convert from pages to lockregions */
721 /* FIXME this assumes single FMPPE, for a max of 64K of flash!!
722 * Current parts can be much bigger.
723 */
727 }
734 /* Clear and disable flash programming interrupts */
738 /* REVISIT this clobbers state set by any halted firmware ...
739 * it might want to process those IRQs.
740 */
745 /* Commit FMPPE */
748 /* Write commit command */
749 /* REVISIT safety check, since this cannot be undone
750 * except by the "Recover a locked device" procedure.
751 * REVISIT DustDevil-A0 parts have an erratum making FMPPE commits
752 * inadvisable ... it makes future mass erase operations fail.
753 */
755 /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
757 /* Wait until erase complete */
758 do
759 {
761 }
764 /* Check acess violations */
767 {
771 }
774 }
777 {
778 /*
779 Call with :
780 r0 = buffer address
781 r1 = destination address
782 r2 = bytecount (in) - endaddr (work)
784 Used registers:
785 r3 = pFLASH_CTRL_BASE
786 r4 = FLASHWRITECMD
787 r5 = #1
788 r6 = bytes written
789 r7 = temp reg
790 */
795 /* mainloop: */
800 /* waitloop: */
809 /* pFLASH_CTRL_BASE: */
811 /* FLASHWRITECMD: */
813 };
817 {
827 /* power of two, and multiple of word size */
830 /* for small buffers it's faster not to download an algorithm */
837 /* flash write code */
838 if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
839 {
842 };
844 /* plus a buffer big enough for this data */
848 /* memory buffer */
850 {
853 {
856 }
859 };
873 {
891 {
894 retval);
897 }
902 }
904 /* REVISIT we could speed up writing multi-section images by
905 * not freeing the initialized write_algorithm this way.
906 */
916 }
918 static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
919 {
930 {
933 }
942 {
945 }
950 /* Refresh flash controller timing */
954 /* Clear and disable flash programming interrupts */
958 /* REVISIT this clobbers state set by any halted firmware ...
959 * it might want to process those IRQs.
960 */
962 /* multiple words to be programmed? */
964 {
965 /* try using a block write */
967 words_remaining);
969 {
971 {
973 }
975 {
976 /* if an error occured, we examine the reason, and quit */
981 }
982 }
983 else
984 {
988 }
989 }
992 {
996 /* Program one word */
1000 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1001 /* Wait until write complete */
1002 do
1003 {
1009 words_remaining--;
1010 }
1013 {
1018 {
1020 bytes_remaining--;
1021 bytes_written++;
1022 }
1027 /* Program one word */
1031 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1032 /* Wait until write complete */
1033 do
1034 {
1037 }
1039 /* Check access violations */
1042 {
1045 }
1047 }
1050 {
1054 /* If this is a stellaris chip, it has flash; probe() is just
1055 * to figure out how much is present. Only do it once.
1056 */
1060 /* stellaris_read_part_info() already handled error checking and
1061 * reporting. Note that it doesn't write, so we don't care about
1062 * whether the target is halted or not.
1063 */
1068 /* provide this for the benefit of the NOR flash framework */
1073 {
1078 }
1081 }
1084 {
1093 {
1096 }
1101 /* Refresh flash controller timing */
1105 /* Clear and disable flash programming interrupts */
1109 /* REVISIT this clobbers state set by any halted firmware ...
1110 * it might want to process those IRQs.
1111 */
1115 /* Wait until erase complete */
1116 do
1117 {
1119 }
1122 /* if device has > 128k, then second erase cycle is needed
1123 * this is only valid for older devices, but will not hurt */
1125 {
1128 /* Wait until erase complete */
1129 do
1130 {
1132 }
1134 }
1137 }
1140 {
1144 {
1147 }
1155 {
1156 /* set all sectors as erased */
1158 {
1160 }
1163 }
1164 else
1165 {
1167 }
1170 }
1172 /**
1173 * Perform the Stellaris "Recovering a 'Locked' Device procedure.
1174 * This performs a mass erase and then restores all nonvolatile registers
1175 * (including USER_* registers and flash lock bits) to their defaults.
1176 * Accordingly, flash can be reprogrammed, and JTAG can be used.
1177 *
1178 * NOTE that DustDevil parts (at least rev A0 silicon) have errata which
1179 * can affect this operation if flash protection has been enabled.
1180 */
1182 {
1190 /* REVISIT ... it may be worth sanity checking that the AP is
1191 * inactive before we start. ARM documents that switching a DP's
1192 * mode while it's active can cause fault modes that need a power
1193 * cycle to recover.
1194 */
1196 /* assert SRST */
1200 }
1211 }
1213 /* de-assert SRST */
1217 /* wait 400+ msec ... OK, "1+ second" is simpler */
1220 /* USER INTERVENTION required for the power cycle
1221 * Restarting OpenOCD is likely needed because of mode switching.
1222 */
1226 done:
1228 }
1231 {
1237 },
1238 {
1244 },
1245 COMMAND_REGISTRATION_DONE
1246 };
1248 {
1253 },
1254 COMMAND_REGISTRATION_DONE
1255 };
1270 };