?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
arm926ejs: -Wshadow warning fix
[openocd/dnglaze.git] / src / target / arm926ejs.c
blobd68e5ca342a2d27fb434348520428adde67d4446
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "arm926ejs.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
30 #include "register.h"
31 #include "arm_opcodes.h"
32
33
34 /*
35 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
36 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
37 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
38 *
39 * 1 ... core debugging
40 * 2 ... EmbeddedICE
41 * 3 ... external boundary scan (SoC-specific, unused here)
42 * 6 ... ETM
43 * 15 ... coprocessor 15
44 */
45
46 #if 0
47 #define _DEBUG_INSTRUCTION_EXECUTION_
48 #endif
49
50 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
51
52 static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2,
53 uint32_t CRn, uint32_t CRm, uint32_t *value)
54 {
55 int retval = ERROR_OK;
56 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
57 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
58 uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
59 struct scan_field fields[4];
60 uint8_t address_buf[2] = {0, 0};
61 uint8_t nr_w_buf = 0;
62 uint8_t access_t = 1;
63
64 buf_set_u32(address_buf, 0, 14, address);
65
66 if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
67 {
68 return retval;
69 }
70 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
71
72 fields[0].num_bits = 32;
73 fields[0].out_value = NULL;
74 fields[0].in_value = (uint8_t *)value;
75
76 fields[1].num_bits = 1;
77 fields[1].out_value = &access_t;
78 fields[1].in_value = &access_t;
79
80 fields[2].num_bits = 14;
81 fields[2].out_value = address_buf;
82 fields[2].in_value = NULL;
83
84 fields[3].num_bits = 1;
85 fields[3].out_value = &nr_w_buf;
86 fields[3].in_value = NULL;
87
88 jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
89
90 long long then = timeval_ms();
91
92 for (;;)
93 {
94 /* rescan with NOP, to wait for the access to complete */
95 access_t = 0;
96 nr_w_buf = 0;
97 jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
98
99 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
100
101 if ((retval = jtag_execute_queue()) != ERROR_OK)
102 {
103 return retval;
104 }
105
106 if (buf_get_u32(&access_t, 0, 1) == 1)
107 {
108 break;
109 }
110
111 /* 10ms timeout */
112 if ((timeval_ms()-then)>10)
113 {
114 LOG_ERROR("cp15 read operation timed out");
115 return ERROR_FAIL;
116 }
117 }
118
119 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
120 LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
121 #endif
122
123 arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
124
125 return ERROR_OK;
126 }
127
128 static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1,
129 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
130 {
131 if (cpnum != 15) {
132 LOG_ERROR("Only cp15 is supported");
133 return ERROR_FAIL;
134 }
135 return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
136 }
137
138 static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2,
139 uint32_t CRn, uint32_t CRm, uint32_t value)
140 {
141 int retval = ERROR_OK;
142 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
143 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
144 uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
145 struct scan_field fields[4];
146 uint8_t value_buf[4];
147 uint8_t address_buf[2] = {0, 0};
148 uint8_t nr_w_buf = 1;
149 uint8_t access_t = 1;
150
151 buf_set_u32(address_buf, 0, 14, address);
152 buf_set_u32(value_buf, 0, 32, value);
153
154 if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
155 {
156 return retval;
157 }
158 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
159
160 fields[0].num_bits = 32;
161 fields[0].out_value = value_buf;
162 fields[0].in_value = NULL;
163
164 fields[1].num_bits = 1;
165 fields[1].out_value = &access_t;
166 fields[1].in_value = &access_t;
167
168 fields[2].num_bits = 14;
169 fields[2].out_value = address_buf;
170 fields[2].in_value = NULL;
171
172 fields[3].num_bits = 1;
173 fields[3].out_value = &nr_w_buf;
174 fields[3].in_value = NULL;
175
176 jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
177
178 long long then = timeval_ms();
179
180 for (;;)
181 {
182 /* rescan with NOP, to wait for the access to complete */
183 access_t = 0;
184 nr_w_buf = 0;
185 jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
186 if ((retval = jtag_execute_queue()) != ERROR_OK)
187 {
188 return retval;
189 }
190
191 if (buf_get_u32(&access_t, 0, 1) == 1)
192 {
193 break;
194 }
195
196 /* 10ms timeout */
197 if ((timeval_ms()-then)>10)
198 {
199 LOG_ERROR("cp15 write operation timed out");
200 return ERROR_FAIL;
201 }
202 }
203
204 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
205 LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
206 #endif
207
208 arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
209
210 return ERROR_OK;
211 }
212
213 static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1,
214 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
215 {
216 if (cpnum != 15) {
217 LOG_ERROR("Only cp15 is supported");
218 return ERROR_FAIL;
219 }
220 return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
221 }
222
223 static int arm926ejs_examine_debug_reason(struct target *target)
224 {
225 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
226 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
227 int debug_reason;
228 int retval;
229
230 embeddedice_read_reg(dbg_stat);
231 if ((retval = jtag_execute_queue()) != ERROR_OK)
232 return retval;
233
234 /* Method-Of-Entry (MOE) field */
235 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
236
237 switch (debug_reason)
238 {
239 case 0:
240 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
241 /* ... since last restart or debug reset ... */
242 target->debug_reason = DBG_REASON_DBGRQ;
243 break;
244 case 1:
245 LOG_DEBUG("breakpoint from EICE unit 0");
246 target->debug_reason = DBG_REASON_BREAKPOINT;
247 break;
248 case 2:
249 LOG_DEBUG("breakpoint from EICE unit 1");
250 target->debug_reason = DBG_REASON_BREAKPOINT;
251 break;
252 case 3:
253 LOG_DEBUG("soft breakpoint (BKPT instruction)");
254 target->debug_reason = DBG_REASON_BREAKPOINT;
255 break;
256 case 4:
257 LOG_DEBUG("vector catch breakpoint");
258 target->debug_reason = DBG_REASON_BREAKPOINT;
259 break;
260 case 5:
261 LOG_DEBUG("external breakpoint");
262 target->debug_reason = DBG_REASON_BREAKPOINT;
263 break;
264 case 6:
265 LOG_DEBUG("watchpoint from EICE unit 0");
266 target->debug_reason = DBG_REASON_WATCHPOINT;
267 break;
268 case 7:
269 LOG_DEBUG("watchpoint from EICE unit 1");
270 target->debug_reason = DBG_REASON_WATCHPOINT;
271 break;
272 case 8:
273 LOG_DEBUG("external watchpoint");
274 target->debug_reason = DBG_REASON_WATCHPOINT;
275 break;
276 case 9:
277 LOG_DEBUG("internal debug request");
278 target->debug_reason = DBG_REASON_DBGRQ;
279 break;
280 case 10:
281 LOG_DEBUG("external debug request");
282 target->debug_reason = DBG_REASON_DBGRQ;
283 break;
284 case 11:
285 LOG_DEBUG("debug re-entry from system speed access");
286 /* This is normal when connecting to something that's
287 * already halted, or in some related code paths, but
288 * otherwise is surprising (and presumably wrong).
289 */
290 switch (target->debug_reason) {
291 case DBG_REASON_DBGRQ:
292 break;
293 default:
294 LOG_ERROR("unexpected -- debug re-entry");
295 /* FALLTHROUGH */
296 case DBG_REASON_UNDEFINED:
297 target->debug_reason = DBG_REASON_DBGRQ;
298 break;
299 }
300 break;
301 case 12:
302 /* FIX!!!! here be dragons!!! We need to fail here so
303 * the target will interpreted as halted but we won't
304 * try to talk to it right now... a resume + halt seems
305 * to sync things up again. Please send an email to
306 * openocd development mailing list if you have hardware
307 * to donate to look into this problem....
308 */
309 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
310 target->debug_reason = DBG_REASON_DBGRQ;
311 break;
312 default:
313 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
314 /* Oh agony! should we interpret this as a halt request or
315 * that the target stopped on it's own accord?
316 */
317 target->debug_reason = DBG_REASON_DBGRQ;
318 /* if we fail here, we won't talk to the target and it will
319 * be reported to be in the halted state */
320 break;
321 }
322
323 return ERROR_OK;
324 }
325
326 static uint32_t arm926ejs_get_ttb(struct target *target)
327 {
328 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
329 int retval;
330 uint32_t ttb = 0x0;
331
332 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
333 return retval;
334
335 return ttb;
336 }
337
338 static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
339 int d_u_cache, int i_cache)
340 {
341 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
342 uint32_t cp15_control;
343
344 /* read cp15 control register */
345 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
346 jtag_execute_queue();
347
348 if (mmu)
349 {
350 /* invalidate TLB */
351 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
352
353 cp15_control &= ~0x1U;
354 }
355
356 if (d_u_cache)
357 {
358 uint32_t debug_override;
359 /* read-modify-write CP15 debug override register
360 * to enable "test and clean all" */
361 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
362 debug_override |= 0x80000;
363 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
364
365 /* clean and invalidate DCache */
366 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
367
368 /* write CP15 debug override register
369 * to disable "test and clean all" */
370 debug_override &= ~0x80000;
371 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
372
373 cp15_control &= ~0x4U;
374 }
375
376 if (i_cache)
377 {
378 /* invalidate ICache */
379 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
380
381 cp15_control &= ~0x1000U;
382 }
383
384 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
385 }
386
387 static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
388 int d_u_cache, int i_cache)
389 {
390 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
391 uint32_t cp15_control;
392
393 /* read cp15 control register */
394 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
395 jtag_execute_queue();
396
397 if (mmu)
398 cp15_control |= 0x1U;
399
400 if (d_u_cache)
401 cp15_control |= 0x4U;
402
403 if (i_cache)
404 cp15_control |= 0x1000U;
405
406 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
407 }
408
409 static void arm926ejs_post_debug_entry(struct target *target)
410 {
411 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
412
413 /* examine cp15 control reg */
414 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
415 jtag_execute_queue();
416 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
417
418 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
419 {
420 uint32_t cache_type_reg;
421 /* identify caches */
422 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
423 jtag_execute_queue();
424 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
425 }
426
427 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
428 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
429 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
430
431 /* save i/d fault status and address register */
432 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
433 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
434 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
435
436 LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
437 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
438
439 uint32_t cache_dbg_ctrl;
440
441 /* read-modify-write CP15 cache debug control register
442 * to disable I/D-cache linefills and force WT */
443 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
444 cache_dbg_ctrl |= 0x7;
445 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
446 }
447
448 static void arm926ejs_pre_restore_context(struct target *target)
449 {
450 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
451
452 /* restore i/d fault status and address register */
453 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
454 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
455 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
456
457 uint32_t cache_dbg_ctrl;
458
459 /* read-modify-write CP15 cache debug control register
460 * to reenable I/D-cache linefills and disable WT */
461 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
462 cache_dbg_ctrl &= ~0x7;
463 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
464 }
465
466 static const char arm926_not[] = "target is not an ARM926";
467
468 static int arm926ejs_verify_pointer(struct command_context *cmd_ctx,
469 struct arm926ejs_common *arm926)
470 {
471 if (arm926->common_magic != ARM926EJS_COMMON_MAGIC) {
472 command_print(cmd_ctx, arm926_not);
473 return ERROR_TARGET_INVALID;
474 }
475 return ERROR_OK;
476 }
477
478 /** Logs summary of ARM926 state for a halted target. */
479 int arm926ejs_arch_state(struct target *target)
480 {
481 static const char *state[] =
482 {
483 "disabled", "enabled"
484 };
485
486 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
487 struct arm *armv4_5;
488
489 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
490 {
491 LOG_ERROR("BUG: %s", arm926_not);
492 return ERROR_TARGET_INVALID;
493 }
494
495 armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
496
497 arm_arch_state(target);
498 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
499 state[arm926ejs->armv4_5_mmu.mmu_enabled],
500 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
501 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
502
503 return ERROR_OK;
504 }
505
506 int arm926ejs_soft_reset_halt(struct target *target)
507 {
508 int retval = ERROR_OK;
509 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
510 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
511 struct arm *armv4_5 = &arm7_9->armv4_5_common;
512 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
513
514 if ((retval = target_halt(target)) != ERROR_OK)
515 {
516 return retval;
517 }
518
519 long long then = timeval_ms();
520 int timeout;
521 while (!(timeout = ((timeval_ms()-then) > 1000)))
522 {
523 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
524 {
525 embeddedice_read_reg(dbg_stat);
526 if ((retval = jtag_execute_queue()) != ERROR_OK)
527 {
528 return retval;
529 }
530 } else
531 {
532 break;
533 }
534 if (debug_level >= 1)
535 {
536 /* do not eat all CPU, time out after 1 se*/
537 alive_sleep(100);
538 } else
539 {
540 keep_alive();
541 }
542 }
543 if (timeout)
544 {
545 LOG_ERROR("Failed to halt CPU after 1 sec");
546 return ERROR_TARGET_TIMEOUT;
547 }
548
549 target->state = TARGET_HALTED;
550
551 /* SVC, ARM state, IRQ and FIQ disabled */
552 uint32_t cpsr;
553
554 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
555 cpsr &= ~0xff;
556 cpsr |= 0xd3;
557 arm_set_cpsr(armv4_5, cpsr);
558 armv4_5->cpsr->dirty = 1;
559
560 /* start fetching from 0x0 */
561 buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
562 armv4_5->pc->dirty = 1;
563 armv4_5->pc->valid = 1;
564
565 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
566 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
567 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
568 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
569
570 return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
571 }
572
573 /** Writes a buffer, in the specified word size, with current MMU settings. */
574 int arm926ejs_write_memory(struct target *target, uint32_t address,
575 uint32_t size, uint32_t count, uint8_t *buffer)
576 {
577 int retval;
578 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
579
580 /* FIX!!!! this should be cleaned up and made much more general. The
581 * plan is to write up and test on arm926ejs specifically and
582 * then generalize and clean up afterwards.
583 *
584 *
585 * Also it should be moved to the callbacks that handle breakpoints
586 * specifically and not the generic memory write fn's. See XScale code.
587 **/
588 if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
589 {
590 /* special case the handling of single word writes to bypass MMU
591 * to allow implementation of breakpoints in memory marked read only
592 * by MMU */
593 if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
594 {
595 /* flush and invalidate data cache
596 *
597 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
598 *
599 */
600 retval = arm926ejs->write_cp15(target, 0, 1, 7, 10, address&~0x3);
601 if (retval != ERROR_OK)
602 return retval;
603 }
604
605 uint32_t pa;
606 retval = target->type->virt2phys(target, address, &pa);
607 if (retval != ERROR_OK)
608 return retval;
609
610 /* write directly to physical memory bypassing any read only MMU bits, etc. */
611 retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
612 if (retval != ERROR_OK)
613 return retval;
614 } else
615 {
616 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
617 return retval;
618 }
619
620 /* If ICache is enabled, we have to invalidate affected ICache lines
621 * the DCache is forced to write-through, so we don't have to clean it here
622 */
623 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
624 {
625 if (count <= 1)
626 {
627 /* invalidate ICache single entry with MVA */
628 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
629 }
630 else
631 {
632 /* invalidate ICache */
633 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
634 }
635 }
636
637 return retval;
638 }
639
640 static int arm926ejs_write_phys_memory(struct target *target,
641 uint32_t address, uint32_t size,
642 uint32_t count, uint8_t *buffer)
643 {
644 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
645
646 return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu,
647 address, size, count, buffer);
648 }
649
650 static int arm926ejs_read_phys_memory(struct target *target,
651 uint32_t address, uint32_t size,
652 uint32_t count, uint8_t *buffer)
653 {
654 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
655
656 return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu,
657 address, size, count, buffer);
658 }
659
660 int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs,
661 struct jtag_tap *tap)
662 {
663 struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
664
665 arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
666 arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
667
668 /* initialize arm7/arm9 specific info (including armv4_5) */
669 arm9tdmi_init_arch_info(target, arm7_9, tap);
670
671 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
672
673 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
674 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
675
676 arm926ejs->read_cp15 = arm926ejs_cp15_read;
677 arm926ejs->write_cp15 = arm926ejs_cp15_write;
678 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
679 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
680 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
681 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
682 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
683 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
684 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
685 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
686
687 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
688
689 /* The ARM926EJ-S implements the ARMv5TE architecture which
690 * has the BKPT instruction, so we don't have to use a watchpoint comparator
691 */
692 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
693 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
694
695 return ERROR_OK;
696 }
697
698 static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
699 {
700 struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
701
702 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
703 target->tap->ir_capture_mask = 0x0f;
704
705 return arm926ejs_init_arch_info(target, arm926ejs, target->tap);
706 }
707
708 COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
709 {
710 int retval;
711 struct target *target = get_current_target(CMD_CTX);
712 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
713
714 retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs);
715 if (retval != ERROR_OK)
716 return retval;
717
718 return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache);
719 }
720
721 static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical)
722 {
723 uint32_t cb;
724 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
725
726 uint32_t ret;
727 int retval = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu,
728 virtual, &cb, &ret);
729 if (retval != ERROR_OK)
730 return retval;
731 *physical = ret;
732 return ERROR_OK;
733 }
734
735 static int arm926ejs_mmu(struct target *target, int *enabled)
736 {
737 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
738
739 if (target->state != TARGET_HALTED)
740 {
741 LOG_ERROR("Target not halted");
742 return ERROR_TARGET_INVALID;
743 }
744 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
745 return ERROR_OK;
746 }
747
748 static const struct command_registration arm926ejs_exec_command_handlers[] = {
749 {
750 .name = "cache_info",
751 .handler = arm926ejs_handle_cache_info_command,
752 .mode = COMMAND_EXEC,
753 .help = "display information about target caches",
754
755 },
756 COMMAND_REGISTRATION_DONE
757 };
758 const struct command_registration arm926ejs_command_handlers[] = {
759 {
760 .chain = arm9tdmi_command_handlers,
761 },
762 {
763 .name = "arm926ejs",
764 .mode = COMMAND_ANY,
765 .help = "arm926ejs command group",
766 .chain = arm926ejs_exec_command_handlers,
767 },
768 COMMAND_REGISTRATION_DONE
769 };
770
771 /** Holds methods for ARM926 targets. */
772 struct target_type arm926ejs_target =
773 {
774 .name = "arm926ejs",
775
776 .poll = arm7_9_poll,
777 .arch_state = arm926ejs_arch_state,
778
779 .target_request_data = arm7_9_target_request_data,
780
781 .halt = arm7_9_halt,
782 .resume = arm7_9_resume,
783 .step = arm7_9_step,
784
785 .assert_reset = arm7_9_assert_reset,
786 .deassert_reset = arm7_9_deassert_reset,
787 .soft_reset_halt = arm926ejs_soft_reset_halt,
788
789 .get_gdb_reg_list = arm_get_gdb_reg_list,
790
791 .read_memory = arm7_9_read_memory,
792 .write_memory = arm926ejs_write_memory,
793 .bulk_write_memory = arm7_9_bulk_write_memory,
794
795 .checksum_memory = arm_checksum_memory,
796 .blank_check_memory = arm_blank_check_memory,
797
798 .run_algorithm = armv4_5_run_algorithm,
799
800 .add_breakpoint = arm7_9_add_breakpoint,
801 .remove_breakpoint = arm7_9_remove_breakpoint,
802 .add_watchpoint = arm7_9_add_watchpoint,
803 .remove_watchpoint = arm7_9_remove_watchpoint,
804
805 .commands = arm926ejs_command_handlers,
806 .target_create = arm926ejs_target_create,
807 .init_target = arm9tdmi_init_target,
808 .examine = arm7_9_examine,
809 .check_reset = arm7_9_check_reset,
810 .virt2phys = arm926ejs_virt2phys,
811 .mmu = arm926ejs_mmu,
812
813 .read_phys_memory = arm926ejs_read_phys_memory,
814 .write_phys_memory = arm926ejs_write_phys_memory,
815 };
Unoffical Testing Grounds for Dean Glazeski