src/target/arm_dpm.c

   1 /*
   2  * Copyright (C) 2009 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation, Inc.,
  17  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "arm_dpm.h"
  26 #include <jtag/jtag.h>
  27 #include "register.h"
  28 #include "breakpoints.h"
  29 #include "target_type.h"
  30 #include "arm_opcodes.h"
  31
  32
  33 /**
  34  * @file
  35  * Implements various ARM DPM operations using architectural debug registers.
  36  * These routines layer over core-specific communication methods to cope with
  37  * implementation differences between cores like ARM1136 and Cortex-A8.
  38  *
  39  * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
  40  * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
  41  * ARMv7-A and ARMv7-R edition (ARM DDI 0406B).  In OpenOCD, DPM operations
  42  * are abstracted through internal programming interfaces to share code and
  43  * to minimize needless differences in debug behavior between cores.
  44  */
  45
  46 /*----------------------------------------------------------------------*/
  47
  48 /*
  49  * Coprocessor support
  50  */
  51
  52 /* Read coprocessor */
  53 static int dpm_mrc(struct target *target, int cpnum,
  54                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  55                 uint32_t *value)
  56 {
  57         struct arm *arm = target_to_arm(target);
  58         struct arm_dpm *dpm = arm->dpm;
  59         int retval;
  60
  61         retval = dpm->prepare(dpm);
  62         if (retval != ERROR_OK)
  63                 return retval;
  64
  65         LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
  66                         (int) op1, (int) CRn,
  67                         (int) CRm, (int) op2);
  68
  69         /* read coprocessor register into R0; return via DCC */
  70         retval = dpm->instr_read_data_r0(dpm,
  71                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  72                         value);
  73
  74         /* (void) */ dpm->finish(dpm);
  75         return retval;
  76 }
  77
  78 static int dpm_mcr(struct target *target, int cpnum,
  79                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  80                 uint32_t value)
  81 {
  82         struct arm *arm = target_to_arm(target);
  83         struct arm_dpm *dpm = arm->dpm;
  84         int retval;
  85
  86         retval = dpm->prepare(dpm);
  87         if (retval != ERROR_OK)
  88                 return retval;
  89
  90         LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
  91                         (int) op1, (int) CRn,
  92                         (int) CRm, (int) op2);
  93
  94         /* read DCC into r0; then write coprocessor register from R0 */
  95         retval = dpm->instr_write_data_r0(dpm,
  96                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  97                         value);
  98
  99         /* (void) */ dpm->finish(dpm);
 100         return retval;
 101 }
 102
 103 /*----------------------------------------------------------------------*/
 104
 105 /*
 106  * Register access utilities
 107  */
 108
 109 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
 110  * Routines *must* restore the original mode before returning!!
 111  */
 112 static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 113 {
 114         int retval;
 115         uint32_t cpsr;
 116
 117         /* restore previous mode */
 118         if (mode == ARM_MODE_ANY)
 119                 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
 120
 121         /* else force to the specified mode */
 122         else
 123                 cpsr = mode;
 124
 125         retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
 126
 127         if (dpm->instr_cpsr_sync)
 128                 retval = dpm->instr_cpsr_sync(dpm);
 129
 130         return retval;
 131 }
 132
 133 /* just read the register -- rely on the core mode being right */
 134 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 135 {
 136         uint32_t value;
 137         int retval;
 138
 139         switch (regnum) {
 140         case 0 ... 14:
 141                 /* return via DCC:  "MCR p14, 0, Rnum, c0, c5, 0" */
 142                 retval = dpm->instr_read_data_dcc(dpm,
 143                                 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
 144                                 &value);
 145                 break;
 146         case 15:        /* PC */
 147                 /* "MOV r0, pc"; then return via DCC */
 148                 retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
 149
 150                 /* NOTE: this seems like a slightly awkward place to update
 151                  * this value ... but if the PC gets written (the only way
 152                  * to change what we compute), the arch spec says subsequent
 153                  * reads return values which are "unpredictable".  So this
 154                  * is always right except in those broken-by-intent cases.
 155                  */
 156                 switch (dpm->arm->core_state) {
 157                 case ARM_STATE_ARM:
 158                         value -= 8;
 159                         break;
 160                 case ARM_STATE_THUMB:
 161                 case ARM_STATE_THUMB_EE:
 162                         value -= 4;
 163                         break;
 164                 case ARM_STATE_JAZELLE:
 165                         /* core-specific ... ? */
 166                         LOG_WARNING("Jazelle PC adjustment unknown");
 167                         break;
 168                 }
 169                 break;
 170         default:
 171                 /* 16: "MRS r0, CPSR"; then return via DCC
 172                  * 17: "MRS r0, SPSR"; then return via DCC
 173                  */
 174                 retval = dpm->instr_read_data_r0(dpm,
 175                                 ARMV4_5_MRS(0, regnum & 1),
 176                                 &value);
 177                 break;
 178         }
 179
 180         if (retval == ERROR_OK) {
 181                 buf_set_u32(r->value, 0, 32, value);
 182                 r->valid = true;
 183                 r->dirty = false;
 184                 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
 185         }
 186
 187         return retval;
 188 }
 189
 190 /* just write the register -- rely on the core mode being right */
 191 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 192 {
 193         int retval;
 194         uint32_t value = buf_get_u32(r->value, 0, 32);
 195
 196         switch (regnum) {
 197         case 0 ... 14:
 198                 /* load register from DCC:  "MRC p14, 0, Rnum, c0, c5, 0" */
 199                 retval = dpm->instr_write_data_dcc(dpm,
 200                                 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
 201                                 value);
 202                 break;
 203         case 15:        /* PC */
 204                 /* read r0 from DCC; then "MOV pc, r0" */
 205                 retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
 206                 break;
 207         default:
 208                 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
 209                  * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
 210                  */
 211                 retval = dpm->instr_write_data_r0(dpm,
 212                                 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
 213                                 value);
 214
 215                 if (regnum == 16 && dpm->instr_cpsr_sync)
 216                         retval = dpm->instr_cpsr_sync(dpm);
 217
 218                 break;
 219         }
 220
 221         if (retval == ERROR_OK) {
 222                 r->dirty = false;
 223                 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
 224         }
 225
 226         return retval;
 227 }
 228
 229 /**
 230  * Read basic registers of the the current context:  R0 to R15, and CPSR;
 231  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
 232  * In normal operation this is called on entry to halting debug state,
 233  * possibly after some other operations supporting restore of debug state
 234  * or making sure the CPU is fully idle (drain write buffer, etc).
 235  */
 236 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
 237 {
 238         struct arm *arm = dpm->arm;
 239         uint32_t cpsr;
 240         int retval;
 241         struct reg *r;
 242
 243         retval = dpm->prepare(dpm);
 244         if (retval != ERROR_OK)
 245                 return retval;
 246
 247         /* read R0 first (it's used for scratch), then CPSR */
 248         r = arm->core_cache->reg_list + 0;
 249         if (!r->valid) {
 250                 retval = dpm_read_reg(dpm, r, 0);
 251                 if (retval != ERROR_OK)
 252                         goto fail;
 253         }
 254         r->dirty = true;
 255
 256         retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
 257         if (retval != ERROR_OK)
 258                 goto fail;
 259
 260         /* update core mode and state, plus shadow mapping for R8..R14 */
 261         arm_set_cpsr(arm, cpsr);
 262
 263         /* REVISIT we can probably avoid reading R1..R14, saving time... */
 264         for (unsigned i = 1; i < 16; i++) {
 265                 r = arm_reg_current(arm, i);
 266                 if (r->valid)
 267                         continue;
 268
 269                 retval = dpm_read_reg(dpm, r, i);
 270                 if (retval != ERROR_OK)
 271                         goto fail;
 272         }
 273
 274         /* NOTE: SPSR ignored (if it's even relevant). */
 275
 276         /* REVISIT the debugger can trigger various exceptions.  See the
 277          * ARMv7A architecture spec, section C5.7, for more info about
 278          * what defenses are needed; v6 debug has the most issues.
 279          */
 280
 281 fail:
 282         /* (void) */ dpm->finish(dpm);
 283         return retval;
 284 }
 285
 286 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
 287  * unless they're removed, or need updating because of single-stepping
 288  * or running debugger code.
 289  */
 290 static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
 291                 struct dpm_bpwp *xp, int *set_p)
 292 {
 293         int retval = ERROR_OK;
 294         bool disable;
 295
 296         if (!set_p) {
 297                 if (!xp->dirty)
 298                         goto done;
 299                 xp->dirty = false;
 300                 /* removed or startup; we must disable it */
 301                 disable = true;
 302         } else if (bpwp) {
 303                 if (!xp->dirty)
 304                         goto done;
 305                 /* disabled, but we must set it */
 306                 xp->dirty = disable = false;
 307                 *set_p = true;
 308         } else {
 309                 if (!*set_p)
 310                         goto done;
 311                 /* set, but we must temporarily disable it */
 312                 xp->dirty = disable = true;
 313                 *set_p = false;
 314         }
 315
 316         if (disable)
 317                 retval = dpm->bpwp_disable(dpm, xp->number);
 318         else
 319                 retval = dpm->bpwp_enable(dpm, xp->number,
 320                                 xp->address, xp->control);
 321
 322         if (retval != ERROR_OK)
 323                 LOG_ERROR("%s: can't %s HW bp/wp %d",
 324                                 disable ? "disable" : "enable",
 325                                 target_name(dpm->arm->target),
 326                                 xp->number);
 327 done:
 328         return retval;
 329 }
 330
 331 /**
 332  * Writes all modified core registers for all processor modes.  In normal
 333  * operation this is called on exit from halting debug state.
 334  *
 335  * @param dpm: represents the processor
 336  * @param bpwp: true ensures breakpoints and watchpoints are set,
 337  *      false ensures they are cleared
 338  */
 339 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 340 {
 341         struct arm *arm = dpm->arm;
 342         struct reg_cache *cache = arm->core_cache;
 343         int retval;
 344         bool did_write;
 345
 346         retval = dpm->prepare(dpm);
 347         if (retval != ERROR_OK)
 348                 goto done;
 349
 350         /* If we're managing hardware breakpoints for this core, enable
 351          * or disable them as requested.
 352          *
 353          * REVISIT We don't yet manage them for ANY cores.  Eventually
 354          * we should be able to assume we handle them; but until then,
 355          * cope with the hand-crafted breakpoint code.
 356          */
 357         if (0) {
 358                 for (unsigned i = 0; i < dpm->nbp; i++) {
 359                         struct dpm_bp *dbp = dpm->dbp + i;
 360                         struct breakpoint *bp = dbp->bp;
 361
 362                         retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
 363                                         bp ? &bp->set : NULL);
 364                 }
 365         }
 366
 367         /* enable/disable watchpoints */
 368         for (unsigned i = 0; i < dpm->nwp; i++) {
 369                 struct dpm_wp *dwp = dpm->dwp + i;
 370                 struct watchpoint *wp = dwp->wp;
 371
 372                 retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
 373                                 wp ? &wp->set : NULL);
 374         }
 375
 376         /* NOTE:  writes to breakpoint and watchpoint registers might
 377          * be queued, and need (efficient/batched) flushing later.
 378          */
 379
 380         /* Scan the registers until we find one that's both dirty and
 381          * eligible for flushing.  Flush that and everything else that
 382          * shares the same core mode setting.  Typically this won't
 383          * actually find anything to do...
 384          */
 385         do {
 386                 enum arm_mode mode = ARM_MODE_ANY;
 387
 388                 did_write = false;
 389
 390                 /* check everything except our scratch register R0 */
 391                 for (unsigned i = 1; i < cache->num_regs; i++) {
 392                         struct arm_reg *r;
 393                         unsigned regnum;
 394
 395                         /* also skip PC, CPSR, and non-dirty */
 396                         if (i == 15)
 397                                 continue;
 398                         if (arm->cpsr == cache->reg_list + i)
 399                                 continue;
 400                         if (!cache->reg_list[i].dirty)
 401                                 continue;
 402
 403                         r = cache->reg_list[i].arch_info;
 404                         regnum = r->num;
 405
 406                         /* may need to pick and set a mode */
 407                         if (!did_write) {
 408                                 enum arm_mode tmode;
 409
 410                                 did_write = true;
 411                                 mode = tmode = r->mode;
 412
 413                                 /* cope with special cases */
 414                                 switch (regnum) {
 415                                 case 8 ... 12:
 416                                         /* r8..r12 "anything but FIQ" case;
 417                                          * we "know" core mode is accurate
 418                                          * since we haven't changed it yet
 419                                          */
 420                                         if (arm->core_mode == ARM_MODE_FIQ
 421                                                         && ARM_MODE_ANY
 422                                                                 != mode)
 423                                                 tmode = ARM_MODE_USR;
 424                                         break;
 425                                 case 16:
 426                                         /* SPSR */
 427                                         regnum++;
 428                                         break;
 429                                 }
 430
 431                                 /* REVISIT error checks */
 432                                 if (tmode != ARM_MODE_ANY)
 433                                         retval = dpm_modeswitch(dpm, tmode);
 434                         }
 435                         if (r->mode != mode)
 436                                 continue;
 437
 438                         retval = dpm_write_reg(dpm,
 439                                         &cache->reg_list[i],
 440                                         regnum);
 441
 442                 }
 443
 444         } while (did_write);
 445
 446         /* Restore original CPSR ... assuming either that we changed it,
 447          * or it's dirty.  Must write PC to ensure the return address is
 448          * defined, and must not write it before CPSR.
 449          */
 450         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 451         arm->cpsr->dirty = false;
 452
 453         retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
 454         cache->reg_list[15].dirty = false;
 455
 456         /* flush R0 -- it's *very* dirty by now */
 457         retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
 458         cache->reg_list[0].dirty = false;
 459
 460         /* (void) */ dpm->finish(dpm);
 461 done:
 462         return retval;
 463 }
 464
 465 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
 466  * specified register ... works around flakiness from ARM core calls.
 467  * Caller already filtered out SPSR access; mode is never MODE_SYS
 468  * or MODE_ANY.
 469  */
 470 static enum arm_mode dpm_mapmode(struct arm *arm,
 471                 unsigned num, enum arm_mode mode)
 472 {
 473         enum arm_mode amode = arm->core_mode;
 474
 475         /* don't switch if the mode is already correct */
 476         if (amode == ARM_MODE_SYS)
 477                  amode = ARM_MODE_USR;
 478         if (mode == amode)
 479                 return ARM_MODE_ANY;
 480
 481         switch (num) {
 482         /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
 483         case 0 ... 7:
 484         case 15:
 485         case 16:
 486                 break;
 487         /* r8..r12 aren't shadowed for anything except FIQ */
 488         case 8 ... 12:
 489                 if (mode == ARM_MODE_FIQ)
 490                         return mode;
 491                 break;
 492         /* r13/sp, and r14/lr are always shadowed */
 493         case 13:
 494         case 14:
 495                 return mode;
 496         default:
 497                 LOG_WARNING("invalid register #%u", num);
 498                 break;
 499         }
 500         return ARM_MODE_ANY;
 501 }
 502
 503
 504 /*
 505  * Standard ARM register accessors ... there are three methods
 506  * in "struct arm", to support individual read/write and bulk read
 507  * of registers.
 508  */
 509
 510 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
 511                 int regnum, enum arm_mode mode)
 512 {
 513         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 514         int retval;
 515
 516         if (regnum < 0 || regnum > 16)
 517                 return ERROR_INVALID_ARGUMENTS;
 518
 519         if (regnum == 16) {
 520                 if (mode != ARM_MODE_ANY)
 521                         regnum = 17;
 522         } else
 523                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 524
 525         /* REVISIT what happens if we try to read SPSR in a core mode
 526          * which has no such register?
 527          */
 528
 529         retval = dpm->prepare(dpm);
 530         if (retval != ERROR_OK)
 531                 return retval;
 532
 533         if (mode != ARM_MODE_ANY) {
 534                 retval = dpm_modeswitch(dpm, mode);
 535                 if (retval != ERROR_OK)
 536                         goto fail;
 537         }
 538
 539         retval = dpm_read_reg(dpm, r, regnum);
 540         /* always clean up, regardless of error */
 541
 542         if (mode != ARM_MODE_ANY)
 543                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 544
 545 fail:
 546         /* (void) */ dpm->finish(dpm);
 547         return retval;
 548 }
 549
 550 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
 551                 int regnum, enum arm_mode mode, uint32_t value)
 552 {
 553         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 554         int retval;
 555
 556
 557         if (regnum < 0 || regnum > 16)
 558                 return ERROR_INVALID_ARGUMENTS;
 559
 560         if (regnum == 16) {
 561                 if (mode != ARM_MODE_ANY)
 562                         regnum = 17;
 563         } else
 564                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 565
 566         /* REVISIT what happens if we try to write SPSR in a core mode
 567          * which has no such register?
 568          */
 569
 570         retval = dpm->prepare(dpm);
 571         if (retval != ERROR_OK)
 572                 return retval;
 573
 574         if (mode != ARM_MODE_ANY) {
 575                 retval = dpm_modeswitch(dpm, mode);
 576                 if (retval != ERROR_OK)
 577                         goto fail;
 578         }
 579
 580         retval = dpm_write_reg(dpm, r, regnum);
 581         /* always clean up, regardless of error */
 582
 583         if (mode != ARM_MODE_ANY)
 584                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 585
 586 fail:
 587         /* (void) */ dpm->finish(dpm);
 588         return retval;
 589 }
 590
 591 static int arm_dpm_full_context(struct target *target)
 592 {
 593         struct arm *arm = target_to_arm(target);
 594         struct arm_dpm *dpm = arm->dpm;
 595         struct reg_cache *cache = arm->core_cache;
 596         int retval;
 597         bool did_read;
 598
 599         retval = dpm->prepare(dpm);
 600         if (retval != ERROR_OK)
 601                 goto done;
 602
 603         do {
 604                 enum arm_mode mode = ARM_MODE_ANY;
 605
 606                 did_read = false;
 607
 608                 /* We "know" arm_dpm_read_current_registers() was called so
 609                  * the unmapped registers (R0..R7, PC, AND CPSR) and some
 610                  * view of R8..R14 are current.  We also "know" oddities of
 611                  * register mapping: special cases for R8..R12 and SPSR.
 612                  *
 613                  * Pick some mode with unread registers and read them all.
 614                  * Repeat until done.
 615                  */
 616                 for (unsigned i = 0; i < cache->num_regs; i++) {
 617                         struct arm_reg *r;
 618
 619                         if (cache->reg_list[i].valid)
 620                                 continue;
 621                         r = cache->reg_list[i].arch_info;
 622
 623                         /* may need to pick a mode and set CPSR */
 624                         if (!did_read) {
 625                                 did_read = true;
 626                                 mode = r->mode;
 627
 628                                 /* For R8..R12 when we've entered debug
 629                                  * state in FIQ mode... patch mode.
 630                                  */
 631                                 if (mode == ARM_MODE_ANY)
 632                                         mode = ARM_MODE_USR;
 633
 634                                 /* REVISIT error checks */
 635                                 retval = dpm_modeswitch(dpm, mode);
 636                         }
 637                         if (r->mode != mode)
 638                                 continue;
 639
 640                         /* CPSR was read, so "R16" must mean SPSR */
 641                         retval = dpm_read_reg(dpm,
 642                                         &cache->reg_list[i],
 643                                         (r->num == 16) ? 17 : r->num);
 644
 645                 }
 646
 647         } while (did_read);
 648
 649         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 650         /* (void) */ dpm->finish(dpm);
 651 done:
 652         return retval;
 653 }
 654
 655
 656 /*----------------------------------------------------------------------*/
 657
 658 /*
 659  * Breakpoint and Watchpoint support.
 660  *
 661  * Hardware {break,watch}points are usually left active, to minimize
 662  * debug entry/exit costs.  When they are set or cleared, it's done in
 663  * batches.  Also, DPM-conformant hardware can update debug registers
 664  * regardless of whether the CPU is running or halted ... though that
 665  * fact isn't currently leveraged.
 666  */
 667
 668 static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
 669                 struct watchpoint *wp)
 670 {
 671         uint32_t addr = wp->address;
 672         uint32_t control;
 673
 674         /* this hardware doesn't support data value matching or masking */
 675         if (wp->value || wp->mask != ~(uint32_t)0) {
 676                 LOG_DEBUG("watchpoint values and masking not supported");
 677                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 678         }
 679
 680         control = (1 << 0)      /* enable */
 681                 | (3 << 1);     /* both user and privileged access */
 682
 683         switch (wp->rw) {
 684         case WPT_READ:
 685                 control |= 1 << 3;
 686                 break;
 687         case WPT_WRITE:
 688                 control |= 2 << 3;
 689                 break;
 690         case WPT_ACCESS:
 691                 control |= 3 << 3;
 692                 break;
 693         }
 694
 695         /* Match 1, 2, or all 4 byte addresses in this word.
 696          *
 697          * FIXME:  v7 hardware allows lengths up to 2 GB, and has eight
 698          * byte address select bits.  Support larger wp->length, if addr
 699          * is suitably aligned.
 700          */
 701         switch (wp->length) {
 702         case 1:
 703                 control |= (1 << (addr & 3)) << 5;
 704                 addr &= ~3;
 705                 break;
 706         case 2:
 707                 /* require 2-byte alignment */
 708                 if (!(addr & 1)) {
 709                         control |= (3 << (addr & 2)) << 5;
 710                         break;
 711                 }
 712                 /* FALL THROUGH */
 713         case 4:
 714                 /* require 4-byte alignment */
 715                 if (!(addr & 3)) {
 716                         control |= 0xf << 5;
 717                         break;
 718                 }
 719                 /* FALL THROUGH */
 720         default:
 721                 LOG_DEBUG("bad watchpoint length or alignment");
 722                 return ERROR_INVALID_ARGUMENTS;
 723         }
 724
 725         /* other control bits:
 726          * bits 9:12 == 0 ... only checking up to four byte addresses (v7 only)
 727          * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
 728          * bit 20 == 0 ... not linked to a context ID
 729          * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
 730          */
 731
 732         dpm->dwp[index].wp = wp;
 733         dpm->dwp[index].bpwp.address = addr & ~3;
 734         dpm->dwp[index].bpwp.control = control;
 735         dpm->dwp[index].bpwp.dirty = true;
 736
 737         /* hardware is updated in write_dirty_registers() */
 738         return ERROR_OK;
 739 }
 740
 741
 742 static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
 743 {
 744         struct arm *arm = target_to_arm(target);
 745         struct arm_dpm *dpm = arm->dpm;
 746         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 747
 748         if (dpm->bpwp_enable) {
 749                 for (unsigned i = 0; i < dpm->nwp; i++) {
 750                         if (!dpm->dwp[i].wp) {
 751                                 retval = dpm_watchpoint_setup(dpm, i, wp);
 752                                 break;
 753                         }
 754                 }
 755         }
 756
 757         return retval;
 758 }
 759
 760 static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
 761 {
 762         struct arm *arm = target_to_arm(target);
 763         struct arm_dpm *dpm = arm->dpm;
 764         int retval = ERROR_INVALID_ARGUMENTS;
 765
 766         for (unsigned i = 0; i < dpm->nwp; i++) {
 767                 if (dpm->dwp[i].wp == wp) {
 768                         dpm->dwp[i].wp = NULL;
 769                         dpm->dwp[i].bpwp.dirty = true;
 770
 771                         /* hardware is updated in write_dirty_registers() */
 772                         retval = ERROR_OK;
 773                         break;
 774                 }
 775         }
 776
 777         return retval;
 778 }
 779
 780 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
 781 {
 782         switch (dpm->arm->core_state) {
 783         case ARM_STATE_ARM:
 784                 addr -= 8;
 785                 break;
 786         case ARM_STATE_THUMB:
 787         case ARM_STATE_THUMB_EE:
 788                 addr -= 4;
 789                 break;
 790         case ARM_STATE_JAZELLE:
 791                 /* ?? */
 792                 break;
 793         }
 794         dpm->wp_pc = addr;
 795 }
 796
 797 /*----------------------------------------------------------------------*/
 798
 799 /*
 800  * Other debug and support utilities
 801  */
 802
 803 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
 804 {
 805         struct target *target = dpm->arm->target;
 806
 807         dpm->dscr = dscr;
 808
 809         /* Examine debug reason */
 810         switch (DSCR_ENTRY(dscr)) {
 811         case 6:         /* Data abort (v6 only) */
 812         case 7:         /* Prefetch abort (v6 only) */
 813                 /* FALL THROUGH -- assume a v6 core in abort mode */
 814         case 0:         /* HALT request from debugger */
 815         case 4:         /* EDBGRQ */
 816                 target->debug_reason = DBG_REASON_DBGRQ;
 817                 break;
 818         case 1:         /* HW breakpoint */
 819         case 3:         /* SW BKPT */
 820         case 5:         /* vector catch */
 821                 target->debug_reason = DBG_REASON_BREAKPOINT;
 822                 break;
 823         case 2:         /* asynch watchpoint */
 824         case 10:        /* precise watchpoint */
 825                 target->debug_reason = DBG_REASON_WATCHPOINT;
 826                 break;
 827         default:
 828                 target->debug_reason = DBG_REASON_UNDEFINED;
 829                 break;
 830         }
 831 }
 832
 833 /*----------------------------------------------------------------------*/
 834
 835 /*
 836  * Setup and management support.
 837  */
 838
 839 /**
 840  * Hooks up this DPM to its associated target; call only once.
 841  * Initially this only covers the register cache.
 842  *
 843  * Oh, and watchpoints.  Yeah.
 844  */
 845 int arm_dpm_setup(struct arm_dpm *dpm)
 846 {
 847         struct arm *arm = dpm->arm;
 848         struct target *target = arm->target;
 849         struct reg_cache *cache;
 850
 851         arm->dpm = dpm;
 852
 853         /* register access setup */
 854         arm->full_context = arm_dpm_full_context;
 855         arm->read_core_reg = arm_dpm_read_core_reg;
 856         arm->write_core_reg = arm_dpm_write_core_reg;
 857
 858         cache = arm_build_reg_cache(target, arm);
 859         if (!cache)
 860                 return ERROR_FAIL;
 861
 862         *register_get_last_cache_p(&target->reg_cache) = cache;
 863
 864         /* coprocessor access setup */
 865         arm->mrc = dpm_mrc;
 866         arm->mcr = dpm_mcr;
 867
 868         /* breakpoint and watchpoint setup */
 869         target->type->add_watchpoint = dpm_add_watchpoint;
 870         target->type->remove_watchpoint = dpm_remove_watchpoint;
 871
 872         /* FIXME add breakpoint support */
 873         /* FIXME add vector catch support */
 874
 875         dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
 876         dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
 877
 878         dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
 879         dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
 880
 881         if (!dpm->dbp || !dpm->dwp) {
 882                 free(dpm->dbp);
 883                 free(dpm->dwp);
 884                 return ERROR_FAIL;
 885         }
 886
 887         LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
 888                         target_name(target), dpm->nbp, dpm->nwp);
 889
 890         /* REVISIT ... and some of those breakpoints could match
 891          * execution context IDs...
 892          */
 893
 894         return ERROR_OK;
 895 }
 896
 897 /**
 898  * Reinitializes DPM state at the beginning of a new debug session
 899  * or after a reset which may have affected the debug module.
 900  */
 901 int arm_dpm_initialize(struct arm_dpm *dpm)
 902 {
 903         /* Disable all breakpoints and watchpoints at startup. */
 904         if (dpm->bpwp_disable) {
 905                 unsigned i;
 906
 907                 for (i = 0; i < dpm->nbp; i++) {
 908                         dpm->dbp[i].bpwp.number = i;
 909                         (void) dpm->bpwp_disable(dpm, i);
 910                 }
 911                 for (i = 0; i < dpm->nwp; i++) {
 912                         dpm->dwp[i].bpwp.number = 16 + i;
 913                         (void) dpm->bpwp_disable(dpm, 16 + i);
 914                 }
 915         } else
 916                 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
 917                         target_name(dpm->arm->target));
 918
 919         return ERROR_OK;
 920 }