?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
debug: use assert's when approperiate
[openocd/cortex.git] / src / target / xscale.c
blob44358bc3f3bb246a51cfa7a591fd63520f93c8af
1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "breakpoints.h"
31 #include "xscale.h"
32 #include "target_type.h"
33 #include "arm_jtag.h"
34 #include "arm_simulator.h"
35 #include "arm_disassembler.h"
36 #include <helper/time_support.h>
37 #include "register.h"
38 #include "image.h"
39 #include "arm_opcodes.h"
40 #include "armv4_5.h"
41
42
43 /*
44 * Important XScale documents available as of October 2009 include:
45 *
46 * Intel XScale® Core Developer’s Manual, January 2004
47 * Order Number: 273473-002
48 * This has a chapter detailing debug facilities, and punts some
49 * details to chip-specific microarchitecture documents.
50 *
51 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
52 * Document Number: 273539-005
53 * Less detailed than the developer's manual, but summarizes those
54 * missing details (for most XScales) and gives LOTS of notes about
55 * debugger/handler interaction issues. Presents a simpler reset
56 * and load-handler sequence than the arch doc. (Note, OpenOCD
57 * doesn't currently support "Hot-Debug" as defined there.)
58 *
59 * Chip-specific microarchitecture documents may also be useful.
60 */
61
62
63 /* forward declarations */
64 static int xscale_resume(struct target *, int current,
65 uint32_t address, int handle_breakpoints, int debug_execution);
66 static int xscale_debug_entry(struct target *);
67 static int xscale_restore_banked(struct target *);
68 static int xscale_get_reg(struct reg *reg);
69 static int xscale_set_reg(struct reg *reg, uint8_t *buf);
70 static int xscale_set_breakpoint(struct target *, struct breakpoint *);
71 static int xscale_set_watchpoint(struct target *, struct watchpoint *);
72 static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
73 static int xscale_read_trace(struct target *);
74
75
76 /* This XScale "debug handler" is loaded into the processor's
77 * mini-ICache, which is 2K of code writable only via JTAG.
78 *
79 * FIXME the OpenOCD "bin2char" utility currently doesn't handle
80 * binary files cleanly. It's string oriented, and terminates them
81 * with a NUL character. Better would be to generate the constants
82 * and let other code decide names, scoping, and other housekeeping.
83 */
84 static /* unsigned const char xscale_debug_handler[] = ... */
85 #include "xscale_debug.h"
86
87 static char *const xscale_reg_list[] =
88 {
89 "XSCALE_MAINID", /* 0 */
90 "XSCALE_CACHETYPE",
91 "XSCALE_CTRL",
92 "XSCALE_AUXCTRL",
93 "XSCALE_TTB",
94 "XSCALE_DAC",
95 "XSCALE_FSR",
96 "XSCALE_FAR",
97 "XSCALE_PID",
98 "XSCALE_CPACCESS",
99 "XSCALE_IBCR0", /* 10 */
100 "XSCALE_IBCR1",
101 "XSCALE_DBR0",
102 "XSCALE_DBR1",
103 "XSCALE_DBCON",
104 "XSCALE_TBREG",
105 "XSCALE_CHKPT0",
106 "XSCALE_CHKPT1",
107 "XSCALE_DCSR",
108 "XSCALE_TX",
109 "XSCALE_RX", /* 20 */
110 "XSCALE_TXRXCTRL",
111 };
112
113 static const struct xscale_reg xscale_reg_arch_info[] =
114 {
115 {XSCALE_MAINID, NULL},
116 {XSCALE_CACHETYPE, NULL},
117 {XSCALE_CTRL, NULL},
118 {XSCALE_AUXCTRL, NULL},
119 {XSCALE_TTB, NULL},
120 {XSCALE_DAC, NULL},
121 {XSCALE_FSR, NULL},
122 {XSCALE_FAR, NULL},
123 {XSCALE_PID, NULL},
124 {XSCALE_CPACCESS, NULL},
125 {XSCALE_IBCR0, NULL},
126 {XSCALE_IBCR1, NULL},
127 {XSCALE_DBR0, NULL},
128 {XSCALE_DBR1, NULL},
129 {XSCALE_DBCON, NULL},
130 {XSCALE_TBREG, NULL},
131 {XSCALE_CHKPT0, NULL},
132 {XSCALE_CHKPT1, NULL},
133 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
134 {-1, NULL}, /* TX accessed via JTAG */
135 {-1, NULL}, /* RX accessed via JTAG */
136 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
137 };
138
139 /* convenience wrapper to access XScale specific registers */
140 static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
141 {
142 uint8_t buf[4];
143
144 buf_set_u32(buf, 0, 32, value);
145
146 return xscale_set_reg(reg, buf);
147 }
148
149 static const char xscale_not[] = "target is not an XScale";
150
151 static int xscale_verify_pointer(struct command_context *cmd_ctx,
152 struct xscale_common *xscale)
153 {
154 if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
155 command_print(cmd_ctx, xscale_not);
156 return ERROR_TARGET_INVALID;
157 }
158 return ERROR_OK;
159 }
160
161 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
162 {
163 assert (tap != NULL);
164
165 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
166 {
167 struct scan_field field;
168 uint8_t scratch[4];
169
170 memset(&field, 0, sizeof field);
171 field.num_bits = tap->ir_length;
172 field.out_value = scratch;
173 buf_set_u32(scratch, 0, field.num_bits, new_instr);
174
175 jtag_add_ir_scan(tap, &field, end_state);
176 }
177
178 return ERROR_OK;
179 }
180
181 static int xscale_read_dcsr(struct target *target)
182 {
183 struct xscale_common *xscale = target_to_xscale(target);
184 int retval;
185 struct scan_field fields[3];
186 uint8_t field0 = 0x0;
187 uint8_t field0_check_value = 0x2;
188 uint8_t field0_check_mask = 0x7;
189 uint8_t field2 = 0x0;
190 uint8_t field2_check_value = 0x0;
191 uint8_t field2_check_mask = 0x1;
192
193 xscale_jtag_set_instr(target->tap,
194 XSCALE_SELDCSR << xscale->xscale_variant,
195 TAP_DRPAUSE);
196
197 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
198 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
199
200 memset(&fields, 0, sizeof fields);
201
202 fields[0].num_bits = 3;
203 fields[0].out_value = &field0;
204 uint8_t tmp;
205 fields[0].in_value = &tmp;
206
207 fields[1].num_bits = 32;
208 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
209
210 fields[2].num_bits = 1;
211 fields[2].out_value = &field2;
212 uint8_t tmp2;
213 fields[2].in_value = &tmp2;
214
215 jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
216
217 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
218 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
219
220 if ((retval = jtag_execute_queue()) != ERROR_OK)
221 {
222 LOG_ERROR("JTAG error while reading DCSR");
223 return retval;
224 }
225
226 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
227 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
228
229 /* write the register with the value we just read
230 * on this second pass, only the first bit of field0 is guaranteed to be 0)
231 */
232 field0_check_mask = 0x1;
233 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
234 fields[1].in_value = NULL;
235
236 jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
237
238 /* DANGER!!! this must be here. It will make sure that the arguments
239 * to jtag_set_check_value() does not go out of scope! */
240 return jtag_execute_queue();
241 }
242
243
244 static void xscale_getbuf(jtag_callback_data_t arg)
245 {
246 uint8_t *in = (uint8_t *)arg;
247 *((uint32_t *)in) = buf_get_u32(in, 0, 32);
248 }
249
250 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
251 {
252 if (num_words == 0)
253 return ERROR_INVALID_ARGUMENTS;
254
255 struct xscale_common *xscale = target_to_xscale(target);
256 int retval = ERROR_OK;
257 tap_state_t path[3];
258 struct scan_field fields[3];
259 uint8_t *field0 = malloc(num_words * 1);
260 uint8_t field0_check_value = 0x2;
261 uint8_t field0_check_mask = 0x6;
262 uint32_t *field1 = malloc(num_words * 4);
263 uint8_t field2_check_value = 0x0;
264 uint8_t field2_check_mask = 0x1;
265 int words_done = 0;
266 int words_scheduled = 0;
267 int i;
268
269 path[0] = TAP_DRSELECT;
270 path[1] = TAP_DRCAPTURE;
271 path[2] = TAP_DRSHIFT;
272
273 memset(&fields, 0, sizeof fields);
274
275 fields[0].num_bits = 3;
276 fields[0].check_value = &field0_check_value;
277 fields[0].check_mask = &field0_check_mask;
278
279 fields[1].num_bits = 32;
280
281 fields[2].num_bits = 1;
282 fields[2].check_value = &field2_check_value;
283 fields[2].check_mask = &field2_check_mask;
284
285 xscale_jtag_set_instr(target->tap,
286 XSCALE_DBGTX << xscale->xscale_variant,
287 TAP_IDLE);
288 jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
289
290 /* repeat until all words have been collected */
291 int attempts = 0;
292 while (words_done < num_words)
293 {
294 /* schedule reads */
295 words_scheduled = 0;
296 for (i = words_done; i < num_words; i++)
297 {
298 fields[0].in_value = &field0[i];
299
300 jtag_add_pathmove(3, path);
301
302 fields[1].in_value = (uint8_t *)(field1 + i);
303
304 jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
305
306 jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
307
308 words_scheduled++;
309 }
310
311 if ((retval = jtag_execute_queue()) != ERROR_OK)
312 {
313 LOG_ERROR("JTAG error while receiving data from debug handler");
314 break;
315 }
316
317 /* examine results */
318 for (i = words_done; i < num_words; i++)
319 {
320 if (!(field0[0] & 1))
321 {
322 /* move backwards if necessary */
323 int j;
324 for (j = i; j < num_words - 1; j++)
325 {
326 field0[j] = field0[j + 1];
327 field1[j] = field1[j + 1];
328 }
329 words_scheduled--;
330 }
331 }
332 if (words_scheduled == 0)
333 {
334 if (attempts++==1000)
335 {
336 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
337 retval = ERROR_TARGET_TIMEOUT;
338 break;
339 }
340 }
341
342 words_done += words_scheduled;
343 }
344
345 for (i = 0; i < num_words; i++)
346 *(buffer++) = buf_get_u32((uint8_t*)&field1[i], 0, 32);
347
348 free(field1);
349
350 return retval;
351 }
352
353 static int xscale_read_tx(struct target *target, int consume)
354 {
355 struct xscale_common *xscale = target_to_xscale(target);
356 tap_state_t path[3];
357 tap_state_t noconsume_path[6];
358 int retval;
359 struct timeval timeout, now;
360 struct scan_field fields[3];
361 uint8_t field0_in = 0x0;
362 uint8_t field0_check_value = 0x2;
363 uint8_t field0_check_mask = 0x6;
364 uint8_t field2_check_value = 0x0;
365 uint8_t field2_check_mask = 0x1;
366
367 xscale_jtag_set_instr(target->tap,
368 XSCALE_DBGTX << xscale->xscale_variant,
369 TAP_IDLE);
370
371 path[0] = TAP_DRSELECT;
372 path[1] = TAP_DRCAPTURE;
373 path[2] = TAP_DRSHIFT;
374
375 noconsume_path[0] = TAP_DRSELECT;
376 noconsume_path[1] = TAP_DRCAPTURE;
377 noconsume_path[2] = TAP_DREXIT1;
378 noconsume_path[3] = TAP_DRPAUSE;
379 noconsume_path[4] = TAP_DREXIT2;
380 noconsume_path[5] = TAP_DRSHIFT;
381
382 memset(&fields, 0, sizeof fields);
383
384 fields[0].num_bits = 3;
385 fields[0].in_value = &field0_in;
386
387 fields[1].num_bits = 32;
388 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
389
390 fields[2].num_bits = 1;
391 uint8_t tmp;
392 fields[2].in_value = &tmp;
393
394 gettimeofday(&timeout, NULL);
395 timeval_add_time(&timeout, 1, 0);
396
397 for (;;)
398 {
399 /* if we want to consume the register content (i.e. clear TX_READY),
400 * we have to go straight from Capture-DR to Shift-DR
401 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
402 */
403 if (consume)
404 jtag_add_pathmove(3, path);
405 else
406 {
407 jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
408 }
409
410 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
411
412 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
413 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
414
415 if ((retval = jtag_execute_queue()) != ERROR_OK)
416 {
417 LOG_ERROR("JTAG error while reading TX");
418 return ERROR_TARGET_TIMEOUT;
419 }
420
421 gettimeofday(&now, NULL);
422 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
423 {
424 LOG_ERROR("time out reading TX register");
425 return ERROR_TARGET_TIMEOUT;
426 }
427 if (!((!(field0_in & 1)) && consume))
428 {
429 goto done;
430 }
431 if (debug_level >= 3)
432 {
433 LOG_DEBUG("waiting 100ms");
434 alive_sleep(100); /* avoid flooding the logs */
435 } else
436 {
437 keep_alive();
438 }
439 }
440 done:
441
442 if (!(field0_in & 1))
443 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
444
445 return ERROR_OK;
446 }
447
448 static int xscale_write_rx(struct target *target)
449 {
450 struct xscale_common *xscale = target_to_xscale(target);
451 int retval;
452 struct timeval timeout, now;
453 struct scan_field fields[3];
454 uint8_t field0_out = 0x0;
455 uint8_t field0_in = 0x0;
456 uint8_t field0_check_value = 0x2;
457 uint8_t field0_check_mask = 0x6;
458 uint8_t field2 = 0x0;
459 uint8_t field2_check_value = 0x0;
460 uint8_t field2_check_mask = 0x1;
461
462 xscale_jtag_set_instr(target->tap,
463 XSCALE_DBGRX << xscale->xscale_variant,
464 TAP_IDLE);
465
466 memset(&fields, 0, sizeof fields);
467
468 fields[0].num_bits = 3;
469 fields[0].out_value = &field0_out;
470 fields[0].in_value = &field0_in;
471
472 fields[1].num_bits = 32;
473 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
474
475 fields[2].num_bits = 1;
476 fields[2].out_value = &field2;
477 uint8_t tmp;
478 fields[2].in_value = &tmp;
479
480 gettimeofday(&timeout, NULL);
481 timeval_add_time(&timeout, 1, 0);
482
483 /* poll until rx_read is low */
484 LOG_DEBUG("polling RX");
485 for (;;)
486 {
487 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
488
489 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
490 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
491
492 if ((retval = jtag_execute_queue()) != ERROR_OK)
493 {
494 LOG_ERROR("JTAG error while writing RX");
495 return retval;
496 }
497
498 gettimeofday(&now, NULL);
499 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
500 {
501 LOG_ERROR("time out writing RX register");
502 return ERROR_TARGET_TIMEOUT;
503 }
504 if (!(field0_in & 1))
505 goto done;
506 if (debug_level >= 3)
507 {
508 LOG_DEBUG("waiting 100ms");
509 alive_sleep(100); /* avoid flooding the logs */
510 } else
511 {
512 keep_alive();
513 }
514 }
515 done:
516
517 /* set rx_valid */
518 field2 = 0x1;
519 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
520
521 if ((retval = jtag_execute_queue()) != ERROR_OK)
522 {
523 LOG_ERROR("JTAG error while writing RX");
524 return retval;
525 }
526
527 return ERROR_OK;
528 }
529
530 /* send count elements of size byte to the debug handler */
531 static int xscale_send(struct target *target, uint8_t *buffer, int count, int size)
532 {
533 struct xscale_common *xscale = target_to_xscale(target);
534 uint32_t t[3];
535 int bits[3];
536 int retval;
537 int done_count = 0;
538
539 xscale_jtag_set_instr(target->tap,
540 XSCALE_DBGRX << xscale->xscale_variant,
541 TAP_IDLE);
542
543 bits[0]=3;
544 t[0]=0;
545 bits[1]=32;
546 t[2]=1;
547 bits[2]=1;
548 int endianness = target->endianness;
549 while (done_count++ < count)
550 {
551 switch (size)
552 {
553 case 4:
554 if (endianness == TARGET_LITTLE_ENDIAN)
555 {
556 t[1]=le_to_h_u32(buffer);
557 } else
558 {
559 t[1]=be_to_h_u32(buffer);
560 }
561 break;
562 case 2:
563 if (endianness == TARGET_LITTLE_ENDIAN)
564 {
565 t[1]=le_to_h_u16(buffer);
566 } else
567 {
568 t[1]=be_to_h_u16(buffer);
569 }
570 break;
571 case 1:
572 t[1]=buffer[0];
573 break;
574 default:
575 LOG_ERROR("BUG: size neither 4, 2 nor 1");
576 return ERROR_INVALID_ARGUMENTS;
577 }
578 jtag_add_dr_out(target->tap,
579 3,
580 bits,
581 t,
582 TAP_IDLE);
583 buffer += size;
584 }
585
586 if ((retval = jtag_execute_queue()) != ERROR_OK)
587 {
588 LOG_ERROR("JTAG error while sending data to debug handler");
589 return retval;
590 }
591
592 return ERROR_OK;
593 }
594
595 static int xscale_send_u32(struct target *target, uint32_t value)
596 {
597 struct xscale_common *xscale = target_to_xscale(target);
598
599 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
600 return xscale_write_rx(target);
601 }
602
603 static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
604 {
605 struct xscale_common *xscale = target_to_xscale(target);
606 int retval;
607 struct scan_field fields[3];
608 uint8_t field0 = 0x0;
609 uint8_t field0_check_value = 0x2;
610 uint8_t field0_check_mask = 0x7;
611 uint8_t field2 = 0x0;
612 uint8_t field2_check_value = 0x0;
613 uint8_t field2_check_mask = 0x1;
614
615 if (hold_rst != -1)
616 xscale->hold_rst = hold_rst;
617
618 if (ext_dbg_brk != -1)
619 xscale->external_debug_break = ext_dbg_brk;
620
621 xscale_jtag_set_instr(target->tap,
622 XSCALE_SELDCSR << xscale->xscale_variant,
623 TAP_IDLE);
624
625 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
626 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
627
628 memset(&fields, 0, sizeof fields);
629
630 fields[0].num_bits = 3;
631 fields[0].out_value = &field0;
632 uint8_t tmp;
633 fields[0].in_value = &tmp;
634
635 fields[1].num_bits = 32;
636 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
637
638 fields[2].num_bits = 1;
639 fields[2].out_value = &field2;
640 uint8_t tmp2;
641 fields[2].in_value = &tmp2;
642
643 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
644
645 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
646 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
647
648 if ((retval = jtag_execute_queue()) != ERROR_OK)
649 {
650 LOG_ERROR("JTAG error while writing DCSR");
651 return retval;
652 }
653
654 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
655 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
656
657 return ERROR_OK;
658 }
659
660 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
661 static unsigned int parity (unsigned int v)
662 {
663 // unsigned int ov = v;
664 v ^= v >> 16;
665 v ^= v >> 8;
666 v ^= v >> 4;
667 v &= 0xf;
668 // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
669 return (0x6996 >> v) & 1;
670 }
671
672 static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
673 {
674 struct xscale_common *xscale = target_to_xscale(target);
675 uint8_t packet[4];
676 uint8_t cmd;
677 int word;
678 struct scan_field fields[2];
679
680 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
681
682 /* LDIC into IR */
683 xscale_jtag_set_instr(target->tap,
684 XSCALE_LDIC << xscale->xscale_variant,
685 TAP_IDLE);
686
687 /* CMD is b011 to load a cacheline into the Mini ICache.
688 * Loading into the main ICache is deprecated, and unused.
689 * It's followed by three zero bits, and 27 address bits.
690 */
691 buf_set_u32(&cmd, 0, 6, 0x3);
692
693 /* virtual address of desired cache line */
694 buf_set_u32(packet, 0, 27, va >> 5);
695
696 memset(&fields, 0, sizeof fields);
697
698 fields[0].num_bits = 6;
699 fields[0].out_value = &cmd;
700
701 fields[1].num_bits = 27;
702 fields[1].out_value = packet;
703
704 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
705
706 /* rest of packet is a cacheline: 8 instructions, with parity */
707 fields[0].num_bits = 32;
708 fields[0].out_value = packet;
709
710 fields[1].num_bits = 1;
711 fields[1].out_value = &cmd;
712
713 for (word = 0; word < 8; word++)
714 {
715 buf_set_u32(packet, 0, 32, buffer[word]);
716
717 uint32_t value;
718 memcpy(&value, packet, sizeof(uint32_t));
719 cmd = parity(value);
720
721 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
722 }
723
724 return jtag_execute_queue();
725 }
726
727 static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
728 {
729 struct xscale_common *xscale = target_to_xscale(target);
730 uint8_t packet[4];
731 uint8_t cmd;
732 struct scan_field fields[2];
733
734 xscale_jtag_set_instr(target->tap,
735 XSCALE_LDIC << xscale->xscale_variant,
736 TAP_IDLE);
737
738 /* CMD for invalidate IC line b000, bits [6:4] b000 */
739 buf_set_u32(&cmd, 0, 6, 0x0);
740
741 /* virtual address of desired cache line */
742 buf_set_u32(packet, 0, 27, va >> 5);
743
744 memset(&fields, 0, sizeof fields);
745
746 fields[0].num_bits = 6;
747 fields[0].out_value = &cmd;
748
749 fields[1].num_bits = 27;
750 fields[1].out_value = packet;
751
752 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
753
754 return ERROR_OK;
755 }
756
757 static int xscale_update_vectors(struct target *target)
758 {
759 struct xscale_common *xscale = target_to_xscale(target);
760 int i;
761 int retval;
762
763 uint32_t low_reset_branch, high_reset_branch;
764
765 for (i = 1; i < 8; i++)
766 {
767 /* if there's a static vector specified for this exception, override */
768 if (xscale->static_high_vectors_set & (1 << i))
769 {
770 xscale->high_vectors[i] = xscale->static_high_vectors[i];
771 }
772 else
773 {
774 retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
775 if (retval == ERROR_TARGET_TIMEOUT)
776 return retval;
777 if (retval != ERROR_OK)
778 {
779 /* Some of these reads will fail as part of normal execution */
780 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
781 }
782 }
783 }
784
785 for (i = 1; i < 8; i++)
786 {
787 if (xscale->static_low_vectors_set & (1 << i))
788 {
789 xscale->low_vectors[i] = xscale->static_low_vectors[i];
790 }
791 else
792 {
793 retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
794 if (retval == ERROR_TARGET_TIMEOUT)
795 return retval;
796 if (retval != ERROR_OK)
797 {
798 /* Some of these reads will fail as part of normal execution */
799 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
800 }
801 }
802 }
803
804 /* calculate branches to debug handler */
805 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
806 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
807
808 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
809 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
810
811 /* invalidate and load exception vectors in mini i-cache */
812 xscale_invalidate_ic_line(target, 0x0);
813 xscale_invalidate_ic_line(target, 0xffff0000);
814
815 xscale_load_ic(target, 0x0, xscale->low_vectors);
816 xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
817
818 return ERROR_OK;
819 }
820
821 static int xscale_arch_state(struct target *target)
822 {
823 struct xscale_common *xscale = target_to_xscale(target);
824 struct arm *armv4_5 = &xscale->armv4_5_common;
825
826 static const char *state[] =
827 {
828 "disabled", "enabled"
829 };
830
831 static const char *arch_dbg_reason[] =
832 {
833 "", "\n(processor reset)", "\n(trace buffer full)"
834 };
835
836 if (armv4_5->common_magic != ARM_COMMON_MAGIC)
837 {
838 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
839 return ERROR_INVALID_ARGUMENTS;
840 }
841
842 arm_arch_state(target);
843 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
844 state[xscale->armv4_5_mmu.mmu_enabled],
845 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
846 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
847 arch_dbg_reason[xscale->arch_debug_reason]);
848
849 return ERROR_OK;
850 }
851
852 static int xscale_poll(struct target *target)
853 {
854 int retval = ERROR_OK;
855
856 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
857 {
858 enum target_state previous_state = target->state;
859 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
860 {
861
862 /* there's data to read from the tx register, we entered debug state */
863 target->state = TARGET_HALTED;
864
865 /* process debug entry, fetching current mode regs */
866 retval = xscale_debug_entry(target);
867 }
868 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
869 {
870 LOG_USER("error while polling TX register, reset CPU");
871 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
872 target->state = TARGET_HALTED;
873 }
874
875 /* debug_entry could have overwritten target state (i.e. immediate resume)
876 * don't signal event handlers in that case
877 */
878 if (target->state != TARGET_HALTED)
879 return ERROR_OK;
880
881 /* if target was running, signal that we halted
882 * otherwise we reentered from debug execution */
883 if (previous_state == TARGET_RUNNING)
884 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
885 else
886 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
887 }
888
889 return retval;
890 }
891
892 static int xscale_debug_entry(struct target *target)
893 {
894 struct xscale_common *xscale = target_to_xscale(target);
895 struct arm *armv4_5 = &xscale->armv4_5_common;
896 uint32_t pc;
897 uint32_t buffer[10];
898 int i;
899 int retval;
900 uint32_t moe;
901
902 /* clear external dbg break (will be written on next DCSR read) */
903 xscale->external_debug_break = 0;
904 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
905 return retval;
906
907 /* get r0, pc, r1 to r7 and cpsr */
908 if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK)
909 return retval;
910
911 /* move r0 from buffer to register cache */
912 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
913 armv4_5->core_cache->reg_list[0].dirty = 1;
914 armv4_5->core_cache->reg_list[0].valid = 1;
915 LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
916
917 /* move pc from buffer to register cache */
918 buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]);
919 armv4_5->pc->dirty = 1;
920 armv4_5->pc->valid = 1;
921 LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
922
923 /* move data from buffer to register cache */
924 for (i = 1; i <= 7; i++)
925 {
926 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
927 armv4_5->core_cache->reg_list[i].dirty = 1;
928 armv4_5->core_cache->reg_list[i].valid = 1;
929 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
930 }
931
932 arm_set_cpsr(armv4_5, buffer[9]);
933 LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
934
935 if (!is_arm_mode(armv4_5->core_mode))
936 {
937 target->state = TARGET_UNKNOWN;
938 LOG_ERROR("cpsr contains invalid mode value - communication failure");
939 return ERROR_TARGET_FAILURE;
940 }
941 LOG_DEBUG("target entered debug state in %s mode",
942 arm_mode_name(armv4_5->core_mode));
943
944 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
945 if (armv4_5->spsr) {
946 xscale_receive(target, buffer, 8);
947 buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]);
948 armv4_5->spsr->dirty = false;
949 armv4_5->spsr->valid = true;
950 }
951 else
952 {
953 /* r8 to r14, but no spsr */
954 xscale_receive(target, buffer, 7);
955 }
956
957 /* move data from buffer to right banked register in cache */
958 for (i = 8; i <= 14; i++)
959 {
960 struct reg *r = arm_reg_current(armv4_5, i);
961
962 buf_set_u32(r->value, 0, 32, buffer[i - 8]);
963 r->dirty = false;
964 r->valid = true;
965 }
966
967 /* examine debug reason */
968 xscale_read_dcsr(target);
969 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
970
971 /* stored PC (for calculating fixup) */
972 pc = buf_get_u32(armv4_5->pc->value, 0, 32);
973
974 switch (moe)
975 {
976 case 0x0: /* Processor reset */
977 target->debug_reason = DBG_REASON_DBGRQ;
978 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
979 pc -= 4;
980 break;
981 case 0x1: /* Instruction breakpoint hit */
982 target->debug_reason = DBG_REASON_BREAKPOINT;
983 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
984 pc -= 4;
985 break;
986 case 0x2: /* Data breakpoint hit */
987 target->debug_reason = DBG_REASON_WATCHPOINT;
988 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
989 pc -= 4;
990 break;
991 case 0x3: /* BKPT instruction executed */
992 target->debug_reason = DBG_REASON_BREAKPOINT;
993 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
994 pc -= 4;
995 break;
996 case 0x4: /* Ext. debug event */
997 target->debug_reason = DBG_REASON_DBGRQ;
998 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
999 pc -= 4;
1000 break;
1001 case 0x5: /* Vector trap occured */
1002 target->debug_reason = DBG_REASON_BREAKPOINT;
1003 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1004 pc -= 4;
1005 break;
1006 case 0x6: /* Trace buffer full break */
1007 target->debug_reason = DBG_REASON_DBGRQ;
1008 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1009 pc -= 4;
1010 break;
1011 case 0x7: /* Reserved (may flag Hot-Debug support) */
1012 default:
1013 LOG_ERROR("Method of Entry is 'Reserved'");
1014 exit(-1);
1015 break;
1016 }
1017
1018 /* apply PC fixup */
1019 buf_set_u32(armv4_5->pc->value, 0, 32, pc);
1020
1021 /* on the first debug entry, identify cache type */
1022 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1023 {
1024 uint32_t cache_type_reg;
1025
1026 /* read cp15 cache type register */
1027 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1028 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1029
1030 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1031 }
1032
1033 /* examine MMU and Cache settings */
1034 /* read cp15 control register */
1035 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1036 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1037 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1038 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1039 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1040
1041 /* tracing enabled, read collected trace data */
1042 if (xscale->trace.buffer_enabled)
1043 {
1044 xscale_read_trace(target);
1045 xscale->trace.buffer_fill--;
1046
1047 /* resume if we're still collecting trace data */
1048 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1049 && (xscale->trace.buffer_fill > 0))
1050 {
1051 xscale_resume(target, 1, 0x0, 1, 0);
1052 }
1053 else
1054 {
1055 xscale->trace.buffer_enabled = 0;
1056 }
1057 }
1058
1059 return ERROR_OK;
1060 }
1061
1062 static int xscale_halt(struct target *target)
1063 {
1064 struct xscale_common *xscale = target_to_xscale(target);
1065
1066 LOG_DEBUG("target->state: %s",
1067 target_state_name(target));
1068
1069 if (target->state == TARGET_HALTED)
1070 {
1071 LOG_DEBUG("target was already halted");
1072 return ERROR_OK;
1073 }
1074 else if (target->state == TARGET_UNKNOWN)
1075 {
1076 /* this must not happen for a xscale target */
1077 LOG_ERROR("target was in unknown state when halt was requested");
1078 return ERROR_TARGET_INVALID;
1079 }
1080 else if (target->state == TARGET_RESET)
1081 {
1082 LOG_DEBUG("target->state == TARGET_RESET");
1083 }
1084 else
1085 {
1086 /* assert external dbg break */
1087 xscale->external_debug_break = 1;
1088 xscale_read_dcsr(target);
1089
1090 target->debug_reason = DBG_REASON_DBGRQ;
1091 }
1092
1093 return ERROR_OK;
1094 }
1095
1096 static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
1097 {
1098 struct xscale_common *xscale = target_to_xscale(target);
1099 struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1100 int retval;
1101
1102 if (xscale->ibcr0_used)
1103 {
1104 struct breakpoint *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1105
1106 if (ibcr0_bp)
1107 {
1108 xscale_unset_breakpoint(target, ibcr0_bp);
1109 }
1110 else
1111 {
1112 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1113 exit(-1);
1114 }
1115 }
1116
1117 if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
1118 return retval;
1119
1120 return ERROR_OK;
1121 }
1122
1123 static int xscale_disable_single_step(struct target *target)
1124 {
1125 struct xscale_common *xscale = target_to_xscale(target);
1126 struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1127 int retval;
1128
1129 if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
1130 return retval;
1131
1132 return ERROR_OK;
1133 }
1134
1135 static void xscale_enable_watchpoints(struct target *target)
1136 {
1137 struct watchpoint *watchpoint = target->watchpoints;
1138
1139 while (watchpoint)
1140 {
1141 if (watchpoint->set == 0)
1142 xscale_set_watchpoint(target, watchpoint);
1143 watchpoint = watchpoint->next;
1144 }
1145 }
1146
1147 static void xscale_enable_breakpoints(struct target *target)
1148 {
1149 struct breakpoint *breakpoint = target->breakpoints;
1150
1151 /* set any pending breakpoints */
1152 while (breakpoint)
1153 {
1154 if (breakpoint->set == 0)
1155 xscale_set_breakpoint(target, breakpoint);
1156 breakpoint = breakpoint->next;
1157 }
1158 }
1159
1160 static int xscale_resume(struct target *target, int current,
1161 uint32_t address, int handle_breakpoints, int debug_execution)
1162 {
1163 struct xscale_common *xscale = target_to_xscale(target);
1164 struct arm *armv4_5 = &xscale->armv4_5_common;
1165 struct breakpoint *breakpoint = target->breakpoints;
1166 uint32_t current_pc;
1167 int retval;
1168 int i;
1169
1170 LOG_DEBUG("-");
1171
1172 if (target->state != TARGET_HALTED)
1173 {
1174 LOG_WARNING("target not halted");
1175 return ERROR_TARGET_NOT_HALTED;
1176 }
1177
1178 if (!debug_execution)
1179 {
1180 target_free_all_working_areas(target);
1181 }
1182
1183 /* update vector tables */
1184 if ((retval = xscale_update_vectors(target)) != ERROR_OK)
1185 return retval;
1186
1187 /* current = 1: continue on current pc, otherwise continue at <address> */
1188 if (!current)
1189 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1190
1191 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1192
1193 /* if we're at the reset vector, we have to simulate the branch */
1194 if (current_pc == 0x0)
1195 {
1196 arm_simulate_step(target, NULL);
1197 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1198 }
1199
1200 /* the front-end may request us not to handle breakpoints */
1201 if (handle_breakpoints)
1202 {
1203 breakpoint = breakpoint_find(target,
1204 buf_get_u32(armv4_5->pc->value, 0, 32));
1205 if (breakpoint != NULL)
1206 {
1207 uint32_t next_pc;
1208 int saved_trace_buffer_enabled;
1209
1210 /* there's a breakpoint at the current PC, we have to step over it */
1211 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1212 xscale_unset_breakpoint(target, breakpoint);
1213
1214 /* calculate PC of next instruction */
1215 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1216 {
1217 uint32_t current_opcode;
1218 target_read_u32(target, current_pc, &current_opcode);
1219 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1220 }
1221
1222 LOG_DEBUG("enable single-step");
1223 xscale_enable_single_step(target, next_pc);
1224
1225 /* restore banked registers */
1226 retval = xscale_restore_banked(target);
1227
1228 /* send resume request */
1229 xscale_send_u32(target, 0x30);
1230
1231 /* send CPSR */
1232 xscale_send_u32(target,
1233 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1234 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1235 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1236
1237 for (i = 7; i >= 0; i--)
1238 {
1239 /* send register */
1240 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1241 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1242 }
1243
1244 /* send PC */
1245 xscale_send_u32(target,
1246 buf_get_u32(armv4_5->pc->value, 0, 32));
1247 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1248 buf_get_u32(armv4_5->pc->value, 0, 32));
1249
1250 /* disable trace data collection in xscale_debug_entry() */
1251 saved_trace_buffer_enabled = xscale->trace.buffer_enabled;
1252 xscale->trace.buffer_enabled = 0;
1253
1254 /* wait for and process debug entry */
1255 xscale_debug_entry(target);
1256
1257 /* re-enable trace buffer, if enabled previously */
1258 xscale->trace.buffer_enabled = saved_trace_buffer_enabled;
1259
1260 LOG_DEBUG("disable single-step");
1261 xscale_disable_single_step(target);
1262
1263 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1264 xscale_set_breakpoint(target, breakpoint);
1265 }
1266 }
1267
1268 /* enable any pending breakpoints and watchpoints */
1269 xscale_enable_breakpoints(target);
1270 xscale_enable_watchpoints(target);
1271
1272 /* restore banked registers */
1273 retval = xscale_restore_banked(target);
1274
1275 /* send resume request (command 0x30 or 0x31)
1276 * clean the trace buffer if it is to be enabled (0x62) */
1277 if (xscale->trace.buffer_enabled)
1278 {
1279 xscale_send_u32(target, 0x62);
1280 xscale_send_u32(target, 0x31);
1281 }
1282 else
1283 xscale_send_u32(target, 0x30);
1284
1285 /* send CPSR */
1286 xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
1287 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1288 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1289
1290 for (i = 7; i >= 0; i--)
1291 {
1292 /* send register */
1293 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1294 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1295 }
1296
1297 /* send PC */
1298 xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32));
1299 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1300 buf_get_u32(armv4_5->pc->value, 0, 32));
1301
1302 target->debug_reason = DBG_REASON_NOTHALTED;
1303
1304 if (!debug_execution)
1305 {
1306 /* registers are now invalid */
1307 register_cache_invalidate(armv4_5->core_cache);
1308 target->state = TARGET_RUNNING;
1309 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1310 }
1311 else
1312 {
1313 target->state = TARGET_DEBUG_RUNNING;
1314 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1315 }
1316
1317 LOG_DEBUG("target resumed");
1318
1319 return ERROR_OK;
1320 }
1321
1322 static int xscale_step_inner(struct target *target, int current,
1323 uint32_t address, int handle_breakpoints)
1324 {
1325 struct xscale_common *xscale = target_to_xscale(target);
1326 struct arm *armv4_5 = &xscale->armv4_5_common;
1327 uint32_t next_pc;
1328 int retval;
1329 int i;
1330
1331 target->debug_reason = DBG_REASON_SINGLESTEP;
1332
1333 /* calculate PC of next instruction */
1334 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1335 {
1336 uint32_t current_opcode, current_pc;
1337 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1338
1339 target_read_u32(target, current_pc, &current_opcode);
1340 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1341 return retval;
1342 }
1343
1344 LOG_DEBUG("enable single-step");
1345 if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK)
1346 return retval;
1347
1348 /* restore banked registers */
1349 if ((retval = xscale_restore_banked(target)) != ERROR_OK)
1350 return retval;
1351
1352 /* send resume request (command 0x30 or 0x31)
1353 * clean the trace buffer if it is to be enabled (0x62) */
1354 if (xscale->trace.buffer_enabled)
1355 {
1356 if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK)
1357 return retval;
1358 if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK)
1359 return retval;
1360 }
1361 else
1362 if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK)
1363 return retval;
1364
1365 /* send CPSR */
1366 retval = xscale_send_u32(target,
1367 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1368 if (retval != ERROR_OK)
1369 return retval;
1370 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1371 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1372
1373 for (i = 7; i >= 0; i--)
1374 {
1375 /* send register */
1376 if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
1377 return retval;
1378 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1379 }
1380
1381 /* send PC */
1382 retval = xscale_send_u32(target,
1383 buf_get_u32(armv4_5->pc->value, 0, 32));
1384 if (retval != ERROR_OK)
1385 return retval;
1386 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1387 buf_get_u32(armv4_5->pc->value, 0, 32));
1388
1389 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1390
1391 /* registers are now invalid */
1392 register_cache_invalidate(armv4_5->core_cache);
1393
1394 /* wait for and process debug entry */
1395 if ((retval = xscale_debug_entry(target)) != ERROR_OK)
1396 return retval;
1397
1398 LOG_DEBUG("disable single-step");
1399 if ((retval = xscale_disable_single_step(target)) != ERROR_OK)
1400 return retval;
1401
1402 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1403
1404 return ERROR_OK;
1405 }
1406
1407 static int xscale_step(struct target *target, int current,
1408 uint32_t address, int handle_breakpoints)
1409 {
1410 struct arm *armv4_5 = target_to_arm(target);
1411 struct breakpoint *breakpoint = NULL;
1412
1413 uint32_t current_pc;
1414 int retval;
1415
1416 if (target->state != TARGET_HALTED)
1417 {
1418 LOG_WARNING("target not halted");
1419 return ERROR_TARGET_NOT_HALTED;
1420 }
1421
1422 /* current = 1: continue on current pc, otherwise continue at <address> */
1423 if (!current)
1424 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1425
1426 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1427
1428 /* if we're at the reset vector, we have to simulate the step */
1429 if (current_pc == 0x0)
1430 {
1431 if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
1432 return retval;
1433 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1434
1435 target->debug_reason = DBG_REASON_SINGLESTEP;
1436 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1437
1438 return ERROR_OK;
1439 }
1440
1441 /* the front-end may request us not to handle breakpoints */
1442 if (handle_breakpoints)
1443 breakpoint = breakpoint_find(target,
1444 buf_get_u32(armv4_5->pc->value, 0, 32));
1445 if (breakpoint != NULL) {
1446 retval = xscale_unset_breakpoint(target, breakpoint);
1447 if (retval != ERROR_OK)
1448 return retval;
1449 }
1450
1451 retval = xscale_step_inner(target, current, address, handle_breakpoints);
1452
1453 if (breakpoint)
1454 {
1455 xscale_set_breakpoint(target, breakpoint);
1456 }
1457
1458 LOG_DEBUG("target stepped");
1459
1460 return ERROR_OK;
1461
1462 }
1463
1464 static int xscale_assert_reset(struct target *target)
1465 {
1466 struct xscale_common *xscale = target_to_xscale(target);
1467
1468 LOG_DEBUG("target->state: %s",
1469 target_state_name(target));
1470
1471 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1472 * end up in T-L-R, which would reset JTAG
1473 */
1474 xscale_jtag_set_instr(target->tap,
1475 XSCALE_SELDCSR << xscale->xscale_variant,
1476 TAP_IDLE);
1477
1478 /* set Hold reset, Halt mode and Trap Reset */
1479 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1480 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1481 xscale_write_dcsr(target, 1, 0);
1482
1483 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1484 xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
1485 jtag_execute_queue();
1486
1487 /* assert reset */
1488 jtag_add_reset(0, 1);
1489
1490 /* sleep 1ms, to be sure we fulfill any requirements */
1491 jtag_add_sleep(1000);
1492 jtag_execute_queue();
1493
1494 target->state = TARGET_RESET;
1495
1496 if (target->reset_halt)
1497 {
1498 int retval;
1499 if ((retval = target_halt(target)) != ERROR_OK)
1500 return retval;
1501 }
1502
1503 return ERROR_OK;
1504 }
1505
1506 static int xscale_deassert_reset(struct target *target)
1507 {
1508 struct xscale_common *xscale = target_to_xscale(target);
1509 struct breakpoint *breakpoint = target->breakpoints;
1510
1511 LOG_DEBUG("-");
1512
1513 xscale->ibcr_available = 2;
1514 xscale->ibcr0_used = 0;
1515 xscale->ibcr1_used = 0;
1516
1517 xscale->dbr_available = 2;
1518 xscale->dbr0_used = 0;
1519 xscale->dbr1_used = 0;
1520
1521 /* mark all hardware breakpoints as unset */
1522 while (breakpoint)
1523 {
1524 if (breakpoint->type == BKPT_HARD)
1525 {
1526 breakpoint->set = 0;
1527 }
1528 breakpoint = breakpoint->next;
1529 }
1530
1531 register_cache_invalidate(xscale->armv4_5_common.core_cache);
1532
1533 /* FIXME mark hardware watchpoints got unset too. Also,
1534 * at least some of the XScale registers are invalid...
1535 */
1536
1537 /*
1538 * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
1539 * contents got invalidated. Safer to force that, so writing new
1540 * contents can't ever fail..
1541 */
1542 {
1543 uint32_t address;
1544 unsigned buf_cnt;
1545 const uint8_t *buffer = xscale_debug_handler;
1546 int retval;
1547
1548 /* release SRST */
1549 jtag_add_reset(0, 0);
1550
1551 /* wait 300ms; 150 and 100ms were not enough */
1552 jtag_add_sleep(300*1000);
1553
1554 jtag_add_runtest(2030, TAP_IDLE);
1555 jtag_execute_queue();
1556
1557 /* set Hold reset, Halt mode and Trap Reset */
1558 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1559 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1560 xscale_write_dcsr(target, 1, 0);
1561
1562 /* Load the debug handler into the mini-icache. Since
1563 * it's using halt mode (not monitor mode), it runs in
1564 * "Special Debug State" for access to registers, memory,
1565 * coprocessors, trace data, etc.
1566 */
1567 address = xscale->handler_address;
1568 for (unsigned binary_size = sizeof xscale_debug_handler - 1;
1569 binary_size > 0;
1570 binary_size -= buf_cnt, buffer += buf_cnt)
1571 {
1572 uint32_t cache_line[8];
1573 unsigned i;
1574
1575 buf_cnt = binary_size;
1576 if (buf_cnt > 32)
1577 buf_cnt = 32;
1578
1579 for (i = 0; i < buf_cnt; i += 4)
1580 {
1581 /* convert LE buffer to host-endian uint32_t */
1582 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1583 }
1584
1585 for (; i < 32; i += 4)
1586 {
1587 cache_line[i / 4] = 0xe1a08008;
1588 }
1589
1590 /* only load addresses other than the reset vectors */
1591 if ((address % 0x400) != 0x0)
1592 {
1593 retval = xscale_load_ic(target, address,
1594 cache_line);
1595 if (retval != ERROR_OK)
1596 return retval;
1597 }
1598
1599 address += buf_cnt;
1600 };
1601
1602 retval = xscale_load_ic(target, 0x0,
1603 xscale->low_vectors);
1604 if (retval != ERROR_OK)
1605 return retval;
1606 retval = xscale_load_ic(target, 0xffff0000,
1607 xscale->high_vectors);
1608 if (retval != ERROR_OK)
1609 return retval;
1610
1611 jtag_add_runtest(30, TAP_IDLE);
1612
1613 jtag_add_sleep(100000);
1614
1615 /* set Hold reset, Halt mode and Trap Reset */
1616 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1617 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1618 xscale_write_dcsr(target, 1, 0);
1619
1620 /* clear Hold reset to let the target run (should enter debug handler) */
1621 xscale_write_dcsr(target, 0, 1);
1622 target->state = TARGET_RUNNING;
1623
1624 if (!target->reset_halt)
1625 {
1626 jtag_add_sleep(10000);
1627
1628 /* we should have entered debug now */
1629 xscale_debug_entry(target);
1630 target->state = TARGET_HALTED;
1631
1632 /* resume the target */
1633 xscale_resume(target, 1, 0x0, 1, 0);
1634 }
1635 }
1636
1637 return ERROR_OK;
1638 }
1639
1640 static int xscale_read_core_reg(struct target *target, struct reg *r,
1641 int num, enum arm_mode mode)
1642 {
1643 /** \todo add debug handler support for core register reads */
1644 LOG_ERROR("not implemented");
1645 return ERROR_OK;
1646 }
1647
1648 static int xscale_write_core_reg(struct target *target, struct reg *r,
1649 int num, enum arm_mode mode, uint32_t value)
1650 {
1651 /** \todo add debug handler support for core register writes */
1652 LOG_ERROR("not implemented");
1653 return ERROR_OK;
1654 }
1655
1656 static int xscale_full_context(struct target *target)
1657 {
1658 struct arm *armv4_5 = target_to_arm(target);
1659
1660 uint32_t *buffer;
1661
1662 int i, j;
1663
1664 LOG_DEBUG("-");
1665
1666 if (target->state != TARGET_HALTED)
1667 {
1668 LOG_WARNING("target not halted");
1669 return ERROR_TARGET_NOT_HALTED;
1670 }
1671
1672 buffer = malloc(4 * 8);
1673
1674 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1675 * we can't enter User mode on an XScale (unpredictable),
1676 * but User shares registers with SYS
1677 */
1678 for (i = 1; i < 7; i++)
1679 {
1680 enum arm_mode mode = armv4_5_number_to_mode(i);
1681 bool valid = true;
1682 struct reg *r;
1683
1684 if (mode == ARM_MODE_USR)
1685 continue;
1686
1687 /* check if there are invalid registers in the current mode
1688 */
1689 for (j = 0; valid && j <= 16; j++)
1690 {
1691 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1692 mode, j).valid)
1693 valid = false;
1694 }
1695 if (valid)
1696 continue;
1697
1698 /* request banked registers */
1699 xscale_send_u32(target, 0x0);
1700
1701 /* send CPSR for desired bank mode */
1702 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1703
1704 /* get banked registers: r8 to r14; and SPSR
1705 * except in USR/SYS mode
1706 */
1707 if (mode != ARM_MODE_SYS) {
1708 /* SPSR */
1709 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1710 mode, 16);
1711
1712 xscale_receive(target, buffer, 8);
1713
1714 buf_set_u32(r->value, 0, 32, buffer[7]);
1715 r->dirty = false;
1716 r->valid = true;
1717 } else {
1718 xscale_receive(target, buffer, 7);
1719 }
1720
1721 /* move data from buffer to register cache */
1722 for (j = 8; j <= 14; j++)
1723 {
1724 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1725 mode, j);
1726
1727 buf_set_u32(r->value, 0, 32, buffer[j - 8]);
1728 r->dirty = false;
1729 r->valid = true;
1730 }
1731 }
1732
1733 free(buffer);
1734
1735 return ERROR_OK;
1736 }
1737
1738 static int xscale_restore_banked(struct target *target)
1739 {
1740 struct arm *armv4_5 = target_to_arm(target);
1741
1742 int i, j;
1743
1744 if (target->state != TARGET_HALTED)
1745 {
1746 LOG_WARNING("target not halted");
1747 return ERROR_TARGET_NOT_HALTED;
1748 }
1749
1750 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1751 * and check if any banked registers need to be written. Ignore
1752 * USR mode (number 0) in favor of SYS; we can't enter User mode on
1753 * an XScale (unpredictable), but they share all registers.
1754 */
1755 for (i = 1; i < 7; i++)
1756 {
1757 enum arm_mode mode = armv4_5_number_to_mode(i);
1758 struct reg *r;
1759
1760 if (mode == ARM_MODE_USR)
1761 continue;
1762
1763 /* check if there are dirty registers in this mode */
1764 for (j = 8; j <= 14; j++)
1765 {
1766 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1767 mode, j).dirty)
1768 goto dirty;
1769 }
1770
1771 /* if not USR/SYS, check if the SPSR needs to be written */
1772 if (mode != ARM_MODE_SYS)
1773 {
1774 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1775 mode, 16).dirty)
1776 goto dirty;
1777 }
1778
1779 /* there's nothing to flush for this mode */
1780 continue;
1781
1782 dirty:
1783 /* command 0x1: "send banked registers" */
1784 xscale_send_u32(target, 0x1);
1785
1786 /* send CPSR for desired mode */
1787 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1788
1789 /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
1790 * but this protocol doesn't understand that nuance.
1791 */
1792 for (j = 8; j <= 14; j++) {
1793 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1794 mode, j);
1795 xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1796 r->dirty = false;
1797 }
1798
1799 /* send spsr if not in USR/SYS mode */
1800 if (mode != ARM_MODE_SYS) {
1801 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
1802 mode, 16);
1803 xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1804 r->dirty = false;
1805 }
1806 }
1807
1808 return ERROR_OK;
1809 }
1810
1811 static int xscale_read_memory(struct target *target, uint32_t address,
1812 uint32_t size, uint32_t count, uint8_t *buffer)
1813 {
1814 struct xscale_common *xscale = target_to_xscale(target);
1815 uint32_t *buf32;
1816 uint32_t i;
1817 int retval;
1818
1819 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1820
1821 if (target->state != TARGET_HALTED)
1822 {
1823 LOG_WARNING("target not halted");
1824 return ERROR_TARGET_NOT_HALTED;
1825 }
1826
1827 /* sanitize arguments */
1828 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1829 return ERROR_INVALID_ARGUMENTS;
1830
1831 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1832 return ERROR_TARGET_UNALIGNED_ACCESS;
1833
1834 /* send memory read request (command 0x1n, n: access size) */
1835 if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
1836 return retval;
1837
1838 /* send base address for read request */
1839 if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1840 return retval;
1841
1842 /* send number of requested data words */
1843 if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1844 return retval;
1845
1846 /* receive data from target (count times 32-bit words in host endianness) */
1847 buf32 = malloc(4 * count);
1848 if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK)
1849 return retval;
1850
1851 /* extract data from host-endian buffer into byte stream */
1852 for (i = 0; i < count; i++)
1853 {
1854 switch (size)
1855 {
1856 case 4:
1857 target_buffer_set_u32(target, buffer, buf32[i]);
1858 buffer += 4;
1859 break;
1860 case 2:
1861 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1862 buffer += 2;
1863 break;
1864 case 1:
1865 *buffer++ = buf32[i] & 0xff;
1866 break;
1867 default:
1868 LOG_ERROR("invalid read size");
1869 return ERROR_INVALID_ARGUMENTS;
1870 }
1871 }
1872
1873 free(buf32);
1874
1875 /* examine DCSR, to see if Sticky Abort (SA) got set */
1876 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1877 return retval;
1878 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1879 {
1880 /* clear SA bit */
1881 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1882 return retval;
1883
1884 return ERROR_TARGET_DATA_ABORT;
1885 }
1886
1887 return ERROR_OK;
1888 }
1889
1890 static int xscale_read_phys_memory(struct target *target, uint32_t address,
1891 uint32_t size, uint32_t count, uint8_t *buffer)
1892 {
1893 struct xscale_common *xscale = target_to_xscale(target);
1894
1895 /* with MMU inactive, there are only physical addresses */
1896 if (!xscale->armv4_5_mmu.mmu_enabled)
1897 return xscale_read_memory(target, address, size, count, buffer);
1898
1899 /** \todo: provide a non-stub implementation of this routine. */
1900 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1901 target_name(target), __func__);
1902 return ERROR_FAIL;
1903 }
1904
1905 static int xscale_write_memory(struct target *target, uint32_t address,
1906 uint32_t size, uint32_t count, uint8_t *buffer)
1907 {
1908 struct xscale_common *xscale = target_to_xscale(target);
1909 int retval;
1910
1911 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1912
1913 if (target->state != TARGET_HALTED)
1914 {
1915 LOG_WARNING("target not halted");
1916 return ERROR_TARGET_NOT_HALTED;
1917 }
1918
1919 /* sanitize arguments */
1920 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1921 return ERROR_INVALID_ARGUMENTS;
1922
1923 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1924 return ERROR_TARGET_UNALIGNED_ACCESS;
1925
1926 /* send memory write request (command 0x2n, n: access size) */
1927 if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
1928 return retval;
1929
1930 /* send base address for read request */
1931 if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1932 return retval;
1933
1934 /* send number of requested data words to be written*/
1935 if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1936 return retval;
1937
1938 /* extract data from host-endian buffer into byte stream */
1939 #if 0
1940 for (i = 0; i < count; i++)
1941 {
1942 switch (size)
1943 {
1944 case 4:
1945 value = target_buffer_get_u32(target, buffer);
1946 xscale_send_u32(target, value);
1947 buffer += 4;
1948 break;
1949 case 2:
1950 value = target_buffer_get_u16(target, buffer);
1951 xscale_send_u32(target, value);
1952 buffer += 2;
1953 break;
1954 case 1:
1955 value = *buffer;
1956 xscale_send_u32(target, value);
1957 buffer += 1;
1958 break;
1959 default:
1960 LOG_ERROR("should never get here");
1961 exit(-1);
1962 }
1963 }
1964 #endif
1965 if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK)
1966 return retval;
1967
1968 /* examine DCSR, to see if Sticky Abort (SA) got set */
1969 if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1970 return retval;
1971 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1972 {
1973 /* clear SA bit */
1974 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1975 return retval;
1976
1977 return ERROR_TARGET_DATA_ABORT;
1978 }
1979
1980 return ERROR_OK;
1981 }
1982
1983 static int xscale_write_phys_memory(struct target *target, uint32_t address,
1984 uint32_t size, uint32_t count, uint8_t *buffer)
1985 {
1986 struct xscale_common *xscale = target_to_xscale(target);
1987
1988 /* with MMU inactive, there are only physical addresses */
1989 if (!xscale->armv4_5_mmu.mmu_enabled)
1990 return xscale_read_memory(target, address, size, count, buffer);
1991
1992 /** \todo: provide a non-stub implementation of this routine. */
1993 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1994 target_name(target), __func__);
1995 return ERROR_FAIL;
1996 }
1997
1998 static int xscale_bulk_write_memory(struct target *target, uint32_t address,
1999 uint32_t count, uint8_t *buffer)
2000 {
2001 return xscale_write_memory(target, address, 4, count, buffer);
2002 }
2003
2004 static int xscale_get_ttb(struct target *target, uint32_t *result)
2005 {
2006 struct xscale_common *xscale = target_to_xscale(target);
2007 uint32_t ttb;
2008 int retval;
2009
2010 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2011 if (retval != ERROR_OK)
2012 return retval;
2013 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2014
2015 *result = ttb;
2016
2017 return ERROR_OK;
2018 }
2019
2020 static int xscale_disable_mmu_caches(struct target *target, int mmu,
2021 int d_u_cache, int i_cache)
2022 {
2023 struct xscale_common *xscale = target_to_xscale(target);
2024 uint32_t cp15_control;
2025 int retval;
2026
2027 /* read cp15 control register */
2028 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2029 if (retval !=ERROR_OK)
2030 return retval;
2031 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2032
2033 if (mmu)
2034 cp15_control &= ~0x1U;
2035
2036 if (d_u_cache)
2037 {
2038 /* clean DCache */
2039 retval = xscale_send_u32(target, 0x50);
2040 if (retval !=ERROR_OK)
2041 return retval;
2042 retval = xscale_send_u32(target, xscale->cache_clean_address);
2043 if (retval !=ERROR_OK)
2044 return retval;
2045
2046 /* invalidate DCache */
2047 retval = xscale_send_u32(target, 0x51);
2048 if (retval !=ERROR_OK)
2049 return retval;
2050
2051 cp15_control &= ~0x4U;
2052 }
2053
2054 if (i_cache)
2055 {
2056 /* invalidate ICache */
2057 retval = xscale_send_u32(target, 0x52);
2058 if (retval !=ERROR_OK)
2059 return retval;
2060 cp15_control &= ~0x1000U;
2061 }
2062
2063 /* write new cp15 control register */
2064 retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2065 if (retval !=ERROR_OK)
2066 return retval;
2067
2068 /* execute cpwait to ensure outstanding operations complete */
2069 retval = xscale_send_u32(target, 0x53);
2070 return retval;
2071 }
2072
2073 static int xscale_enable_mmu_caches(struct target *target, int mmu,
2074 int d_u_cache, int i_cache)
2075 {
2076 struct xscale_common *xscale = target_to_xscale(target);
2077 uint32_t cp15_control;
2078 int retval;
2079
2080 /* read cp15 control register */
2081 retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2082 if (retval !=ERROR_OK)
2083 return retval;
2084 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2085
2086 if (mmu)
2087 cp15_control |= 0x1U;
2088
2089 if (d_u_cache)
2090 cp15_control |= 0x4U;
2091
2092 if (i_cache)
2093 cp15_control |= 0x1000U;
2094
2095 /* write new cp15 control register */
2096 retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2097 if (retval !=ERROR_OK)
2098 return retval;
2099
2100 /* execute cpwait to ensure outstanding operations complete */
2101 retval = xscale_send_u32(target, 0x53);
2102 return retval;
2103 }
2104
2105 static int xscale_set_breakpoint(struct target *target,
2106 struct breakpoint *breakpoint)
2107 {
2108 int retval;
2109 struct xscale_common *xscale = target_to_xscale(target);
2110
2111 if (target->state != TARGET_HALTED)
2112 {
2113 LOG_WARNING("target not halted");
2114 return ERROR_TARGET_NOT_HALTED;
2115 }
2116
2117 if (breakpoint->set)
2118 {
2119 LOG_WARNING("breakpoint already set");
2120 return ERROR_OK;
2121 }
2122
2123 if (breakpoint->type == BKPT_HARD)
2124 {
2125 uint32_t value = breakpoint->address | 1;
2126 if (!xscale->ibcr0_used)
2127 {
2128 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2129 xscale->ibcr0_used = 1;
2130 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2131 }
2132 else if (!xscale->ibcr1_used)
2133 {
2134 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2135 xscale->ibcr1_used = 1;
2136 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2137 }
2138 else
2139 {
2140 LOG_ERROR("BUG: no hardware comparator available");
2141 return ERROR_OK;
2142 }
2143 }
2144 else if (breakpoint->type == BKPT_SOFT)
2145 {
2146 if (breakpoint->length == 4)
2147 {
2148 /* keep the original instruction in target endianness */
2149 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2150 {
2151 return retval;
2152 }
2153 /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2154 if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
2155 {
2156 return retval;
2157 }
2158 }
2159 else
2160 {
2161 /* keep the original instruction in target endianness */
2162 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2163 {
2164 return retval;
2165 }
2166 /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2167 if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
2168 {
2169 return retval;
2170 }
2171 }
2172 breakpoint->set = 1;
2173
2174 xscale_send_u32(target, 0x50); /* clean dcache */
2175 xscale_send_u32(target, xscale->cache_clean_address);
2176 xscale_send_u32(target, 0x51); /* invalidate dcache */
2177 xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
2178 }
2179
2180 return ERROR_OK;
2181 }
2182
2183 static int xscale_add_breakpoint(struct target *target,
2184 struct breakpoint *breakpoint)
2185 {
2186 struct xscale_common *xscale = target_to_xscale(target);
2187
2188 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2189 {
2190 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2191 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2192 }
2193
2194 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2195 {
2196 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2197 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2198 }
2199
2200 if (breakpoint->type == BKPT_HARD)
2201 {
2202 xscale->ibcr_available--;
2203 }
2204
2205 return ERROR_OK;
2206 }
2207
2208 static int xscale_unset_breakpoint(struct target *target,
2209 struct breakpoint *breakpoint)
2210 {
2211 int retval;
2212 struct xscale_common *xscale = target_to_xscale(target);
2213
2214 if (target->state != TARGET_HALTED)
2215 {
2216 LOG_WARNING("target not halted");
2217 return ERROR_TARGET_NOT_HALTED;
2218 }
2219
2220 if (!breakpoint->set)
2221 {
2222 LOG_WARNING("breakpoint not set");
2223 return ERROR_OK;
2224 }
2225
2226 if (breakpoint->type == BKPT_HARD)
2227 {
2228 if (breakpoint->set == 1)
2229 {
2230 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2231 xscale->ibcr0_used = 0;
2232 }
2233 else if (breakpoint->set == 2)
2234 {
2235 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2236 xscale->ibcr1_used = 0;
2237 }
2238 breakpoint->set = 0;
2239 }
2240 else
2241 {
2242 /* restore original instruction (kept in target endianness) */
2243 if (breakpoint->length == 4)
2244 {
2245 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2246 {
2247 return retval;
2248 }
2249 }
2250 else
2251 {
2252 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2253 {
2254 return retval;
2255 }
2256 }
2257 breakpoint->set = 0;
2258
2259 xscale_send_u32(target, 0x50); /* clean dcache */
2260 xscale_send_u32(target, xscale->cache_clean_address);
2261 xscale_send_u32(target, 0x51); /* invalidate dcache */
2262 xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */
2263 }
2264
2265 return ERROR_OK;
2266 }
2267
2268 static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2269 {
2270 struct xscale_common *xscale = target_to_xscale(target);
2271
2272 if (target->state != TARGET_HALTED)
2273 {
2274 LOG_WARNING("target not halted");
2275 return ERROR_TARGET_NOT_HALTED;
2276 }
2277
2278 if (breakpoint->set)
2279 {
2280 xscale_unset_breakpoint(target, breakpoint);
2281 }
2282
2283 if (breakpoint->type == BKPT_HARD)
2284 xscale->ibcr_available++;
2285
2286 return ERROR_OK;
2287 }
2288
2289 static int xscale_set_watchpoint(struct target *target,
2290 struct watchpoint *watchpoint)
2291 {
2292 struct xscale_common *xscale = target_to_xscale(target);
2293 uint32_t enable = 0;
2294 struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2295 uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2296
2297 if (target->state != TARGET_HALTED)
2298 {
2299 LOG_WARNING("target not halted");
2300 return ERROR_TARGET_NOT_HALTED;
2301 }
2302
2303 switch (watchpoint->rw)
2304 {
2305 case WPT_READ:
2306 enable = 0x3;
2307 break;
2308 case WPT_ACCESS:
2309 enable = 0x2;
2310 break;
2311 case WPT_WRITE:
2312 enable = 0x1;
2313 break;
2314 default:
2315 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2316 }
2317
2318 /* For watchpoint across more than one word, both DBR registers must
2319 be enlisted, with the second used as a mask. */
2320 if (watchpoint->length > 4)
2321 {
2322 if (xscale->dbr0_used || xscale->dbr1_used)
2323 {
2324 LOG_ERROR("BUG: sufficient hardware comparators unavailable");
2325 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2326 }
2327
2328 /* Write mask value to DBR1, based on the length argument.
2329 * Address bits ignored by the comparator are those set in mask. */
2330 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
2331 watchpoint->length - 1);
2332 xscale->dbr1_used = 1;
2333 enable |= 0x100; /* DBCON[M] */
2334 }
2335
2336 if (!xscale->dbr0_used)
2337 {
2338 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2339 dbcon_value |= enable;
2340 xscale_set_reg_u32(dbcon, dbcon_value);
2341 watchpoint->set = 1;
2342 xscale->dbr0_used = 1;
2343 }
2344 else if (!xscale->dbr1_used)
2345 {
2346 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2347 dbcon_value |= enable << 2;
2348 xscale_set_reg_u32(dbcon, dbcon_value);
2349 watchpoint->set = 2;
2350 xscale->dbr1_used = 1;
2351 }
2352 else
2353 {
2354 LOG_ERROR("BUG: no hardware comparator available");
2355 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2356 }
2357
2358 return ERROR_OK;
2359 }
2360
2361 static int xscale_add_watchpoint(struct target *target,
2362 struct watchpoint *watchpoint)
2363 {
2364 struct xscale_common *xscale = target_to_xscale(target);
2365
2366 if (xscale->dbr_available < 1)
2367 {
2368 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2369 }
2370
2371 if (watchpoint->value)
2372 LOG_WARNING("xscale does not support value, mask arguments; ignoring");
2373
2374 /* check that length is a power of two */
2375 for (uint32_t len = watchpoint->length; len != 1; len /= 2)
2376 {
2377 if (len % 2)
2378 {
2379 LOG_ERROR("xscale requires that watchpoint length is a power of two");
2380 return ERROR_COMMAND_ARGUMENT_INVALID;
2381 }
2382 }
2383
2384 if (watchpoint->length == 4) /* single word watchpoint */
2385 {
2386 xscale->dbr_available--; /* one DBR reg used */
2387 return ERROR_OK;
2388 }
2389
2390 /* watchpoints across multiple words require both DBR registers */
2391 if (xscale->dbr_available < 2)
2392 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2393
2394 xscale->dbr_available = 0;
2395 return ERROR_OK;
2396 }
2397
2398 static int xscale_unset_watchpoint(struct target *target,
2399 struct watchpoint *watchpoint)
2400 {
2401 struct xscale_common *xscale = target_to_xscale(target);
2402 struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2403 uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2404
2405 if (target->state != TARGET_HALTED)
2406 {
2407 LOG_WARNING("target not halted");
2408 return ERROR_TARGET_NOT_HALTED;
2409 }
2410
2411 if (!watchpoint->set)
2412 {
2413 LOG_WARNING("breakpoint not set");
2414 return ERROR_OK;
2415 }
2416
2417 if (watchpoint->set == 1)
2418 {
2419 if (watchpoint->length > 4)
2420 {
2421 dbcon_value &= ~0x103; /* clear DBCON[M] as well */
2422 xscale->dbr1_used = 0; /* DBR1 was used for mask */
2423 }
2424 else
2425 dbcon_value &= ~0x3;
2426
2427 xscale_set_reg_u32(dbcon, dbcon_value);
2428 xscale->dbr0_used = 0;
2429 }
2430 else if (watchpoint->set == 2)
2431 {
2432 dbcon_value &= ~0xc;
2433 xscale_set_reg_u32(dbcon, dbcon_value);
2434 xscale->dbr1_used = 0;
2435 }
2436 watchpoint->set = 0;
2437
2438 return ERROR_OK;
2439 }
2440
2441 static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
2442 {
2443 struct xscale_common *xscale = target_to_xscale(target);
2444
2445 if (target->state != TARGET_HALTED)
2446 {
2447 LOG_WARNING("target not halted");
2448 return ERROR_TARGET_NOT_HALTED;
2449 }
2450
2451 if (watchpoint->set)
2452 {
2453 xscale_unset_watchpoint(target, watchpoint);
2454 }
2455
2456 if (watchpoint->length > 4)
2457 xscale->dbr_available++; /* both DBR regs now available */
2458
2459 xscale->dbr_available++;
2460
2461 return ERROR_OK;
2462 }
2463
2464 static int xscale_get_reg(struct reg *reg)
2465 {
2466 struct xscale_reg *arch_info = reg->arch_info;
2467 struct target *target = arch_info->target;
2468 struct xscale_common *xscale = target_to_xscale(target);
2469
2470 /* DCSR, TX and RX are accessible via JTAG */
2471 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2472 {
2473 return xscale_read_dcsr(arch_info->target);
2474 }
2475 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2476 {
2477 /* 1 = consume register content */
2478 return xscale_read_tx(arch_info->target, 1);
2479 }
2480 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2481 {
2482 /* can't read from RX register (host -> debug handler) */
2483 return ERROR_OK;
2484 }
2485 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2486 {
2487 /* can't (explicitly) read from TXRXCTRL register */
2488 return ERROR_OK;
2489 }
2490 else /* Other DBG registers have to be transfered by the debug handler */
2491 {
2492 /* send CP read request (command 0x40) */
2493 xscale_send_u32(target, 0x40);
2494
2495 /* send CP register number */
2496 xscale_send_u32(target, arch_info->dbg_handler_number);
2497
2498 /* read register value */
2499 xscale_read_tx(target, 1);
2500 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2501
2502 reg->dirty = 0;
2503 reg->valid = 1;
2504 }
2505
2506 return ERROR_OK;
2507 }
2508
2509 static int xscale_set_reg(struct reg *reg, uint8_t* buf)
2510 {
2511 struct xscale_reg *arch_info = reg->arch_info;
2512 struct target *target = arch_info->target;
2513 struct xscale_common *xscale = target_to_xscale(target);
2514 uint32_t value = buf_get_u32(buf, 0, 32);
2515
2516 /* DCSR, TX and RX are accessible via JTAG */
2517 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2518 {
2519 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2520 return xscale_write_dcsr(arch_info->target, -1, -1);
2521 }
2522 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2523 {
2524 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2525 return xscale_write_rx(arch_info->target);
2526 }
2527 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2528 {
2529 /* can't write to TX register (debug-handler -> host) */
2530 return ERROR_OK;
2531 }
2532 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2533 {
2534 /* can't (explicitly) write to TXRXCTRL register */
2535 return ERROR_OK;
2536 }
2537 else /* Other DBG registers have to be transfered by the debug handler */
2538 {
2539 /* send CP write request (command 0x41) */
2540 xscale_send_u32(target, 0x41);
2541
2542 /* send CP register number */
2543 xscale_send_u32(target, arch_info->dbg_handler_number);
2544
2545 /* send CP register value */
2546 xscale_send_u32(target, value);
2547 buf_set_u32(reg->value, 0, 32, value);
2548 }
2549
2550 return ERROR_OK;
2551 }
2552
2553 static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
2554 {
2555 struct xscale_common *xscale = target_to_xscale(target);
2556 struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2557 struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
2558
2559 /* send CP write request (command 0x41) */
2560 xscale_send_u32(target, 0x41);
2561
2562 /* send CP register number */
2563 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2564
2565 /* send CP register value */
2566 xscale_send_u32(target, value);
2567 buf_set_u32(dcsr->value, 0, 32, value);
2568
2569 return ERROR_OK;
2570 }
2571
2572 static int xscale_read_trace(struct target *target)
2573 {
2574 struct xscale_common *xscale = target_to_xscale(target);
2575 struct arm *armv4_5 = &xscale->armv4_5_common;
2576 struct xscale_trace_data **trace_data_p;
2577
2578 /* 258 words from debug handler
2579 * 256 trace buffer entries
2580 * 2 checkpoint addresses
2581 */
2582 uint32_t trace_buffer[258];
2583 int is_address[256];
2584 int i, j;
2585 unsigned int num_checkpoints = 0;
2586
2587 if (target->state != TARGET_HALTED)
2588 {
2589 LOG_WARNING("target must be stopped to read trace data");
2590 return ERROR_TARGET_NOT_HALTED;
2591 }
2592
2593 /* send read trace buffer command (command 0x61) */
2594 xscale_send_u32(target, 0x61);
2595
2596 /* receive trace buffer content */
2597 xscale_receive(target, trace_buffer, 258);
2598
2599 /* parse buffer backwards to identify address entries */
2600 for (i = 255; i >= 0; i--)
2601 {
2602 /* also count number of checkpointed entries */
2603 if ((trace_buffer[i] & 0xe0) == 0xc0)
2604 num_checkpoints++;
2605
2606 is_address[i] = 0;
2607 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2608 ((trace_buffer[i] & 0xf0) == 0xd0))
2609 {
2610 if (i > 0)
2611 is_address[--i] = 1;
2612 if (i > 0)
2613 is_address[--i] = 1;
2614 if (i > 0)
2615 is_address[--i] = 1;
2616 if (i > 0)
2617 is_address[--i] = 1;
2618 }
2619 }
2620
2621
2622 /* search first non-zero entry that is not part of an address */
2623 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2624 ;
2625
2626 if (j == 256)
2627 {
2628 LOG_DEBUG("no trace data collected");
2629 return ERROR_XSCALE_NO_TRACE_DATA;
2630 }
2631
2632 /* account for possible partial address at buffer start (wrap mode only) */
2633 if (is_address[0])
2634 { /* first entry is address; complete set of 4? */
2635 i = 1;
2636 while (i < 4)
2637 if (!is_address[i++])
2638 break;
2639 if (i < 4)
2640 j += i; /* partial address; can't use it */
2641 }
2642
2643 /* if first valid entry is indirect branch, can't use that either (no address) */
2644 if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
2645 j++;
2646
2647 /* walk linked list to terminating entry */
2648 for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2649 ;
2650
2651 *trace_data_p = malloc(sizeof(struct xscale_trace_data));
2652 (*trace_data_p)->next = NULL;
2653 (*trace_data_p)->chkpt0 = trace_buffer[256];
2654 (*trace_data_p)->chkpt1 = trace_buffer[257];
2655 (*trace_data_p)->last_instruction =
2656 buf_get_u32(armv4_5->pc->value, 0, 32);
2657 (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
2658 (*trace_data_p)->depth = 256 - j;
2659 (*trace_data_p)->num_checkpoints = num_checkpoints;
2660
2661 for (i = j; i < 256; i++)
2662 {
2663 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2664 if (is_address[i])
2665 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2666 else
2667 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2668 }
2669
2670 return ERROR_OK;
2671 }
2672
2673 static int xscale_read_instruction(struct target *target, uint32_t pc,
2674 struct arm_instruction *instruction)
2675 {
2676 struct xscale_common *const xscale = target_to_xscale(target);
2677 int i;
2678 int section = -1;
2679 size_t size_read;
2680 uint32_t opcode;
2681 int retval;
2682
2683 if (!xscale->trace.image)
2684 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2685
2686 /* search for the section the current instruction belongs to */
2687 for (i = 0; i < xscale->trace.image->num_sections; i++)
2688 {
2689 if ((xscale->trace.image->sections[i].base_address <= pc) &&
2690 (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > pc))
2691 {
2692 section = i;
2693 break;
2694 }
2695 }
2696
2697 if (section == -1)
2698 {
2699 /* current instruction couldn't be found in the image */
2700 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2701 }
2702
2703 if (xscale->trace.core_state == ARM_STATE_ARM)
2704 {
2705 uint8_t buf[4];
2706 if ((retval = image_read_section(xscale->trace.image, section,
2707 pc - xscale->trace.image->sections[section].base_address,
2708 4, buf, &size_read)) != ERROR_OK)
2709 {
2710 LOG_ERROR("error while reading instruction: %i", retval);
2711 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2712 }
2713 opcode = target_buffer_get_u32(target, buf);
2714 arm_evaluate_opcode(opcode, pc, instruction);
2715 }
2716 else if (xscale->trace.core_state == ARM_STATE_THUMB)
2717 {
2718 uint8_t buf[2];
2719 if ((retval = image_read_section(xscale->trace.image, section,
2720 pc - xscale->trace.image->sections[section].base_address,
2721 2, buf, &size_read)) != ERROR_OK)
2722 {
2723 LOG_ERROR("error while reading instruction: %i", retval);
2724 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2725 }
2726 opcode = target_buffer_get_u16(target, buf);
2727 thumb_evaluate_opcode(opcode, pc, instruction);
2728 }
2729 else
2730 {
2731 LOG_ERROR("BUG: unknown core state encountered");
2732 exit(-1);
2733 }
2734
2735 return ERROR_OK;
2736 }
2737
2738 /* Extract address encoded into trace data.
2739 * Write result to address referenced by argument 'target', or 0 if incomplete. */
2740 static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
2741 int i, uint32_t *target)
2742 {
2743 /* if there are less than four entries prior to the indirect branch message
2744 * we can't extract the address */
2745 if (i < 4)
2746 *target = 0;
2747 else
2748 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2749 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2750 }
2751
2752 static inline void xscale_display_instruction(struct target *target, uint32_t pc,
2753 struct arm_instruction *instruction,
2754 struct command_context *cmd_ctx)
2755 {
2756 int retval = xscale_read_instruction(target, pc, instruction);
2757 if (retval == ERROR_OK)
2758 command_print(cmd_ctx, "%s", instruction->text);
2759 else
2760 command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc);
2761 }
2762
2763 static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
2764 {
2765 struct xscale_common *xscale = target_to_xscale(target);
2766 struct xscale_trace_data *trace_data = xscale->trace.data;
2767 int i, retval;
2768 uint32_t breakpoint_pc;
2769 struct arm_instruction instruction;
2770 uint32_t current_pc = 0; /* initialized when address determined */
2771
2772 if (!xscale->trace.image)
2773 LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
2774
2775 /* loop for each trace buffer that was loaded from target */
2776 while (trace_data)
2777 {
2778 int chkpt = 0; /* incremented as checkpointed entries found */
2779 int j;
2780
2781 /* FIXME: set this to correct mode when trace buffer is first enabled */
2782 xscale->trace.core_state = ARM_STATE_ARM;
2783
2784 /* loop for each entry in this trace buffer */
2785 for (i = 0; i < trace_data->depth; i++)
2786 {
2787 int exception = 0;
2788 uint32_t chkpt_reg = 0x0;
2789 uint32_t branch_target = 0;
2790 int count;
2791
2792 /* trace entry type is upper nybble of 'message byte' */
2793 int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4;
2794
2795 /* Target addresses of indirect branches are written into buffer
2796 * before the message byte representing the branch. Skip past it */
2797 if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2798 continue;
2799
2800 switch (trace_msg_type)
2801 {
2802 case 0: /* Exceptions */
2803 case 1:
2804 case 2:
2805 case 3:
2806 case 4:
2807 case 5:
2808 case 6:
2809 case 7:
2810 exception = (trace_data->entries[i].data & 0x70) >> 4;
2811
2812 /* FIXME: vector table may be at ffff0000 */
2813 branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
2814 break;
2815
2816 case 8: /* Direct Branch */
2817 break;
2818
2819 case 9: /* Indirect Branch */
2820 xscale_branch_address(trace_data, i, &branch_target);
2821 break;
2822
2823 case 13: /* Checkpointed Indirect Branch */
2824 xscale_branch_address(trace_data, i, &branch_target);
2825 if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2826 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */
2827 else
2828 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */
2829
2830 chkpt++;
2831 break;
2832
2833 case 12: /* Checkpointed Direct Branch */
2834 if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2835 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */
2836 else
2837 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */
2838
2839 /* if no current_pc, checkpoint will be starting point */
2840 if (current_pc == 0)
2841 branch_target = chkpt_reg;
2842
2843 chkpt++;
2844 break;
2845
2846 case 15: /* Roll-over */
2847 break;
2848
2849 default: /* Reserved */
2850 LOG_WARNING("trace is suspect: invalid trace message byte");
2851 continue;
2852
2853 }
2854
2855 /* If we don't have the current_pc yet, but we did get the branch target
2856 * (either from the trace buffer on indirect branch, or from a checkpoint reg),
2857 * then we can start displaying instructions at the next iteration, with
2858 * branch_target as the starting point.
2859 */
2860 if (current_pc == 0)
2861 {
2862 current_pc = branch_target; /* remains 0 unless branch_target obtained */
2863 continue;
2864 }
2865
2866 /* We have current_pc. Read and display the instructions from the image.
2867 * First, display count instructions (lower nybble of message byte). */
2868 count = trace_data->entries[i].data & 0x0f;
2869 for (j = 0; j < count; j++)
2870 {
2871 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2872 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2873 }
2874
2875 /* An additional instruction is implicitly added to count for
2876 * rollover and some exceptions: undef, swi, prefetch abort. */
2877 if ((trace_msg_type == 15) || (exception > 0 && exception < 4))
2878 {
2879 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2880 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2881 }
2882
2883 if (trace_msg_type == 15) /* rollover */
2884 continue;
2885
2886 if (exception)
2887 {
2888 command_print(cmd_ctx, "--- exception %i ---", exception);
2889 continue;
2890 }
2891
2892 /* not exception or rollover; next instruction is a branch and is
2893 * not included in the count */
2894 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2895
2896 /* for direct branches, extract branch destination from instruction */
2897 if ((trace_msg_type == 8) || (trace_msg_type == 12))
2898 {
2899 retval = xscale_read_instruction(target, current_pc, &instruction);
2900 if (retval == ERROR_OK)
2901 current_pc = instruction.info.b_bl_bx_blx.target_address;
2902 else
2903 current_pc = 0; /* branch destination unknown */
2904
2905 /* direct branch w/ checkpoint; can also get from checkpoint reg */
2906 if (trace_msg_type == 12)
2907 {
2908 if (current_pc == 0)
2909 current_pc = chkpt_reg;
2910 else if (current_pc != chkpt_reg) /* sanity check */
2911 LOG_WARNING("trace is suspect: checkpoint register "
2912 "inconsistent with adddress from image");
2913 }
2914
2915 if (current_pc == 0)
2916 command_print(cmd_ctx, "address unknown");
2917
2918 continue;
2919 }
2920
2921 /* indirect branch; the branch destination was read from trace buffer */
2922 if ((trace_msg_type == 9) || (trace_msg_type == 13))
2923 {
2924 current_pc = branch_target;
2925
2926 /* sanity check (checkpoint reg is redundant) */
2927 if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
2928 LOG_WARNING("trace is suspect: checkpoint register "
2929 "inconsistent with address from trace buffer");
2930 }
2931
2932 } /* END: for (i = 0; i < trace_data->depth; i++) */
2933
2934 breakpoint_pc = trace_data->last_instruction; /* used below */
2935 trace_data = trace_data->next;
2936
2937 } /* END: while (trace_data) */
2938
2939 /* Finally... display all instructions up to the value of the pc when the
2940 * debug break occurred (saved when trace data was collected from target).
2941 * This is necessary because the trace only records execution branches and 16
2942 * consecutive instructions (rollovers), so last few typically missed.
2943 */
2944 if (current_pc == 0)
2945 return ERROR_OK; /* current_pc was never found */
2946
2947 /* how many instructions remaining? */
2948 int gap_count = (breakpoint_pc - current_pc) /
2949 (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
2950
2951 /* should never be negative or over 16, but verify */
2952 if (gap_count < 0 || gap_count > 16)
2953 {
2954 LOG_WARNING("trace is suspect: excessive gap at end of trace");
2955 return ERROR_OK; /* bail; large number or negative value no good */
2956 }
2957
2958 /* display remaining instructions */
2959 for (i = 0; i < gap_count; i++)
2960 {
2961 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2962 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2963 }
2964
2965 return ERROR_OK;
2966 }
2967
2968 static const struct reg_arch_type xscale_reg_type = {
2969 .get = xscale_get_reg,
2970 .set = xscale_set_reg,
2971 };
2972
2973 static void xscale_build_reg_cache(struct target *target)
2974 {
2975 struct xscale_common *xscale = target_to_xscale(target);
2976 struct arm *armv4_5 = &xscale->armv4_5_common;
2977 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
2978 struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
2979 int i;
2980 int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
2981
2982 (*cache_p) = arm_build_reg_cache(target, armv4_5);
2983
2984 (*cache_p)->next = malloc(sizeof(struct reg_cache));
2985 cache_p = &(*cache_p)->next;
2986
2987 /* fill in values for the xscale reg cache */
2988 (*cache_p)->name = "XScale registers";
2989 (*cache_p)->next = NULL;
2990 (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
2991 (*cache_p)->num_regs = num_regs;
2992
2993 for (i = 0; i < num_regs; i++)
2994 {
2995 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2996 (*cache_p)->reg_list[i].value = calloc(4, 1);
2997 (*cache_p)->reg_list[i].dirty = 0;
2998 (*cache_p)->reg_list[i].valid = 0;
2999 (*cache_p)->reg_list[i].size = 32;
3000 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
3001 (*cache_p)->reg_list[i].type = &xscale_reg_type;
3002 arch_info[i] = xscale_reg_arch_info[i];
3003 arch_info[i].target = target;
3004 }
3005
3006 xscale->reg_cache = (*cache_p);
3007 }
3008
3009 static int xscale_init_target(struct command_context *cmd_ctx,
3010 struct target *target)
3011 {
3012 xscale_build_reg_cache(target);
3013 return ERROR_OK;
3014 }
3015
3016 static int xscale_init_arch_info(struct target *target,
3017 struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
3018 {
3019 struct arm *armv4_5;
3020 uint32_t high_reset_branch, low_reset_branch;
3021 int i;
3022
3023 armv4_5 = &xscale->armv4_5_common;
3024
3025 /* store architecture specfic data */
3026 xscale->common_magic = XSCALE_COMMON_MAGIC;
3027
3028 /* we don't really *need* a variant param ... */
3029 if (variant) {
3030 int ir_length = 0;
3031
3032 if (strcmp(variant, "pxa250") == 0
3033 || strcmp(variant, "pxa255") == 0
3034 || strcmp(variant, "pxa26x") == 0)
3035 ir_length = 5;
3036 else if (strcmp(variant, "pxa27x") == 0
3037 || strcmp(variant, "ixp42x") == 0
3038 || strcmp(variant, "ixp45x") == 0
3039 || strcmp(variant, "ixp46x") == 0)
3040 ir_length = 7;
3041 else if (strcmp(variant, "pxa3xx") == 0)
3042 ir_length = 11;
3043 else
3044 LOG_WARNING("%s: unrecognized variant %s",
3045 tap->dotted_name, variant);
3046
3047 if (ir_length && ir_length != tap->ir_length) {
3048 LOG_WARNING("%s: IR length for %s is %d; fixing",
3049 tap->dotted_name, variant, ir_length);
3050 tap->ir_length = ir_length;
3051 }
3052 }
3053
3054 /* PXA3xx shifts the JTAG instructions */
3055 if (tap->ir_length == 11)
3056 xscale->xscale_variant = XSCALE_PXA3XX;
3057 else
3058 xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
3059
3060 /* the debug handler isn't installed (and thus not running) at this time */
3061 xscale->handler_address = 0xfe000800;
3062
3063 /* clear the vectors we keep locally for reference */
3064 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
3065 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
3066
3067 /* no user-specified vectors have been configured yet */
3068 xscale->static_low_vectors_set = 0x0;
3069 xscale->static_high_vectors_set = 0x0;
3070
3071 /* calculate branches to debug handler */
3072 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
3073 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
3074
3075 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
3076 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
3077
3078 for (i = 1; i <= 7; i++)
3079 {
3080 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3081 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3082 }
3083
3084 /* 64kB aligned region used for DCache cleaning */
3085 xscale->cache_clean_address = 0xfffe0000;
3086
3087 xscale->hold_rst = 0;
3088 xscale->external_debug_break = 0;
3089
3090 xscale->ibcr_available = 2;
3091 xscale->ibcr0_used = 0;
3092 xscale->ibcr1_used = 0;
3093
3094 xscale->dbr_available = 2;
3095 xscale->dbr0_used = 0;
3096 xscale->dbr1_used = 0;
3097
3098 LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
3099 target_name(target));
3100
3101 xscale->arm_bkpt = ARMV5_BKPT(0x0);
3102 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
3103
3104 xscale->vector_catch = 0x1;
3105
3106 xscale->trace.capture_status = TRACE_IDLE;
3107 xscale->trace.data = NULL;
3108 xscale->trace.image = NULL;
3109 xscale->trace.buffer_enabled = 0;
3110 xscale->trace.buffer_fill = 0;
3111
3112 /* prepare ARMv4/5 specific information */
3113 armv4_5->arch_info = xscale;
3114 armv4_5->read_core_reg = xscale_read_core_reg;
3115 armv4_5->write_core_reg = xscale_write_core_reg;
3116 armv4_5->full_context = xscale_full_context;
3117
3118 arm_init_arch_info(target, armv4_5);
3119
3120 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3121 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3122 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3123 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3124 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3125 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3126 xscale->armv4_5_mmu.has_tiny_pages = 1;
3127 xscale->armv4_5_mmu.mmu_enabled = 0;
3128
3129 return ERROR_OK;
3130 }
3131
3132 static int xscale_target_create(struct target *target, Jim_Interp *interp)
3133 {
3134 struct xscale_common *xscale;
3135
3136 if (sizeof xscale_debug_handler - 1 > 0x800) {
3137 LOG_ERROR("debug_handler.bin: larger than 2kb");
3138 return ERROR_FAIL;
3139 }
3140
3141 xscale = calloc(1, sizeof(*xscale));
3142 if (!xscale)
3143 return ERROR_FAIL;
3144
3145 return xscale_init_arch_info(target, xscale, target->tap,
3146 target->variant);
3147 }
3148
3149 COMMAND_HANDLER(xscale_handle_debug_handler_command)
3150 {
3151 struct target *target = NULL;
3152 struct xscale_common *xscale;
3153 int retval;
3154 uint32_t handler_address;
3155
3156 if (CMD_ARGC < 2)
3157 {
3158 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3159 return ERROR_OK;
3160 }
3161
3162 if ((target = get_target(CMD_ARGV[0])) == NULL)
3163 {
3164 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3165 return ERROR_FAIL;
3166 }
3167
3168 xscale = target_to_xscale(target);
3169 retval = xscale_verify_pointer(CMD_CTX, xscale);
3170 if (retval != ERROR_OK)
3171 return retval;
3172
3173 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
3174
3175 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3176 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3177 {
3178 xscale->handler_address = handler_address;
3179 }
3180 else
3181 {
3182 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3183 return ERROR_FAIL;
3184 }
3185
3186 return ERROR_OK;
3187 }
3188
3189 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
3190 {
3191 struct target *target = NULL;
3192 struct xscale_common *xscale;
3193 int retval;
3194 uint32_t cache_clean_address;
3195
3196 if (CMD_ARGC < 2)
3197 {
3198 return ERROR_COMMAND_SYNTAX_ERROR;
3199 }
3200
3201 target = get_target(CMD_ARGV[0]);
3202 if (target == NULL)
3203 {
3204 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3205 return ERROR_FAIL;
3206 }
3207 xscale = target_to_xscale(target);
3208 retval = xscale_verify_pointer(CMD_CTX, xscale);
3209 if (retval != ERROR_OK)
3210 return retval;
3211
3212 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
3213
3214 if (cache_clean_address & 0xffff)
3215 {
3216 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3217 }
3218 else
3219 {
3220 xscale->cache_clean_address = cache_clean_address;
3221 }
3222
3223 return ERROR_OK;
3224 }
3225
3226 COMMAND_HANDLER(xscale_handle_cache_info_command)
3227 {
3228 struct target *target = get_current_target(CMD_CTX);
3229 struct xscale_common *xscale = target_to_xscale(target);
3230 int retval;
3231
3232 retval = xscale_verify_pointer(CMD_CTX, xscale);
3233 if (retval != ERROR_OK)
3234 return retval;
3235
3236 return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
3237 }
3238
3239 static int xscale_virt2phys(struct target *target,
3240 uint32_t virtual, uint32_t *physical)
3241 {
3242 struct xscale_common *xscale = target_to_xscale(target);
3243 uint32_t cb;
3244
3245 if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
3246 LOG_ERROR(xscale_not);
3247 return ERROR_TARGET_INVALID;
3248 }
3249
3250 uint32_t ret;
3251 int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
3252 virtual, &cb, &ret);
3253 if (retval != ERROR_OK)
3254 return retval;
3255 *physical = ret;
3256 return ERROR_OK;
3257 }
3258
3259 static int xscale_mmu(struct target *target, int *enabled)
3260 {
3261 struct xscale_common *xscale = target_to_xscale(target);
3262
3263 if (target->state != TARGET_HALTED)
3264 {
3265 LOG_ERROR("Target not halted");
3266 return ERROR_TARGET_INVALID;
3267 }
3268 *enabled = xscale->armv4_5_mmu.mmu_enabled;
3269 return ERROR_OK;
3270 }
3271
3272 COMMAND_HANDLER(xscale_handle_mmu_command)
3273 {
3274 struct target *target = get_current_target(CMD_CTX);
3275 struct xscale_common *xscale = target_to_xscale(target);
3276 int retval;
3277
3278 retval = xscale_verify_pointer(CMD_CTX, xscale);
3279 if (retval != ERROR_OK)
3280 return retval;
3281
3282 if (target->state != TARGET_HALTED)
3283 {
3284 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3285 return ERROR_OK;
3286 }
3287
3288 if (CMD_ARGC >= 1)
3289 {
3290 bool enable;
3291 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3292 if (enable)
3293 xscale_enable_mmu_caches(target, 1, 0, 0);
3294 else
3295 xscale_disable_mmu_caches(target, 1, 0, 0);
3296 xscale->armv4_5_mmu.mmu_enabled = enable;
3297 }
3298
3299 command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3300
3301 return ERROR_OK;
3302 }
3303
3304 COMMAND_HANDLER(xscale_handle_idcache_command)
3305 {
3306 struct target *target = get_current_target(CMD_CTX);
3307 struct xscale_common *xscale = target_to_xscale(target);
3308
3309 int retval = xscale_verify_pointer(CMD_CTX, xscale);
3310 if (retval != ERROR_OK)
3311 return retval;
3312
3313 if (target->state != TARGET_HALTED)
3314 {
3315 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3316 return ERROR_OK;
3317 }
3318
3319 bool icache = false;
3320 if (strcmp(CMD_NAME, "icache") == 0)
3321 icache = true;
3322 if (CMD_ARGC >= 1)
3323 {
3324 bool enable;
3325 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3326 if (icache) {
3327 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
3328 if (enable)
3329 xscale_enable_mmu_caches(target, 0, 0, 1);
3330 else
3331 xscale_disable_mmu_caches(target, 0, 0, 1);
3332 } else {
3333 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
3334 if (enable)
3335 xscale_enable_mmu_caches(target, 0, 1, 0);
3336 else
3337 xscale_disable_mmu_caches(target, 0, 1, 0);
3338 }
3339 }
3340
3341 bool enabled = icache ?
3342 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
3343 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
3344 const char *msg = enabled ? "enabled" : "disabled";
3345 command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
3346
3347 return ERROR_OK;
3348 }
3349
3350 COMMAND_HANDLER(xscale_handle_vector_catch_command)
3351 {
3352 struct target *target = get_current_target(CMD_CTX);
3353 struct xscale_common *xscale = target_to_xscale(target);
3354 int retval;
3355
3356 retval = xscale_verify_pointer(CMD_CTX, xscale);
3357 if (retval != ERROR_OK)
3358 return retval;
3359
3360 if (CMD_ARGC < 1)
3361 {
3362 command_print(CMD_CTX, "usage: xscale vector_catch [mask]");
3363 }
3364 else
3365 {
3366 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch);
3367 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3368 xscale_write_dcsr(target, -1, -1);
3369 }
3370
3371 command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3372
3373 return ERROR_OK;
3374 }
3375
3376
3377 COMMAND_HANDLER(xscale_handle_vector_table_command)
3378 {
3379 struct target *target = get_current_target(CMD_CTX);
3380 struct xscale_common *xscale = target_to_xscale(target);
3381 int err = 0;
3382 int retval;
3383
3384 retval = xscale_verify_pointer(CMD_CTX, xscale);
3385 if (retval != ERROR_OK)
3386 return retval;
3387
3388 if (CMD_ARGC == 0) /* print current settings */
3389 {
3390 int idx;
3391
3392 command_print(CMD_CTX, "active user-set static vectors:");
3393 for (idx = 1; idx < 8; idx++)
3394 if (xscale->static_low_vectors_set & (1 << idx))
3395 command_print(CMD_CTX, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
3396 for (idx = 1; idx < 8; idx++)
3397 if (xscale->static_high_vectors_set & (1 << idx))
3398 command_print(CMD_CTX, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
3399 return ERROR_OK;
3400 }
3401
3402 if (CMD_ARGC != 3)
3403 err = 1;
3404 else
3405 {
3406 int idx;
3407 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
3408 uint32_t vec;
3409 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
3410
3411 if (idx < 1 || idx >= 8)
3412 err = 1;
3413
3414 if (!err && strcmp(CMD_ARGV[0], "low") == 0)
3415 {
3416 xscale->static_low_vectors_set |= (1<<idx);
3417 xscale->static_low_vectors[idx] = vec;
3418 }
3419 else if (!err && (strcmp(CMD_ARGV[0], "high") == 0))
3420 {
3421 xscale->static_high_vectors_set |= (1<<idx);
3422 xscale->static_high_vectors[idx] = vec;
3423 }
3424 else
3425 err = 1;
3426 }
3427
3428 if (err)
3429 command_print(CMD_CTX, "usage: xscale vector_table <high|low> <index> <code>");
3430
3431 return ERROR_OK;
3432 }
3433
3434
3435 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
3436 {
3437 struct target *target = get_current_target(CMD_CTX);
3438 struct xscale_common *xscale = target_to_xscale(target);
3439 uint32_t dcsr_value;
3440 int retval;
3441
3442 retval = xscale_verify_pointer(CMD_CTX, xscale);
3443 if (retval != ERROR_OK)
3444 return retval;
3445
3446 if (target->state != TARGET_HALTED)
3447 {
3448 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3449 return ERROR_OK;
3450 }
3451
3452 if ((CMD_ARGC >= 1) && (strcmp("enable", CMD_ARGV[0]) == 0))
3453 {
3454 struct xscale_trace_data *td, *next_td;
3455 xscale->trace.buffer_enabled = 1;
3456
3457 /* free old trace data */
3458 td = xscale->trace.data;
3459 while (td)
3460 {
3461 next_td = td->next;
3462
3463 if (td->entries)
3464 free(td->entries);
3465 free(td);
3466 td = next_td;
3467 }
3468 xscale->trace.data = NULL;
3469 }
3470 else if ((CMD_ARGC >= 1) && (strcmp("disable", CMD_ARGV[0]) == 0))
3471 {
3472 xscale->trace.buffer_enabled = 0;
3473 }
3474
3475 if ((CMD_ARGC >= 2) && (strcmp("fill", CMD_ARGV[1]) == 0))
3476 {
3477 uint32_t fill = 1;
3478 if (CMD_ARGC >= 3)
3479 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], fill);
3480 xscale->trace.buffer_fill = fill;
3481 }
3482 else if ((CMD_ARGC >= 2) && (strcmp("wrap", CMD_ARGV[1]) == 0))
3483 {
3484 xscale->trace.buffer_fill = -1;
3485 }
3486
3487 command_print(CMD_CTX, "trace buffer %s (%s)",
3488 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3489 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3490
3491 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3492 if (xscale->trace.buffer_fill >= 0)
3493 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3494 else
3495 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3496
3497 return ERROR_OK;
3498 }
3499
3500 COMMAND_HANDLER(xscale_handle_trace_image_command)
3501 {
3502 struct target *target = get_current_target(CMD_CTX);
3503 struct xscale_common *xscale = target_to_xscale(target);
3504 int retval;
3505
3506 if (CMD_ARGC < 1)
3507 {
3508 command_print(CMD_CTX, "usage: xscale trace_image <file> [base address] [type]");
3509 return ERROR_OK;
3510 }
3511
3512 retval = xscale_verify_pointer(CMD_CTX, xscale);
3513 if (retval != ERROR_OK)
3514 return retval;
3515
3516 if (xscale->trace.image)
3517 {
3518 image_close(xscale->trace.image);
3519 free(xscale->trace.image);
3520 command_print(CMD_CTX, "previously loaded image found and closed");
3521 }
3522
3523 xscale->trace.image = malloc(sizeof(struct image));
3524 xscale->trace.image->base_address_set = 0;
3525 xscale->trace.image->start_address_set = 0;
3526
3527 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3528 if (CMD_ARGC >= 2)
3529 {
3530 xscale->trace.image->base_address_set = 1;
3531 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
3532 }
3533 else
3534 {
3535 xscale->trace.image->base_address_set = 0;
3536 }
3537
3538 if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
3539 {
3540 free(xscale->trace.image);
3541 xscale->trace.image = NULL;
3542 return ERROR_OK;
3543 }
3544
3545 return ERROR_OK;
3546 }
3547
3548 COMMAND_HANDLER(xscale_handle_dump_trace_command)
3549 {
3550 struct target *target = get_current_target(CMD_CTX);
3551 struct xscale_common *xscale = target_to_xscale(target);
3552 struct xscale_trace_data *trace_data;
3553 struct fileio file;
3554 int retval;
3555
3556 retval = xscale_verify_pointer(CMD_CTX, xscale);
3557 if (retval != ERROR_OK)
3558 return retval;
3559
3560 if (target->state != TARGET_HALTED)
3561 {
3562 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3563 return ERROR_OK;
3564 }
3565
3566 if (CMD_ARGC < 1)
3567 {
3568 command_print(CMD_CTX, "usage: xscale dump_trace <file>");
3569 return ERROR_OK;
3570 }
3571
3572 trace_data = xscale->trace.data;
3573
3574 if (!trace_data)
3575 {
3576 command_print(CMD_CTX, "no trace data collected");
3577 return ERROR_OK;
3578 }
3579
3580 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3581 {
3582 return ERROR_OK;
3583 }
3584
3585 while (trace_data)
3586 {
3587 int i;
3588
3589 fileio_write_u32(&file, trace_data->chkpt0);
3590 fileio_write_u32(&file, trace_data->chkpt1);
3591 fileio_write_u32(&file, trace_data->last_instruction);
3592 fileio_write_u32(&file, trace_data->depth);
3593
3594 for (i = 0; i < trace_data->depth; i++)
3595 fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3596
3597 trace_data = trace_data->next;
3598 }
3599
3600 fileio_close(&file);
3601
3602 return ERROR_OK;
3603 }
3604
3605 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
3606 {
3607 struct target *target = get_current_target(CMD_CTX);
3608 struct xscale_common *xscale = target_to_xscale(target);
3609 int retval;
3610
3611 retval = xscale_verify_pointer(CMD_CTX, xscale);
3612 if (retval != ERROR_OK)
3613 return retval;
3614
3615 xscale_analyze_trace(target, CMD_CTX);
3616
3617 return ERROR_OK;
3618 }
3619
3620 COMMAND_HANDLER(xscale_handle_cp15)
3621 {
3622 struct target *target = get_current_target(CMD_CTX);
3623 struct xscale_common *xscale = target_to_xscale(target);
3624 int retval;
3625
3626 retval = xscale_verify_pointer(CMD_CTX, xscale);
3627 if (retval != ERROR_OK)
3628 return retval;
3629
3630 if (target->state != TARGET_HALTED)
3631 {
3632 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3633 return ERROR_OK;
3634 }
3635 uint32_t reg_no = 0;
3636 struct reg *reg = NULL;
3637 if (CMD_ARGC > 0)
3638 {
3639 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
3640 /*translate from xscale cp15 register no to openocd register*/
3641 switch (reg_no)
3642 {
3643 case 0:
3644 reg_no = XSCALE_MAINID;
3645 break;
3646 case 1:
3647 reg_no = XSCALE_CTRL;
3648 break;
3649 case 2:
3650 reg_no = XSCALE_TTB;
3651 break;
3652 case 3:
3653 reg_no = XSCALE_DAC;
3654 break;
3655 case 5:
3656 reg_no = XSCALE_FSR;
3657 break;
3658 case 6:
3659 reg_no = XSCALE_FAR;
3660 break;
3661 case 13:
3662 reg_no = XSCALE_PID;
3663 break;
3664 case 15:
3665 reg_no = XSCALE_CPACCESS;
3666 break;
3667 default:
3668 command_print(CMD_CTX, "invalid register number");
3669 return ERROR_INVALID_ARGUMENTS;
3670 }
3671 reg = &xscale->reg_cache->reg_list[reg_no];
3672
3673 }
3674 if (CMD_ARGC == 1)
3675 {
3676 uint32_t value;
3677
3678 /* read cp15 control register */
3679 xscale_get_reg(reg);
3680 value = buf_get_u32(reg->value, 0, 32);
3681 command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
3682 }
3683 else if (CMD_ARGC == 2)
3684 {
3685 uint32_t value;
3686 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
3687
3688 /* send CP write request (command 0x41) */
3689 xscale_send_u32(target, 0x41);
3690
3691 /* send CP register number */
3692 xscale_send_u32(target, reg_no);
3693
3694 /* send CP register value */
3695 xscale_send_u32(target, value);
3696
3697 /* execute cpwait to ensure outstanding operations complete */
3698 xscale_send_u32(target, 0x53);
3699 }
3700 else
3701 {
3702 command_print(CMD_CTX, "usage: cp15 [register]<, [value]>");
3703 }
3704
3705 return ERROR_OK;
3706 }
3707
3708 static const struct command_registration xscale_exec_command_handlers[] = {
3709 {
3710 .name = "cache_info",
3711 .handler = xscale_handle_cache_info_command,
3712 .mode = COMMAND_EXEC,
3713 .help = "display information about CPU caches",
3714 },
3715 {
3716 .name = "mmu",
3717 .handler = xscale_handle_mmu_command,
3718 .mode = COMMAND_EXEC,
3719 .help = "enable or disable the MMU",
3720 .usage = "['enable'|'disable']",
3721 },
3722 {
3723 .name = "icache",
3724 .handler = xscale_handle_idcache_command,
3725 .mode = COMMAND_EXEC,
3726 .help = "display ICache state, optionally enabling or "
3727 "disabling it",
3728 .usage = "['enable'|'disable']",
3729 },
3730 {
3731 .name = "dcache",
3732 .handler = xscale_handle_idcache_command,
3733 .mode = COMMAND_EXEC,
3734 .help = "display DCache state, optionally enabling or "
3735 "disabling it",
3736 .usage = "['enable'|'disable']",
3737 },
3738 {
3739 .name = "vector_catch",
3740 .handler = xscale_handle_vector_catch_command,
3741 .mode = COMMAND_EXEC,
3742 .help = "set or display 8-bit mask of vectors "
3743 "that should trigger debug entry",
3744 .usage = "[mask]",
3745 },
3746 {
3747 .name = "vector_table",
3748 .handler = xscale_handle_vector_table_command,
3749 .mode = COMMAND_EXEC,
3750 .help = "set vector table entry in mini-ICache, "
3751 "or display current tables",
3752 .usage = "[('high'|'low') index code]",
3753 },
3754 {
3755 .name = "trace_buffer",
3756 .handler = xscale_handle_trace_buffer_command,
3757 .mode = COMMAND_EXEC,
3758 .help = "display trace buffer status, enable or disable "
3759 "tracing, and optionally reconfigure trace mode",
3760 .usage = "['enable'|'disable' ['fill' number|'wrap']]",
3761 },
3762 {
3763 .name = "dump_trace",
3764 .handler = xscale_handle_dump_trace_command,
3765 .mode = COMMAND_EXEC,
3766 .help = "dump content of trace buffer to file",
3767 .usage = "filename",
3768 },
3769 {
3770 .name = "analyze_trace",
3771 .handler = xscale_handle_analyze_trace_buffer_command,
3772 .mode = COMMAND_EXEC,
3773 .help = "analyze content of trace buffer",
3774 .usage = "",
3775 },
3776 {
3777 .name = "trace_image",
3778 .handler = xscale_handle_trace_image_command,
3779 .mode = COMMAND_EXEC,
3780 .help = "load image from file to address (default 0)",
3781 .usage = "filename [offset [filetype]]",
3782 },
3783 {
3784 .name = "cp15",
3785 .handler = xscale_handle_cp15,
3786 .mode = COMMAND_EXEC,
3787 .help = "Read or write coprocessor 15 register.",
3788 .usage = "register [value]",
3789 },
3790 COMMAND_REGISTRATION_DONE
3791 };
3792 static const struct command_registration xscale_any_command_handlers[] = {
3793 {
3794 .name = "debug_handler",
3795 .handler = xscale_handle_debug_handler_command,
3796 .mode = COMMAND_ANY,
3797 .help = "Change address used for debug handler.",
3798 .usage = "target address",
3799 },
3800 {
3801 .name = "cache_clean_address",
3802 .handler = xscale_handle_cache_clean_address_command,
3803 .mode = COMMAND_ANY,
3804 .help = "Change address used for cleaning data cache.",
3805 .usage = "address",
3806 },
3807 {
3808 .chain = xscale_exec_command_handlers,
3809 },
3810 COMMAND_REGISTRATION_DONE
3811 };
3812 static const struct command_registration xscale_command_handlers[] = {
3813 {
3814 .chain = arm_command_handlers,
3815 },
3816 {
3817 .name = "xscale",
3818 .mode = COMMAND_ANY,
3819 .help = "xscale command group",
3820 .chain = xscale_any_command_handlers,
3821 },
3822 COMMAND_REGISTRATION_DONE
3823 };
3824
3825 struct target_type xscale_target =
3826 {
3827 .name = "xscale",
3828
3829 .poll = xscale_poll,
3830 .arch_state = xscale_arch_state,
3831
3832 .target_request_data = NULL,
3833
3834 .halt = xscale_halt,
3835 .resume = xscale_resume,
3836 .step = xscale_step,
3837
3838 .assert_reset = xscale_assert_reset,
3839 .deassert_reset = xscale_deassert_reset,
3840 .soft_reset_halt = NULL,
3841
3842 /* REVISIT on some cores, allow exporting iwmmxt registers ... */
3843 .get_gdb_reg_list = arm_get_gdb_reg_list,
3844
3845 .read_memory = xscale_read_memory,
3846 .read_phys_memory = xscale_read_phys_memory,
3847 .write_memory = xscale_write_memory,
3848 .write_phys_memory = xscale_write_phys_memory,
3849 .bulk_write_memory = xscale_bulk_write_memory,
3850
3851 .checksum_memory = arm_checksum_memory,
3852 .blank_check_memory = arm_blank_check_memory,
3853
3854 .run_algorithm = armv4_5_run_algorithm,
3855
3856 .add_breakpoint = xscale_add_breakpoint,
3857 .remove_breakpoint = xscale_remove_breakpoint,
3858 .add_watchpoint = xscale_add_watchpoint,
3859 .remove_watchpoint = xscale_remove_watchpoint,
3860
3861 .commands = xscale_command_handlers,
3862 .target_create = xscale_target_create,
3863 .init_target = xscale_init_target,
3864
3865 .virt2phys = xscale_virt2phys,
3866 .mmu = xscale_mmu
3867 };
Marex's Cortex A8 development branch