| commit | b6c4a5db3e306b317308bab1e872b4a66eb65487 | |
| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | |
| Mon, 22 Feb 2016 14:23:10 +0000 (22 15:23 +0100) | ||
| committer | Paul Fertser <fercerpav@gmail.com> | |
| Thu, 24 Mar 2016 12:32:43 +0000 (24 12:32 +0000) | ||
| tree | f761fc2ace6298173a782a72a8f513bdbac523d3 | treesnapshot (tar.gz zip) |
| parent | 0a97b232b15c4519777f9223da33423379983dc4 | commitdiff |
cortex_a: allow physical memory access through AHB-AP again
This feature is required for boards that use a programmatical way
to reset the cpu, like the TI Pandaboard with OMAP4. The board only
has a 14 pin JTAG header that doesn't feature SRST and is reset by
direct write to the PRM_RSTCTL register.
iMX6 can be reset through triggering the on-chip watchdog, but for these
methods to work reliably, access through the AHB-AP without interaction
with the CPU core is necessary.
Change-Id: I9a07a536adda83cc2f93e504384c8c7f0306220b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3359
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This feature is required for boards that use a programmatical way
to reset the cpu, like the TI Pandaboard with OMAP4. The board only
has a 14 pin JTAG header that doesn't feature SRST and is reset by
direct write to the PRM_RSTCTL register.
iMX6 can be reset through triggering the on-chip watchdog, but for these
methods to work reliably, access through the AHB-AP without interaction
with the CPU core is necessary.
Change-Id: I9a07a536adda83cc2f93e504384c8c7f0306220b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3359
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
| src/target/cortex_a.c | diffblobblamehistory |