src/jtag/aice/aice_port.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013 by Andes Technology                                *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20 #ifndef _AICE_PORT_H_
  21 #define _AICE_PORT_H_
  22
  23 #include <target/nds32_edm.h>
  24
  25 #define AICE_MAX_NUM_CORE      (0x10)
  26
  27 #define ERROR_AICE_DISCONNECT  (-200)
  28 #define ERROR_AICE_TIMEOUT     (-201)
  29
  30 enum aice_target_state_s {
  31         AICE_DISCONNECT = 0,
  32         AICE_TARGET_DETACH,
  33         AICE_TARGET_UNKNOWN,
  34         AICE_TARGET_RUNNING,
  35         AICE_TARGET_HALTED,
  36         AICE_TARGET_RESET,
  37         AICE_TARGET_DEBUG_RUNNING,
  38 };
  39
  40 enum aice_srst_type_s {
  41         AICE_SRST = 0x1,
  42         AICE_RESET_HOLD = 0x8,
  43 };
  44
  45 enum aice_target_endian {
  46         AICE_LITTLE_ENDIAN = 0,
  47         AICE_BIG_ENDIAN,
  48 };
  49
  50 enum aice_api_s {
  51         AICE_OPEN = 0x0,
  52         AICE_CLOSE,
  53         AICE_RESET,
  54         AICE_IDCODE,
  55         AICE_SET_JTAG_CLOCK,
  56         AICE_ASSERT_SRST,
  57         AICE_RUN,
  58         AICE_HALT,
  59         AICE_STEP,
  60         AICE_READ_REG,
  61         AICE_WRITE_REG,
  62         AICE_READ_REG_64,
  63         AICE_WRITE_REG_64,
  64         AICE_READ_MEM_UNIT,
  65         AICE_WRITE_MEM_UNIT,
  66         AICE_READ_MEM_BULK,
  67         AICE_WRITE_MEM_BULK,
  68         AICE_READ_DEBUG_REG,
  69         AICE_WRITE_DEBUG_REG,
  70         AICE_STATE,
  71         AICE_MEMORY_ACCESS,
  72         AICE_MEMORY_MODE,
  73         AICE_READ_TLB,
  74         AICE_CACHE_CTL,
  75         AICE_SET_RETRY_TIMES,
  76         AICE_PROGRAM_EDM,
  77         AICE_SET_COMMAND_MODE,
  78         AICE_EXECUTE,
  79         AICE_SET_CUSTOM_SRST_SCRIPT,
  80         AICE_SET_CUSTOM_TRST_SCRIPT,
  81         AICE_SET_CUSTOM_RESTART_SCRIPT,
  82         AICE_SET_COUNT_TO_CHECK_DBGER,
  83         AICE_SET_DATA_ENDIAN,
  84 };
  85
  86 enum aice_error_s {
  87         AICE_OK,
  88         AICE_ACK,
  89         AICE_ERROR,
  90 };
  91
  92 enum aice_cache_ctl_type {
  93         AICE_CACHE_CTL_L1D_INVALALL = 0,
  94         AICE_CACHE_CTL_L1D_VA_INVAL,
  95         AICE_CACHE_CTL_L1D_WBALL,
  96         AICE_CACHE_CTL_L1D_VA_WB,
  97         AICE_CACHE_CTL_L1I_INVALALL,
  98         AICE_CACHE_CTL_L1I_VA_INVAL,
  99 };
 100
 101 enum aice_command_mode {
 102         AICE_COMMAND_MODE_NORMAL,
 103         AICE_COMMAND_MODE_PACK,
 104         AICE_COMMAND_MODE_BATCH,
 105 };
 106
 107 struct aice_port_param_s {
 108         /** */
 109         char *device_desc;
 110         /** */
 111         char *serial;
 112         /** */
 113         uint16_t vid;
 114         /** */
 115         uint16_t pid;
 116         /** */
 117         char *adapter_name;
 118 };
 119
 120 struct aice_port_s {
 121         /** */
 122         uint32_t coreid;
 123         /** */
 124         const struct aice_port *port;
 125 };
 126
 127 /** */
 128 extern struct aice_port_api_s aice_usb_layout_api;
 129
 130 /** */
 131 struct aice_port_api_s {
 132         /** */
 133         int (*open)(struct aice_port_param_s *param);
 134         /** */
 135         int (*close)(void);
 136         /** */
 137         int (*reset)(void);
 138         /** */
 139         int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
 140         /** */
 141         int (*set_jtag_clock)(uint32_t a_clock);
 142         /** */
 143         int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
 144         /** */
 145         int (*run)(uint32_t coreid);
 146         /** */
 147         int (*halt)(uint32_t coreid);
 148         /** */
 149         int (*step)(uint32_t coreid);
 150         /** */
 151         int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
 152         /** */
 153         int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
 154         /** */
 155         int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
 156         /** */
 157         int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
 158         /** */
 159         int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 160                         uint32_t count, uint8_t *buffer);
 161         /** */
 162         int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 163                         uint32_t count, const uint8_t *buffer);
 164         /** */
 165         int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 166                         uint8_t *buffer);
 167         /** */
 168         int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 169                         const uint8_t *buffer);
 170         /** */
 171         int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
 172         /** */
 173         int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
 174
 175         /** */
 176         int (*state)(uint32_t coreid, enum aice_target_state_s *state);
 177
 178         /** */
 179         int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
 180         /** */
 181         int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
 182
 183         /** */
 184         int (*read_tlb)(uint32_t coreid, uint32_t virtual_address, uint32_t *physical_address);
 185
 186         /** */
 187         int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
 188
 189         /** */
 190         int (*set_retry_times)(uint32_t a_retry_times);
 191
 192         /** */
 193         int (*program_edm)(uint32_t coreid, char *command_sequence);
 194
 195         /** */
 196         int (*set_command_mode)(enum aice_command_mode command_mode);
 197
 198         /** */
 199         int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
 200
 201         /** */
 202         int (*set_custom_srst_script)(const char *script);
 203
 204         /** */
 205         int (*set_custom_trst_script)(const char *script);
 206
 207         /** */
 208         int (*set_custom_restart_script)(const char *script);
 209
 210         /** */
 211         int (*set_count_to_check_dbger)(uint32_t count_to_check);
 212
 213         /** */
 214         int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
 215
 216         /** */
 217         int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
 218                 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
 219 };
 220
 221 #define AICE_PORT_UNKNOWN       0
 222 #define AICE_PORT_AICE_USB      1
 223 #define AICE_PORT_AICE_PIPE     2
 224
 225 /** */
 226 struct aice_port {
 227         /** */
 228         char *name;
 229         /** */
 230         int type;
 231         /** */
 232         struct aice_port_api_s *const api;
 233 };
 234
 235 /** */
 236 const struct aice_port *aice_port_get_list(void);
 237
 238 #endif