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mips_ejtag: remove memory protection bit before DM
[openocd.git] / src / target / mips_ejtag.c
blob85748146d0d7725aa6083981f066c7243de4ea06
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "mips32.h"
30 #include "mips_ejtag.h"
31 #include "mips32_dmaacc.h"
32
33 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
34 {
35 struct jtag_tap *tap;
36
37 tap = ejtag_info->tap;
38 assert(tap != NULL);
39
40 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
41 struct scan_field field;
42 uint8_t t[4];
43
44 field.num_bits = tap->ir_length;
45 field.out_value = t;
46 buf_set_u32(t, 0, field.num_bits, new_instr);
47 field.in_value = NULL;
48
49 jtag_add_ir_scan(tap, &field, TAP_IDLE);
50 }
51 }
52
53 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
54 {
55 struct scan_field field;
56 uint8_t r[4];
57
58 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
59
60 field.num_bits = 32;
61 field.out_value = NULL;
62 field.in_value = r;
63
64 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
65
66 int retval;
67 retval = jtag_execute_queue();
68 if (retval != ERROR_OK) {
69 LOG_ERROR("register read failed");
70 return retval;
71 }
72
73 *idcode = buf_get_u32(field.in_value, 0, 32);
74
75 return ERROR_OK;
76 }
77
78 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
79 {
80 struct scan_field field;
81 uint8_t r[4];
82
83 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
84
85 field.num_bits = 32;
86 field.out_value = NULL;
87 field.in_value = r;
88
89 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
90
91 int retval;
92 retval = jtag_execute_queue();
93 if (retval != ERROR_OK) {
94 LOG_ERROR("register read failed");
95 return retval;
96 }
97
98 *impcode = buf_get_u32(field.in_value, 0, 32);
99
100 return ERROR_OK;
101 }
102
103 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
104 {
105 assert(ejtag_info->tap != NULL);
106 struct jtag_tap *tap = ejtag_info->tap;
107
108 struct scan_field field;
109 uint8_t out_scan[12];
110
111 /* processor access "all" register 96 bit */
112 field.num_bits = 96;
113
114 field.out_value = out_scan;
115 buf_set_u32(out_scan, 0, 32, ctrl);
116 buf_set_u32(out_scan + 4, 0, 32, data);
117 buf_set_u32(out_scan + 8, 0, 32, 0);
118
119 field.in_value = in_scan_buf;
120
121 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
122
123 keep_alive();
124 }
125
126 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
127 {
128 struct jtag_tap *tap;
129 tap = ejtag_info->tap;
130 assert(tap != NULL);
131
132 struct scan_field field;
133 uint8_t t[4], r[4];
134 int retval;
135
136 field.num_bits = 32;
137 field.out_value = t;
138 buf_set_u32(t, 0, field.num_bits, *data);
139 field.in_value = r;
140
141 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
142
143 retval = jtag_execute_queue();
144 if (retval != ERROR_OK) {
145 LOG_ERROR("register read failed");
146 return retval;
147 }
148
149 *data = buf_get_u32(field.in_value, 0, 32);
150
151 keep_alive();
152
153 return ERROR_OK;
154 }
155
156 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
157 {
158 uint8_t t[4];
159 struct jtag_tap *tap;
160 tap = ejtag_info->tap;
161 assert(tap != NULL);
162
163 struct scan_field field;
164
165 field.num_bits = 32;
166 field.out_value = t;
167 buf_set_u32(t, 0, field.num_bits, data);
168
169 field.in_value = NULL;
170
171 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
172 }
173
174 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
175 {
176 struct jtag_tap *tap;
177 tap = ejtag_info->tap;
178 assert(tap != NULL);
179
180 struct scan_field field;
181 uint8_t t[4] = {0, 0, 0, 0}, r[4];
182 int retval;
183
184 field.num_bits = 8;
185 field.out_value = t;
186 buf_set_u32(t, 0, field.num_bits, *data);
187 field.in_value = r;
188
189 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
190
191 retval = jtag_execute_queue();
192 if (retval != ERROR_OK) {
193 LOG_ERROR("register read failed");
194 return retval;
195 }
196
197 *data = buf_get_u32(field.in_value, 0, 32);
198
199 return ERROR_OK;
200 }
201
202 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
203 {
204 struct jtag_tap *tap;
205 tap = ejtag_info->tap;
206 assert(tap != NULL);
207
208 struct scan_field field;
209
210 field.num_bits = 8;
211 field.out_value = &data;
212 field.in_value = NULL;
213
214 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
215 }
216
217 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
218 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
219 {
220 struct pracc_queue_info ctx = {.max_code = 7};
221 pracc_queue_init(&ctx);
222 if (ctx.retval != ERROR_OK)
223 goto exit;
224
225 pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
226 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
227 if (!enable_step)
228 pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
229
230 pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
231 pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
232 pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
233 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
234
235 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
236 exit:
237 pracc_queue_free(&ctx);
238 return ctx.retval;
239 }
240
241 /*
242 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
243 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
244 * For example bcm7401 and others. At leas on some
245 * CPUs, DebugMode wont start if this bit is not removed.
246 */
247 static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
248 {
249 uint32_t dcr;
250 int retval;
251
252 retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
253 if (retval != ERROR_OK)
254 goto error;
255
256 dcr &= ~EJTAG_DCR_MP;
257 retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
258 if (retval != ERROR_OK)
259 goto error;
260 return ERROR_OK;
261 error:
262 LOG_ERROR("Failed to remove DCR MPbit!");
263 return retval;
264 }
265
266 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
267 {
268 uint32_t ejtag_ctrl;
269 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
270
271 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
272 if (disable_dcr_mp(ejtag_info) != ERROR_OK)
273 goto error;
274 }
275
276 /* set debug break bit */
277 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
278 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
279
280 /* break bit will be cleared by hardware */
281 ejtag_ctrl = ejtag_info->ejtag_ctrl;
282 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
283 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
284 if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
285 goto error;
286
287 return ERROR_OK;
288 error:
289 LOG_ERROR("Failed to enter Debug Mode!");
290 return ERROR_FAIL;
291 }
292
293 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
294 {
295 uint32_t instr = MIPS32_DRET;
296 struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &instr, .code_count = 1, .store_count = 0};
297
298 /* execute our dret instruction */
299 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
300
301 /* pic32mx workaround, false pending at low core clock */
302 jtag_add_sleep(1000);
303 return ctx.retval;
304 }
305
306 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
307 {
308 int retval;
309
310 retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
311 if (retval != ERROR_OK)
312 return retval;
313 LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
314
315 /* get ejtag version */
316 ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
317
318 switch (ejtag_info->ejtag_version) {
319 case EJTAG_VERSION_20:
320 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
321 break;
322 case EJTAG_VERSION_25:
323 LOG_DEBUG("EJTAG: Version 2.5 Detected");
324 break;
325 case EJTAG_VERSION_26:
326 LOG_DEBUG("EJTAG: Version 2.6 Detected");
327 break;
328 case EJTAG_VERSION_31:
329 LOG_DEBUG("EJTAG: Version 3.1 Detected");
330 break;
331 case EJTAG_VERSION_41:
332 LOG_DEBUG("EJTAG: Version 4.1 Detected");
333 break;
334 case EJTAG_VERSION_51:
335 LOG_DEBUG("EJTAG: Version 5.1 Detected");
336 break;
337 default:
338 LOG_DEBUG("EJTAG: Unknown Version Detected");
339 break;
340 }
341 LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
342 ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
343 ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
344 ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
345 ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
346 ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
347 ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
348 ejtag_info->impcode & EJTAG_DCR_MIPS64 ? " MIPS64" : " MIPS32");
349
350 if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
351 LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
352
353 /* set initial state for ejtag control reg */
354 ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
355 ejtag_info->fast_access_save = -1;
356
357 return ERROR_OK;
358 }
359
360 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
361 {
362 struct jtag_tap *tap;
363
364 tap = ejtag_info->tap;
365 assert(tap != NULL);
366
367 struct scan_field fields[2];
368 uint8_t spracc = 0;
369 uint8_t t[4] = {0, 0, 0, 0};
370
371 /* fastdata 1-bit register */
372 fields[0].num_bits = 1;
373 fields[0].out_value = &spracc;
374 fields[0].in_value = NULL;
375
376 /* processor access data register 32 bit */
377 fields[1].num_bits = 32;
378 fields[1].out_value = t;
379
380 if (write_t) {
381 fields[1].in_value = NULL;
382 buf_set_u32(t, 0, 32, *data);
383 } else
384 fields[1].in_value = (void *) data;
385
386 jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
387
388 if (!write_t && data)
389 jtag_add_callback(mips_le_to_h_u32,
390 (jtag_callback_data_t) data);
391
392 keep_alive();
393
394 return ERROR_OK;
395 }
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