src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #ifndef OPENOCD_TARGET_ARM_H
  26 #define OPENOCD_TARGET_ARM_H
  27
  28 #include <helper/command.h>
  29 #include "target.h"
  30
  31
  32 /**
  33  * @file
  34  * Holds the interface to ARM cores.
  35  *
  36  * At this writing, only "classic ARM" cores built on the ARMv4 register
  37  * and mode model are supported.  The Thumb2-only microcontroller profile
  38  * support has not yet been integrated, affecting Cortex-M parts.
  39  */
  40
  41 /**
  42  * Represent state of an ARM core.
  43  *
  44  * Most numbers match the five low bits of the *PSR registers on
  45  * "classic ARM" processors, which build on the ARMv4 processor
  46  * modes and register set.
  47  *
  48  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  49  *
  50  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  51  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  52  * they support.
  53  */
  54 enum arm_mode {
  55         ARM_MODE_USR = 16,
  56         ARM_MODE_FIQ = 17,
  57         ARM_MODE_IRQ = 18,
  58         ARM_MODE_SVC = 19,
  59         ARM_MODE_MON = 22,
  60         ARM_MODE_ABT = 23,
  61         ARM_MODE_UND = 27,
  62         ARM_MODE_1176_MON = 28,
  63         ARM_MODE_SYS = 31,
  64
  65         ARM_MODE_THREAD = 0,
  66         ARM_MODE_USER_THREAD = 1,
  67         ARM_MODE_HANDLER = 2,
  68
  69         ARMV8_64_EL0T = 0x0,
  70         ARMV8_64_EL1T = 0x4,
  71         ARMV8_64_EL1H = 0x5,
  72         ARMV8_64_EL2T = 0x8,
  73         ARMV8_64_EL2H = 0x9,
  74         ARMV8_64_EL3T = 0xC,
  75         ARMV8_64_EL3H = 0xD,
  76
  77         ARM_MODE_ANY = -1
  78 };
  79
  80 /* VFPv3 internal register numbers mapping to d0:31 */
  81 enum {
  82         ARM_VFP_V3_D0 = 51,
  83         ARM_VFP_V3_D1,
  84         ARM_VFP_V3_D2,
  85         ARM_VFP_V3_D3,
  86         ARM_VFP_V3_D4,
  87         ARM_VFP_V3_D5,
  88         ARM_VFP_V3_D6,
  89         ARM_VFP_V3_D7,
  90         ARM_VFP_V3_D8,
  91         ARM_VFP_V3_D9,
  92         ARM_VFP_V3_D10,
  93         ARM_VFP_V3_D11,
  94         ARM_VFP_V3_D12,
  95         ARM_VFP_V3_D13,
  96         ARM_VFP_V3_D14,
  97         ARM_VFP_V3_D15,
  98         ARM_VFP_V3_D16,
  99         ARM_VFP_V3_D17,
 100         ARM_VFP_V3_D18,
 101         ARM_VFP_V3_D19,
 102         ARM_VFP_V3_D20,
 103         ARM_VFP_V3_D21,
 104         ARM_VFP_V3_D22,
 105         ARM_VFP_V3_D23,
 106         ARM_VFP_V3_D24,
 107         ARM_VFP_V3_D25,
 108         ARM_VFP_V3_D26,
 109         ARM_VFP_V3_D27,
 110         ARM_VFP_V3_D28,
 111         ARM_VFP_V3_D29,
 112         ARM_VFP_V3_D30,
 113         ARM_VFP_V3_D31,
 114         ARM_VFP_V3_FPSCR,
 115 };
 116
 117 const char *arm_mode_name(unsigned psr_mode);
 118 bool is_arm_mode(unsigned psr_mode);
 119
 120 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
 121 enum arm_state {
 122         ARM_STATE_ARM,
 123         ARM_STATE_THUMB,
 124         ARM_STATE_JAZELLE,
 125         ARM_STATE_THUMB_EE,
 126         ARM_STATE_AARCH64,
 127 };
 128
 129 /** ARM vector floating point enabled, if yes which version. */
 130 enum arm_vfp_version {
 131         ARM_VFP_DISABLED,
 132         ARM_VFP_V1,
 133         ARM_VFP_V2,
 134         ARM_VFP_V3,
 135 };
 136
 137 #define ARM_COMMON_MAGIC 0x0A450A45
 138
 139 /**
 140  * Represents a generic ARM core, with standard application registers.
 141  *
 142  * There are sixteen application registers (including PC, SP, LR) and a PSR.
 143  * Cortex-M series cores do not support as many core states or shadowed
 144  * registers as traditional ARM cores, and only support Thumb2 instructions.
 145  */
 146 struct arm {
 147         int common_magic;
 148         struct reg_cache *core_cache;
 149
 150         /** Handle to the PC; valid in all core modes. */
 151         struct reg *pc;
 152
 153         /** Handle to the CPSR/xPSR; valid in all core modes. */
 154         struct reg *cpsr;
 155
 156         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 157         struct reg *spsr;
 158
 159         /** Support for arm_reg_current() */
 160         const int *map;
 161
 162         /**
 163          * Indicates what registers are in the ARM state core register set.
 164          * ARM_MODE_ANY indicates the standard set of 37 registers,
 165          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 166          * more registers are shadowed, for "Secure Monitor" mode.
 167          * ARM_MODE_THREAD indicates a microcontroller profile core,
 168          * which only shadows SP.
 169          */
 170         enum arm_mode core_type;
 171
 172         /** Record the current core mode: SVC, USR, or some other mode. */
 173         enum arm_mode core_mode;
 174
 175         /** Record the current core state: ARM, Thumb, or otherwise. */
 176         enum arm_state core_state;
 177
 178         /** Flag reporting unavailability of the BKPT instruction. */
 179         bool is_armv4;
 180
 181         /** Flag reporting armv6m based core. */
 182         bool is_armv6m;
 183
 184         /** Flag reporting whether semihosting is active. */
 185         bool is_semihosting;
 186
 187         /** Flag reporting whether semihosting fileio is active. */
 188         bool is_semihosting_fileio;
 189
 190         /** Flag reporting whether semihosting fileio operation is active. */
 191         bool semihosting_hit_fileio;
 192
 193         /** Floating point or VFP version, 0 if disabled. */
 194         int arm_vfp_version;
 195
 196         /** Current semihosting operation. */
 197         int semihosting_op;
 198
 199         /** Current semihosting result. */
 200         int semihosting_result;
 201
 202         /** Value to be returned by semihosting SYS_ERRNO request. */
 203         int semihosting_errno;
 204
 205         int (*setup_semihosting)(struct target *target, int enable);
 206
 207         /** Semihosting command line. */
 208         char *semihosting_cmdline;
 209
 210         /** Backpointer to the target. */
 211         struct target *target;
 212
 213         /** Handle for the debug module, if one is present. */
 214         struct arm_dpm *dpm;
 215
 216         /** Handle for the Embedded Trace Module, if one is present. */
 217         struct etm_context *etm;
 218
 219         /* FIXME all these methods should take "struct arm *" not target */
 220
 221         /** Retrieve all core registers, for display. */
 222         int (*full_context)(struct target *target);
 223
 224         /** Retrieve a single core register. */
 225         int (*read_core_reg)(struct target *target, struct reg *reg,
 226                         int num, enum arm_mode mode);
 227         int (*write_core_reg)(struct target *target, struct reg *reg,
 228                         int num, enum arm_mode mode, uint8_t *value);
 229
 230         /** Read coprocessor register.  */
 231         int (*mrc)(struct target *target, int cpnum,
 232                         uint32_t op1, uint32_t op2,
 233                         uint32_t CRn, uint32_t CRm,
 234                         uint32_t *value);
 235
 236         /** Write coprocessor register.  */
 237         int (*mcr)(struct target *target, int cpnum,
 238                         uint32_t op1, uint32_t op2,
 239                         uint32_t CRn, uint32_t CRm,
 240                         uint32_t value);
 241
 242         void *arch_info;
 243
 244         /** For targets conforming to ARM Debug Interface v5,
 245          * this handle references the Debug Access Port (DAP)
 246          * used to make requests to the target.
 247          */
 248         struct adiv5_dap *dap;
 249 };
 250
 251 /** Convert target handle to generic ARM target state handle. */
 252 static inline struct arm *target_to_arm(struct target *target)
 253 {
 254         assert(target != NULL);
 255         return target->arch_info;
 256 }
 257
 258 static inline bool is_arm(struct arm *arm)
 259 {
 260         assert(arm != NULL);
 261         return arm->common_magic == ARM_COMMON_MAGIC;
 262 }
 263
 264 struct arm_algorithm {
 265         int common_magic;
 266
 267         enum arm_mode core_mode;
 268         enum arm_state core_state;
 269 };
 270
 271 struct arm_reg {
 272         int num;
 273         enum arm_mode mode;
 274         struct target *target;
 275         struct arm *arm;
 276         uint8_t value[16];
 277 };
 278
 279 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 280 struct reg_cache *armv8_build_reg_cache(struct target *target);
 281
 282 extern const struct command_registration arm_command_handlers[];
 283
 284 int arm_arch_state(struct target *target);
 285 int arm_get_gdb_reg_list(struct target *target,
 286                 struct reg **reg_list[], int *reg_list_size,
 287                 enum target_register_class reg_class);
 288 int armv8_get_gdb_reg_list(struct target *target,
 289                 struct reg **reg_list[], int *reg_list_size,
 290                 enum target_register_class reg_class);
 291
 292 int arm_init_arch_info(struct target *target, struct arm *arm);
 293
 294 /* REVISIT rename this once it's usable by ARMv7-M */
 295 int armv4_5_run_algorithm(struct target *target,
 296                 int num_mem_params, struct mem_param *mem_params,
 297                 int num_reg_params, struct reg_param *reg_params,
 298                 target_addr_t entry_point, target_addr_t exit_point,
 299                 int timeout_ms, void *arch_info);
 300 int armv4_5_run_algorithm_inner(struct target *target,
 301                 int num_mem_params, struct mem_param *mem_params,
 302                 int num_reg_params, struct reg_param *reg_params,
 303                 uint32_t entry_point, uint32_t exit_point,
 304                 int timeout_ms, void *arch_info,
 305                 int (*run_it)(struct target *target, uint32_t exit_point,
 306                                 int timeout_ms, void *arch_info));
 307
 308 int arm_checksum_memory(struct target *target,
 309                 target_addr_t address, uint32_t count, uint32_t *checksum);
 310 int arm_blank_check_memory(struct target *target,
 311                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 312
 313 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 314 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 315 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
 316
 317 extern struct reg arm_gdb_dummy_fp_reg;
 318 extern struct reg arm_gdb_dummy_fps_reg;
 319
 320 #endif /* OPENOCD_TARGET_ARM_H */