1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
28 #include "mips_ejtag.h"
29 #include "mips32_dmaacc.h"
31 void mips_ejtag_set_instr(struct mips_ejtag
*ejtag_info
, uint32_t new_instr
)
33 assert(ejtag_info
->tap
!= NULL
);
34 struct jtag_tap
*tap
= ejtag_info
->tap
;
36 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
) {
38 struct scan_field field
;
39 field
.num_bits
= tap
->ir_length
;
43 buf_set_u32(t
, 0, field
.num_bits
, new_instr
);
45 field
.in_value
= NULL
;
47 jtag_add_ir_scan(tap
, &field
, TAP_IDLE
);
51 int mips_ejtag_get_idcode(struct mips_ejtag
*ejtag_info
, uint32_t *idcode
)
53 struct scan_field field
;
56 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IDCODE
);
59 field
.out_value
= NULL
;
62 jtag_add_dr_scan(ejtag_info
->tap
, 1, &field
, TAP_IDLE
);
65 retval
= jtag_execute_queue();
66 if (retval
!= ERROR_OK
) {
67 LOG_ERROR("register read failed");
71 *idcode
= buf_get_u32(field
.in_value
, 0, 32);
76 static int mips_ejtag_get_impcode(struct mips_ejtag
*ejtag_info
, uint32_t *impcode
)
78 struct scan_field field
;
81 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IMPCODE
);
84 field
.out_value
= NULL
;
87 jtag_add_dr_scan(ejtag_info
->tap
, 1, &field
, TAP_IDLE
);
90 retval
= jtag_execute_queue();
91 if (retval
!= ERROR_OK
) {
92 LOG_ERROR("register read failed");
96 *impcode
= buf_get_u32(field
.in_value
, 0, 32);
101 void mips_ejtag_add_scan_96(struct mips_ejtag
*ejtag_info
, uint32_t ctrl
, uint32_t data
, uint8_t *in_scan_buf
)
103 assert(ejtag_info
->tap
!= NULL
);
104 struct jtag_tap
*tap
= ejtag_info
->tap
;
106 struct scan_field field
;
107 uint8_t out_scan
[12];
109 /* processor access "all" register 96 bit */
112 field
.out_value
= out_scan
;
113 buf_set_u32(out_scan
, 0, 32, ctrl
);
114 buf_set_u32(out_scan
+ 4, 0, 32, data
);
115 buf_set_u32(out_scan
+ 8, 0, 32, 0);
117 field
.in_value
= in_scan_buf
;
119 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
124 void mips_ejtag_drscan_32_queued(struct mips_ejtag
*ejtag_info
, uint32_t data_out
, uint8_t *data_in
)
126 assert(ejtag_info
->tap
!= NULL
);
127 struct jtag_tap
*tap
= ejtag_info
->tap
;
129 struct scan_field field
;
133 field
.out_value
= scan_out
;
134 buf_set_u32(scan_out
, 0, field
.num_bits
, data_out
);
136 field
.in_value
= data_in
;
137 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
142 int mips_ejtag_drscan_32(struct mips_ejtag
*ejtag_info
, uint32_t *data
)
145 mips_ejtag_drscan_32_queued(ejtag_info
, *data
, scan_in
);
147 int retval
= jtag_execute_queue();
148 if (retval
!= ERROR_OK
) {
149 LOG_ERROR("register read failed");
153 *data
= buf_get_u32(scan_in
, 0, 32);
157 void mips_ejtag_drscan_32_out(struct mips_ejtag
*ejtag_info
, uint32_t data
)
159 mips_ejtag_drscan_32_queued(ejtag_info
, data
, NULL
);
162 int mips_ejtag_drscan_8(struct mips_ejtag
*ejtag_info
, uint8_t *data
)
164 assert(ejtag_info
->tap
!= NULL
);
165 struct jtag_tap
*tap
= ejtag_info
->tap
;
167 struct scan_field field
;
170 field
.out_value
= data
;
171 field
.in_value
= data
;
173 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
175 int retval
= jtag_execute_queue();
176 if (retval
!= ERROR_OK
) {
177 LOG_ERROR("register read failed");
183 void mips_ejtag_drscan_8_out(struct mips_ejtag
*ejtag_info
, uint8_t data
)
185 assert(ejtag_info
->tap
!= NULL
);
186 struct jtag_tap
*tap
= ejtag_info
->tap
;
188 struct scan_field field
;
191 field
.out_value
= &data
;
192 field
.in_value
= NULL
;
194 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
197 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
198 int mips_ejtag_config_step(struct mips_ejtag
*ejtag_info
, int enable_step
)
200 struct pracc_queue_info ctx
;
201 pracc_queue_init(&ctx
);
203 pracc_add(&ctx
, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
204 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
206 pracc_add(&ctx
, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
208 pracc_add(&ctx
, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
209 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of $8 */
210 pracc_add(&ctx
, 0, MIPS32_B(NEG16((ctx
.code_count
+ 1)))); /* jump to start */
211 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of $8 */
213 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
, 1);
214 pracc_queue_free(&ctx
);
219 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
220 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
221 * For example bcm7401 and others. At leas on some
222 * CPUs, DebugMode wont start if this bit is not removed.
224 static int disable_dcr_mp(struct mips_ejtag
*ejtag_info
)
229 retval
= mips32_dmaacc_read_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
230 if (retval
!= ERROR_OK
)
233 dcr
&= ~EJTAG_DCR_MP
;
234 retval
= mips32_dmaacc_write_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
235 if (retval
!= ERROR_OK
)
239 LOG_ERROR("Failed to remove DCR MPbit!");
243 int mips_ejtag_enter_debug(struct mips_ejtag
*ejtag_info
)
246 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
248 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
249 if (disable_dcr_mp(ejtag_info
) != ERROR_OK
)
253 /* set debug break bit */
254 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_JTAGBRK
;
255 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
257 /* break bit will be cleared by hardware */
258 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
259 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
260 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32
"", ejtag_ctrl
);
261 if ((ejtag_ctrl
& EJTAG_CTRL_BRKST
) == 0)
266 LOG_ERROR("Failed to enter Debug Mode!");
270 int mips_ejtag_exit_debug(struct mips_ejtag
*ejtag_info
)
272 pa_list pracc_list
= {.instr
= MIPS32_DRET
, .addr
= 0};
273 struct pracc_queue_info ctx
= {.max_code
= 1, .pracc_list
= &pracc_list
, .code_count
= 1, .store_count
= 0};
275 /* execute our dret instruction */
276 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
, 0);
278 /* pic32mx workaround, false pending at low core clock */
279 jtag_add_sleep(1000);
283 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
286 static void mips_ejtag_init_mmr(struct mips_ejtag
*ejtag_info
)
288 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
289 ejtag_info
->ejtag_ibs_addr
= EJTAG_V20_IBS
;
290 ejtag_info
->ejtag_iba0_addr
= EJTAG_V20_IBA0
;
291 ejtag_info
->ejtag_ibc_offs
= EJTAG_V20_IBC_OFFS
;
292 ejtag_info
->ejtag_ibm_offs
= EJTAG_V20_IBM_OFFS
;
294 ejtag_info
->ejtag_dbs_addr
= EJTAG_V20_DBS
;
295 ejtag_info
->ejtag_dba0_addr
= EJTAG_V20_DBA0
;
296 ejtag_info
->ejtag_dbc_offs
= EJTAG_V20_DBC_OFFS
;
297 ejtag_info
->ejtag_dbm_offs
= EJTAG_V20_DBM_OFFS
;
298 ejtag_info
->ejtag_dbv_offs
= EJTAG_V20_DBV_OFFS
;
300 ejtag_info
->ejtag_iba_step_size
= EJTAG_V20_IBAn_STEP
;
301 ejtag_info
->ejtag_dba_step_size
= EJTAG_V20_DBAn_STEP
;
303 ejtag_info
->ejtag_ibs_addr
= EJTAG_V25_IBS
;
304 ejtag_info
->ejtag_iba0_addr
= EJTAG_V25_IBA0
;
305 ejtag_info
->ejtag_ibm_offs
= EJTAG_V25_IBM_OFFS
;
306 ejtag_info
->ejtag_ibasid_offs
= EJTAG_V25_IBASID_OFFS
;
307 ejtag_info
->ejtag_ibc_offs
= EJTAG_V25_IBC_OFFS
;
309 ejtag_info
->ejtag_dbs_addr
= EJTAG_V25_DBS
;
310 ejtag_info
->ejtag_dba0_addr
= EJTAG_V25_DBA0
;
311 ejtag_info
->ejtag_dbm_offs
= EJTAG_V25_DBM_OFFS
;
312 ejtag_info
->ejtag_dbasid_offs
= EJTAG_V25_DBASID_OFFS
;
313 ejtag_info
->ejtag_dbc_offs
= EJTAG_V25_DBC_OFFS
;
314 ejtag_info
->ejtag_dbv_offs
= EJTAG_V25_DBV_OFFS
;
316 ejtag_info
->ejtag_iba_step_size
= EJTAG_V25_IBAn_STEP
;
317 ejtag_info
->ejtag_dba_step_size
= EJTAG_V25_DBAn_STEP
;
321 static void ejtag_v20_print_imp(struct mips_ejtag
*ejtag_info
)
323 LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
324 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP
) ? " SDBBP_SPECIAL2" : " SDBBP",
325 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT
) ? " EADDR>32bit" : " EADDR=32bit",
326 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK
) ? " COMPLEX_BREAK" : "",
327 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH
) ? " DCACHE_COH" : " DCACHE_NOT_COH",
328 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH
) ? " ICACHE_COH" : " ICACHE_NOT_COH",
329 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB
) ? " noPB" : " PB",
330 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB
) ? " noDB" : " DB",
331 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB
) ? " noIB" : " IB");
332 LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8
,
333 (uint8_t)((ejtag_info
->impcode
>> EJTAG_V20_IMP_BCHANNELS_SHIFT
) &
334 EJTAG_V20_IMP_BCHANNELS_MASK
));
337 static void ejtag_v26_print_imp(struct mips_ejtag
*ejtag_info
)
339 LOG_DEBUG("EJTAG v2.6: features:%s%s",
340 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K
) ? " R3k" : " R4k",
341 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT
) ? " DINT" : "");
344 static void ejtag_main_print_imp(struct mips_ejtag
*ejtag_info
)
346 LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
347 EJTAG_IMP_HAS(EJTAG_IMP_ASID8
) ? " ASID_8" : "",
348 EJTAG_IMP_HAS(EJTAG_IMP_ASID6
) ? " ASID_6" : "",
349 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16
) ? " MIPS16" : "",
350 EJTAG_IMP_HAS(EJTAG_IMP_NODMA
) ? " noDMA" : " DMA",
351 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64
) ? " MIPS64" : " MIPS32");
353 switch (ejtag_info
->ejtag_version
) {
354 case EJTAG_VERSION_20
:
355 ejtag_v20_print_imp(ejtag_info
);
357 case EJTAG_VERSION_25
:
358 case EJTAG_VERSION_26
:
359 case EJTAG_VERSION_31
:
360 case EJTAG_VERSION_41
:
361 case EJTAG_VERSION_51
:
362 ejtag_v26_print_imp(ejtag_info
);
369 int mips_ejtag_init(struct mips_ejtag
*ejtag_info
)
373 retval
= mips_ejtag_get_impcode(ejtag_info
, &ejtag_info
->impcode
);
374 if (retval
!= ERROR_OK
)
376 LOG_DEBUG("impcode: 0x%8.8" PRIx32
"", ejtag_info
->impcode
);
378 /* get ejtag version */
379 ejtag_info
->ejtag_version
= ((ejtag_info
->impcode
>> 29) & 0x07);
381 switch (ejtag_info
->ejtag_version
) {
382 case EJTAG_VERSION_20
:
383 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
385 case EJTAG_VERSION_25
:
386 LOG_DEBUG("EJTAG: Version 2.5 Detected");
388 case EJTAG_VERSION_26
:
389 LOG_DEBUG("EJTAG: Version 2.6 Detected");
391 case EJTAG_VERSION_31
:
392 LOG_DEBUG("EJTAG: Version 3.1 Detected");
394 case EJTAG_VERSION_41
:
395 LOG_DEBUG("EJTAG: Version 4.1 Detected");
397 case EJTAG_VERSION_51
:
398 LOG_DEBUG("EJTAG: Version 5.1 Detected");
401 LOG_DEBUG("EJTAG: Unknown Version Detected");
404 ejtag_main_print_imp(ejtag_info
);
406 if ((ejtag_info
->impcode
& EJTAG_IMP_NODMA
) == 0) {
407 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
408 "workaround current broken code.");
409 ejtag_info
->impcode
|= EJTAG_IMP_NODMA
;
412 ejtag_info
->ejtag_ctrl
= EJTAG_CTRL_PRACC
| EJTAG_CTRL_PROBEN
;
414 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
)
415 ejtag_info
->ejtag_ctrl
|= EJTAG_CTRL_ROCC
| EJTAG_CTRL_SETDEV
;
417 ejtag_info
->fast_access_save
= -1;
419 mips_ejtag_init_mmr(ejtag_info
);
424 int mips_ejtag_fastdata_scan(struct mips_ejtag
*ejtag_info
, int write_t
, uint32_t *data
)
426 assert(ejtag_info
->tap
!= NULL
);
427 struct jtag_tap
*tap
= ejtag_info
->tap
;
429 struct scan_field fields
[2];
431 /* fastdata 1-bit register */
432 fields
[0].num_bits
= 1;
435 fields
[0].out_value
= &spracc
;
436 fields
[0].in_value
= NULL
;
438 /* processor access data register 32 bit */
439 fields
[1].num_bits
= 32;
441 uint8_t t
[4] = {0, 0, 0, 0};
442 fields
[1].out_value
= t
;
445 fields
[1].in_value
= NULL
;
446 buf_set_u32(t
, 0, 32, *data
);
448 fields
[1].in_value
= (uint8_t *) data
;
450 jtag_add_dr_scan(tap
, 2, fields
, TAP_IDLE
);
452 if (!write_t
&& data
)
453 jtag_add_callback(mips_le_to_h_u32
,
454 (jtag_callback_data_t
) data
);