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flash/nor/stm32lx: Add revision 'V' for STM32L1xx Cat.3 devices
[openocd.git] / src / flash / nor / stm32lx.c
blob3251df3fcfe6f44abacba341ff6875f02d724e54
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33 #include <target/cortex_m.h>
34
35 /* stm32lx flash register locations */
36
37 #define FLASH_ACR 0x00
38 #define FLASH_PECR 0x04
39 #define FLASH_PDKEYR 0x08
40 #define FLASH_PEKEYR 0x0C
41 #define FLASH_PRGKEYR 0x10
42 #define FLASH_OPTKEYR 0x14
43 #define FLASH_SR 0x18
44 #define FLASH_OBR 0x1C
45 #define FLASH_WRPR 0x20
46
47 /* FLASH_ACR bites */
48 #define FLASH_ACR__LATENCY (1<<0)
49 #define FLASH_ACR__PRFTEN (1<<1)
50 #define FLASH_ACR__ACC64 (1<<2)
51 #define FLASH_ACR__SLEEP_PD (1<<3)
52 #define FLASH_ACR__RUN_PD (1<<4)
53
54 /* FLASH_PECR bits */
55 #define FLASH_PECR__PELOCK (1<<0)
56 #define FLASH_PECR__PRGLOCK (1<<1)
57 #define FLASH_PECR__OPTLOCK (1<<2)
58 #define FLASH_PECR__PROG (1<<3)
59 #define FLASH_PECR__DATA (1<<4)
60 #define FLASH_PECR__FTDW (1<<8)
61 #define FLASH_PECR__ERASE (1<<9)
62 #define FLASH_PECR__FPRG (1<<10)
63 #define FLASH_PECR__EOPIE (1<<16)
64 #define FLASH_PECR__ERRIE (1<<17)
65 #define FLASH_PECR__OBL_LAUNCH (1<<18)
66
67 /* FLASH_SR bits */
68 #define FLASH_SR__BSY (1<<0)
69 #define FLASH_SR__EOP (1<<1)
70 #define FLASH_SR__ENDHV (1<<2)
71 #define FLASH_SR__READY (1<<3)
72 #define FLASH_SR__WRPERR (1<<8)
73 #define FLASH_SR__PGAERR (1<<9)
74 #define FLASH_SR__SIZERR (1<<10)
75 #define FLASH_SR__OPTVERR (1<<11)
76
77 /* Unlock keys */
78 #define PEKEY1 0x89ABCDEF
79 #define PEKEY2 0x02030405
80 #define PRGKEY1 0x8C9DAEBF
81 #define PRGKEY2 0x13141516
82 #define OPTKEY1 0xFBEAD9C8
83 #define OPTKEY2 0x24252627
84
85 /* other registers */
86 #define DBGMCU_IDCODE 0xE0042000
87 #define DBGMCU_IDCODE_L0 0x40015800
88
89 /* Constants */
90 #define FLASH_SECTOR_SIZE 4096
91 #define FLASH_BANK0_ADDRESS 0x08000000
92
93 /* option bytes */
94 #define OPTION_BYTES_ADDRESS 0x1FF80000
95
96 #define OPTION_BYTE_0_PR1 0xFFFF0000
97 #define OPTION_BYTE_0_PR0 0xFF5500AA
98
99 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
100 static int stm32lx_lock_program_memory(struct flash_bank *bank);
101 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
102 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
103 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
104 static int stm32lx_lock(struct flash_bank *bank);
105 static int stm32lx_unlock(struct flash_bank *bank);
106 static int stm32lx_mass_erase(struct flash_bank *bank);
107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
108 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb);
109
110 struct stm32lx_rev {
111 uint16_t rev;
112 const char *str;
113 };
114
115 struct stm32lx_part_info {
116 uint16_t id;
117 const char *device_str;
118 const struct stm32lx_rev *revs;
119 size_t num_revs;
120 unsigned int page_size;
121 unsigned int pages_per_sector;
122 uint16_t max_flash_size_kb;
123 uint16_t first_bank_size_kb; /* used when has_dual_banks is true */
124 bool has_dual_banks;
125
126 uint32_t flash_base; /* Flash controller registers location */
127 uint32_t fsize_base; /* Location of FSIZE register */
128 };
129
130 struct stm32lx_flash_bank {
131 int probed;
132 uint32_t idcode;
133 uint32_t user_bank_size;
134 uint32_t flash_base;
135
136 struct stm32lx_part_info part_info;
137 };
138
139 static const struct stm32lx_rev stm32_416_revs[] = {
140 { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
141 };
142 static const struct stm32lx_rev stm32_417_revs[] = {
143 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
144 };
145 static const struct stm32lx_rev stm32_425_revs[] = {
146 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
147 };
148 static const struct stm32lx_rev stm32_427_revs[] = {
149 { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },
150 };
151 static const struct stm32lx_rev stm32_429_revs[] = {
152 { 0x1000, "A" }, { 0x1018, "Z" },
153 };
154 static const struct stm32lx_rev stm32_436_revs[] = {
155 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
156 };
157 static const struct stm32lx_rev stm32_437_revs[] = {
158 { 0x1000, "A" },
159 };
160 static const struct stm32lx_rev stm32_447_revs[] = {
161 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
162 };
163 static const struct stm32lx_rev stm32_457_revs[] = {
164 { 0x1000, "A" }, { 0x1008, "Z" },
165 };
166
167 static const struct stm32lx_part_info stm32lx_parts[] = {
168 {
169 .id = 0x416,
170 .revs = stm32_416_revs,
171 .num_revs = ARRAY_SIZE(stm32_416_revs),
172 .device_str = "STM32L1xx (Cat.1 - Low/Medium Density)",
173 .page_size = 256,
174 .pages_per_sector = 16,
175 .max_flash_size_kb = 128,
176 .has_dual_banks = false,
177 .flash_base = 0x40023C00,
178 .fsize_base = 0x1FF8004C,
179 },
180 {
181 .id = 0x417,
182 .revs = stm32_417_revs,
183 .num_revs = ARRAY_SIZE(stm32_417_revs),
184 .device_str = "STM32L0xx (Cat. 3)",
185 .page_size = 128,
186 .pages_per_sector = 32,
187 .max_flash_size_kb = 64,
188 .has_dual_banks = false,
189 .flash_base = 0x40022000,
190 .fsize_base = 0x1FF8007C,
191 },
192 {
193 .id = 0x425,
194 .revs = stm32_425_revs,
195 .num_revs = ARRAY_SIZE(stm32_425_revs),
196 .device_str = "STM32L0xx (Cat. 2)",
197 .page_size = 128,
198 .pages_per_sector = 32,
199 .max_flash_size_kb = 32,
200 .has_dual_banks = false,
201 .flash_base = 0x40022000,
202 .fsize_base = 0x1FF8007C,
203 },
204 {
205 .id = 0x427,
206 .revs = stm32_427_revs,
207 .num_revs = ARRAY_SIZE(stm32_427_revs),
208 .device_str = "STM32L1xx (Cat.3 - Medium+ Density)",
209 .page_size = 256,
210 .pages_per_sector = 16,
211 .max_flash_size_kb = 256,
212 .has_dual_banks = false,
213 .flash_base = 0x40023C00,
214 .fsize_base = 0x1FF800CC,
215 },
216 {
217 .id = 0x429,
218 .revs = stm32_429_revs,
219 .num_revs = ARRAY_SIZE(stm32_429_revs),
220 .device_str = "STM32L1xx (Cat.2)",
221 .page_size = 256,
222 .pages_per_sector = 16,
223 .max_flash_size_kb = 128,
224 .has_dual_banks = false,
225 .flash_base = 0x40023C00,
226 .fsize_base = 0x1FF8004C,
227 },
228 {
229 .id = 0x436,
230 .revs = stm32_436_revs,
231 .num_revs = ARRAY_SIZE(stm32_436_revs),
232 .device_str = "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
233 .page_size = 256,
234 .pages_per_sector = 16,
235 .max_flash_size_kb = 384,
236 .first_bank_size_kb = 192,
237 .has_dual_banks = true,
238 .flash_base = 0x40023C00,
239 .fsize_base = 0x1FF800CC,
240 },
241 {
242 .id = 0x437,
243 .revs = stm32_437_revs,
244 .num_revs = ARRAY_SIZE(stm32_437_revs),
245 .device_str = "STM32L1xx (Cat.5/Cat.6)",
246 .page_size = 256,
247 .pages_per_sector = 16,
248 .max_flash_size_kb = 512,
249 .first_bank_size_kb = 0, /* determined in runtime */
250 .has_dual_banks = true,
251 .flash_base = 0x40023C00,
252 .fsize_base = 0x1FF800CC,
253 },
254 {
255 .id = 0x447,
256 .revs = stm32_447_revs,
257 .num_revs = ARRAY_SIZE(stm32_447_revs),
258 .device_str = "STM32L0xx (Cat.5)",
259 .page_size = 128,
260 .pages_per_sector = 32,
261 .max_flash_size_kb = 192,
262 .first_bank_size_kb = 0, /* determined in runtime */
263 .has_dual_banks = false, /* determined in runtime */
264 .flash_base = 0x40022000,
265 .fsize_base = 0x1FF8007C,
266 },
267 {
268 .id = 0x457,
269 .revs = stm32_457_revs,
270 .num_revs = ARRAY_SIZE(stm32_457_revs),
271 .device_str = "STM32L0xx (Cat.1)",
272 .page_size = 128,
273 .pages_per_sector = 32,
274 .max_flash_size_kb = 16,
275 .has_dual_banks = false,
276 .flash_base = 0x40022000,
277 .fsize_base = 0x1FF8007C,
278 },
279 };
280
281 /* flash bank stm32lx <base> <size> 0 0 <target#>
282 */
283 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
284 {
285 struct stm32lx_flash_bank *stm32lx_info;
286 if (CMD_ARGC < 6)
287 return ERROR_COMMAND_SYNTAX_ERROR;
288
289 /* Create the bank structure */
290 stm32lx_info = calloc(1, sizeof(*stm32lx_info));
291
292 /* Check allocation */
293 if (stm32lx_info == NULL) {
294 LOG_ERROR("failed to allocate bank structure");
295 return ERROR_FAIL;
296 }
297
298 bank->driver_priv = stm32lx_info;
299
300 stm32lx_info->probed = 0;
301 stm32lx_info->user_bank_size = bank->size;
302
303 /* the stm32l erased value is 0x00 */
304 bank->default_padded_value = bank->erased_value = 0x00;
305
306 return ERROR_OK;
307 }
308
309 COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
310 {
311 int i;
312
313 if (CMD_ARGC < 1)
314 return ERROR_COMMAND_SYNTAX_ERROR;
315
316 struct flash_bank *bank;
317 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
318 if (ERROR_OK != retval)
319 return retval;
320
321 retval = stm32lx_mass_erase(bank);
322 if (retval == ERROR_OK) {
323 /* set all sectors as erased */
324 for (i = 0; i < bank->num_sectors; i++)
325 bank->sectors[i].is_erased = 1;
326
327 command_print(CMD_CTX, "stm32lx mass erase complete");
328 } else {
329 command_print(CMD_CTX, "stm32lx mass erase failed");
330 }
331
332 return retval;
333 }
334
335 COMMAND_HANDLER(stm32lx_handle_lock_command)
336 {
337 if (CMD_ARGC < 1)
338 return ERROR_COMMAND_SYNTAX_ERROR;
339
340 struct flash_bank *bank;
341 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
342 if (ERROR_OK != retval)
343 return retval;
344
345 retval = stm32lx_lock(bank);
346
347 if (retval == ERROR_OK)
348 command_print(CMD_CTX, "STM32Lx locked, takes effect after power cycle.");
349 else
350 command_print(CMD_CTX, "STM32Lx lock failed");
351
352 return retval;
353 }
354
355 COMMAND_HANDLER(stm32lx_handle_unlock_command)
356 {
357 if (CMD_ARGC < 1)
358 return ERROR_COMMAND_SYNTAX_ERROR;
359
360 struct flash_bank *bank;
361 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
362 if (ERROR_OK != retval)
363 return retval;
364
365 retval = stm32lx_unlock(bank);
366
367 if (retval == ERROR_OK)
368 command_print(CMD_CTX, "STM32Lx unlocked, takes effect after power cycle.");
369 else
370 command_print(CMD_CTX, "STM32Lx unlock failed");
371
372 return retval;
373 }
374
375 static int stm32lx_protect_check(struct flash_bank *bank)
376 {
377 int retval;
378 struct target *target = bank->target;
379 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
380
381 uint32_t wrpr;
382
383 /*
384 * Read the WRPR word, and check each bit (corresponding to each
385 * flash sector
386 */
387 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
388 &wrpr);
389 if (retval != ERROR_OK)
390 return retval;
391
392 for (int i = 0; i < bank->num_sectors; i++) {
393 if (wrpr & (1 << i))
394 bank->sectors[i].is_protected = 1;
395 else
396 bank->sectors[i].is_protected = 0;
397 }
398 return ERROR_OK;
399 }
400
401 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
402 {
403 int retval;
404
405 /*
406 * It could be possible to do a mass erase if all sectors must be
407 * erased, but it is not implemented yet.
408 */
409
410 if (bank->target->state != TARGET_HALTED) {
411 LOG_ERROR("Target not halted");
412 return ERROR_TARGET_NOT_HALTED;
413 }
414
415 /*
416 * Loop over the selected sectors and erase them
417 */
418 for (int i = first; i <= last; i++) {
419 retval = stm32lx_erase_sector(bank, i);
420 if (retval != ERROR_OK)
421 return retval;
422 bank->sectors[i].is_erased = 1;
423 }
424 return ERROR_OK;
425 }
426
427 static int stm32lx_protect(struct flash_bank *bank, int set, int first,
428 int last)
429 {
430 LOG_WARNING("protection of the STM32L flash is not implemented");
431 return ERROR_OK;
432 }
433
434 static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer,
435 uint32_t offset, uint32_t count)
436 {
437 struct target *target = bank->target;
438 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
439
440 uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
441 uint32_t buffer_size = 16384;
442 struct working_area *write_algorithm;
443 struct working_area *source;
444 uint32_t address = bank->base + offset;
445
446 struct reg_param reg_params[3];
447 struct armv7m_algorithm armv7m_info;
448
449 int retval = ERROR_OK;
450
451 static const uint8_t stm32lx_flash_write_code[] = {
452 #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
453 };
454
455 /* Make sure we're performing a half-page aligned write. */
456 if (count % hp_nb) {
457 LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIi32 "B)", hp_nb, count);
458 return ERROR_FAIL;
459 }
460
461 /* flash write code */
462 if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
463 &write_algorithm) != ERROR_OK) {
464 LOG_DEBUG("no working area for block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
466 }
467
468 /* Write the flashing code */
469 retval = target_write_buffer(target,
470 write_algorithm->address,
471 sizeof(stm32lx_flash_write_code),
472 stm32lx_flash_write_code);
473 if (retval != ERROR_OK) {
474 target_free_working_area(target, write_algorithm);
475 return retval;
476 }
477
478 /* Allocate half pages memory */
479 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
480 if (buffer_size > 1024)
481 buffer_size -= 1024;
482 else
483 buffer_size /= 2;
484
485 if (buffer_size <= stm32lx_info->part_info.page_size) {
486 /* we already allocated the writing code, but failed to get a
487 * buffer, free the algorithm */
488 target_free_working_area(target, write_algorithm);
489
490 LOG_WARNING("no large enough working area available, can't do block memory writes");
491 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
492 }
493 }
494
495 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
496 armv7m_info.core_mode = ARM_MODE_THREAD;
497 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
498 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
499 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
500
501 /* Enable half-page write */
502 retval = stm32lx_enable_write_half_page(bank);
503 if (retval != ERROR_OK) {
504 target_free_working_area(target, source);
505 target_free_working_area(target, write_algorithm);
506
507 destroy_reg_param(&reg_params[0]);
508 destroy_reg_param(&reg_params[1]);
509 destroy_reg_param(&reg_params[2]);
510 return retval;
511 }
512
513 struct armv7m_common *armv7m = target_to_armv7m(target);
514 if (armv7m == NULL) {
515
516 /* something is very wrong if armv7m is NULL */
517 LOG_ERROR("unable to get armv7m target");
518 return retval;
519 }
520
521 /* save any DEMCR flags and configure target to catch any Hard Faults */
522 uint32_t demcr_save = armv7m->demcr;
523 armv7m->demcr = VC_HARDERR;
524
525 /* Loop while there are bytes to write */
526 while (count > 0) {
527 uint32_t this_count;
528 this_count = (count > buffer_size) ? buffer_size : count;
529
530 /* Write the next half pages */
531 retval = target_write_buffer(target, source->address, this_count, buffer);
532 if (retval != ERROR_OK)
533 break;
534
535 /* 4: Store useful information in the registers */
536 /* the destination address of the copy (R0) */
537 buf_set_u32(reg_params[0].value, 0, 32, address);
538 /* The source address of the copy (R1) */
539 buf_set_u32(reg_params[1].value, 0, 32, source->address);
540 /* The length of the copy (R2) */
541 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
542
543 /* 5: Execute the bunch of code */
544 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
545 / sizeof(*reg_params), reg_params,
546 write_algorithm->address, 0, 10000, &armv7m_info);
547 if (retval != ERROR_OK)
548 break;
549
550 /* check for Hard Fault */
551 if (armv7m->exception_number == 3)
552 break;
553
554 /* 6: Wait while busy */
555 retval = stm32lx_wait_until_bsy_clear(bank);
556 if (retval != ERROR_OK)
557 break;
558
559 buffer += this_count;
560 address += this_count;
561 count -= this_count;
562 }
563
564 /* restore previous flags */
565 armv7m->demcr = demcr_save;
566
567 if (armv7m->exception_number == 3) {
568
569 /* the stm32l15x devices seem to have an issue when blank.
570 * if a ram loader is executed on a blank device it will
571 * Hard Fault, this issue does not happen for a already programmed device.
572 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
573 * The workaround of handling the Hard Fault exception does work, but makes the
574 * loader more complicated, as a compromise we manually write the pages, programming time
575 * is reduced by 50% using this slower method.
576 */
577
578 LOG_WARNING("Couldn't use loader, falling back to page memory writes");
579
580 while (count > 0) {
581 uint32_t this_count;
582 this_count = (count > hp_nb) ? hp_nb : count;
583
584 /* Write the next half pages */
585 retval = target_write_buffer(target, address, this_count, buffer);
586 if (retval != ERROR_OK)
587 break;
588
589 /* Wait while busy */
590 retval = stm32lx_wait_until_bsy_clear(bank);
591 if (retval != ERROR_OK)
592 break;
593
594 buffer += this_count;
595 address += this_count;
596 count -= this_count;
597 }
598 }
599
600 if (retval == ERROR_OK)
601 retval = stm32lx_lock_program_memory(bank);
602
603 target_free_working_area(target, source);
604 target_free_working_area(target, write_algorithm);
605
606 destroy_reg_param(&reg_params[0]);
607 destroy_reg_param(&reg_params[1]);
608 destroy_reg_param(&reg_params[2]);
609
610 return retval;
611 }
612
613 static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
614 uint32_t offset, uint32_t count)
615 {
616 struct target *target = bank->target;
617 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
618
619 uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
620 uint32_t halfpages_number;
621 uint32_t bytes_remaining = 0;
622 uint32_t address = bank->base + offset;
623 uint32_t bytes_written = 0;
624 int retval, retval2;
625
626 if (bank->target->state != TARGET_HALTED) {
627 LOG_ERROR("Target not halted");
628 return ERROR_TARGET_NOT_HALTED;
629 }
630
631 if (offset & 0x3) {
632 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
633 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
634 }
635
636 retval = stm32lx_unlock_program_memory(bank);
637 if (retval != ERROR_OK)
638 return retval;
639
640 /* first we need to write any unaligned head bytes upto
641 * the next 128 byte page */
642
643 if (offset % hp_nb)
644 bytes_remaining = MIN(count, hp_nb - (offset % hp_nb));
645
646 while (bytes_remaining > 0) {
647 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
648
649 /* copy remaining bytes into the write buffer */
650 uint32_t bytes_to_write = MIN(4, bytes_remaining);
651 memcpy(value, buffer + bytes_written, bytes_to_write);
652
653 retval = target_write_buffer(target, address, 4, value);
654 if (retval != ERROR_OK)
655 goto reset_pg_and_lock;
656
657 bytes_written += bytes_to_write;
658 bytes_remaining -= bytes_to_write;
659 address += 4;
660
661 retval = stm32lx_wait_until_bsy_clear(bank);
662 if (retval != ERROR_OK)
663 goto reset_pg_and_lock;
664 }
665
666 offset += bytes_written;
667 count -= bytes_written;
668
669 /* this should always pass this check here */
670 assert((offset % hp_nb) == 0);
671
672 /* calculate half pages */
673 halfpages_number = count / hp_nb;
674
675 if (halfpages_number) {
676 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, hp_nb * halfpages_number);
677 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
678 /* attempt slow memory writes */
679 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
680 halfpages_number = 0;
681 } else {
682 if (retval != ERROR_OK)
683 return ERROR_FAIL;
684 }
685 }
686
687 /* write any remaining bytes */
688 uint32_t page_bytes_written = hp_nb * halfpages_number;
689 bytes_written += page_bytes_written;
690 address += page_bytes_written;
691 bytes_remaining = count - page_bytes_written;
692
693 retval = stm32lx_unlock_program_memory(bank);
694 if (retval != ERROR_OK)
695 return retval;
696
697 while (bytes_remaining > 0) {
698 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
699
700 /* copy remaining bytes into the write buffer */
701 uint32_t bytes_to_write = MIN(4, bytes_remaining);
702 memcpy(value, buffer + bytes_written, bytes_to_write);
703
704 retval = target_write_buffer(target, address, 4, value);
705 if (retval != ERROR_OK)
706 goto reset_pg_and_lock;
707
708 bytes_written += bytes_to_write;
709 bytes_remaining -= bytes_to_write;
710 address += 4;
711
712 retval = stm32lx_wait_until_bsy_clear(bank);
713 if (retval != ERROR_OK)
714 goto reset_pg_and_lock;
715 }
716
717 reset_pg_and_lock:
718 retval2 = stm32lx_lock_program_memory(bank);
719 if (retval == ERROR_OK)
720 retval = retval2;
721
722 return retval;
723 }
724
725 static int stm32lx_read_id_code(struct target *target, uint32_t *id)
726 {
727 struct armv7m_common *armv7m = target_to_armv7m(target);
728 int retval;
729 if (armv7m->arm.is_armv6m == true)
730 retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
731 else
732 /* read stm32 device id register */
733 retval = target_read_u32(target, DBGMCU_IDCODE, id);
734 return retval;
735 }
736
737 static int stm32lx_probe(struct flash_bank *bank)
738 {
739 struct target *target = bank->target;
740 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
741 int i;
742 uint16_t flash_size_in_kb;
743 uint32_t device_id;
744 uint32_t base_address = FLASH_BANK0_ADDRESS;
745 uint32_t second_bank_base;
746 unsigned int n;
747
748 stm32lx_info->probed = 0;
749
750 int retval = stm32lx_read_id_code(bank->target, &device_id);
751 if (retval != ERROR_OK)
752 return retval;
753
754 stm32lx_info->idcode = device_id;
755
756 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
757
758 for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
759 if ((device_id & 0xfff) == stm32lx_parts[n].id) {
760 stm32lx_info->part_info = stm32lx_parts[n];
761 break;
762 }
763 }
764
765 if (n == ARRAY_SIZE(stm32lx_parts)) {
766 LOG_WARNING("Cannot identify target as a STM32L family.");
767 return ERROR_FAIL;
768 } else {
769 LOG_INFO("Device: %s", stm32lx_info->part_info.device_str);
770 }
771
772 stm32lx_info->flash_base = stm32lx_info->part_info.flash_base;
773
774 /* Get the flash size from target. */
775 retval = target_read_u16(target, stm32lx_info->part_info.fsize_base,
776 &flash_size_in_kb);
777
778 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
779 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
780 * section 30.1.1. */
781 if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
782 if (flash_size_in_kb == 0)
783 flash_size_in_kb = 384;
784 else if (flash_size_in_kb == 1)
785 flash_size_in_kb = 256;
786 }
787
788 /* 0x429 devices only use the lowest 8 bits of the flash size register */
789 if (retval == ERROR_OK && (device_id & 0xfff) == 0x429) {
790 flash_size_in_kb &= 0xff;
791 }
792
793 /* Failed reading flash size or flash size invalid (early silicon),
794 * default to max target family */
795 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
796 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
797 stm32lx_info->part_info.max_flash_size_kb);
798 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
799 } else if (flash_size_in_kb > stm32lx_info->part_info.max_flash_size_kb) {
800 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
801 flash_size_in_kb, stm32lx_info->part_info.max_flash_size_kb,
802 stm32lx_info->part_info.max_flash_size_kb);
803 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
804 }
805
806 /* Overwrite default dual-bank configuration */
807 retval = stm32lx_update_part_info(bank, flash_size_in_kb);
808 if (retval != ERROR_OK)
809 return ERROR_FAIL;
810
811 if (stm32lx_info->part_info.has_dual_banks) {
812 /* Use the configured base address to determine if this is the first or second flash bank.
813 * Verify that the base address is reasonably correct and determine the flash bank size
814 */
815 second_bank_base = base_address +
816 stm32lx_info->part_info.first_bank_size_kb * 1024;
817 if (bank->base == second_bank_base || !bank->base) {
818 /* This is the second bank */
819 base_address = second_bank_base;
820 flash_size_in_kb = flash_size_in_kb -
821 stm32lx_info->part_info.first_bank_size_kb;
822 } else if (bank->base == base_address) {
823 /* This is the first bank */
824 flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
825 } else {
826 LOG_WARNING("STM32L flash bank base address config is incorrect."
827 " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
828 bank->base, base_address, second_bank_base);
829 return ERROR_FAIL;
830 }
831 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
832 bank->bank_number, flash_size_in_kb, base_address);
833 } else {
834 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
835 }
836
837 /* if the user sets the size manually then ignore the probed value
838 * this allows us to work around devices that have a invalid flash size register value */
839 if (stm32lx_info->user_bank_size) {
840 flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
841 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
842 }
843
844 /* calculate numbers of sectors (4kB per sector) */
845 int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
846
847 if (bank->sectors) {
848 free(bank->sectors);
849 bank->sectors = NULL;
850 }
851
852 bank->size = flash_size_in_kb * 1024;
853 bank->base = base_address;
854 bank->num_sectors = num_sectors;
855 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
856 if (bank->sectors == NULL) {
857 LOG_ERROR("failed to allocate bank sectors");
858 return ERROR_FAIL;
859 }
860
861 for (i = 0; i < num_sectors; i++) {
862 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
863 bank->sectors[i].size = FLASH_SECTOR_SIZE;
864 bank->sectors[i].is_erased = -1;
865 bank->sectors[i].is_protected = 1;
866 }
867
868 stm32lx_info->probed = 1;
869
870 return ERROR_OK;
871 }
872
873 static int stm32lx_auto_probe(struct flash_bank *bank)
874 {
875 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
876
877 if (stm32lx_info->probed)
878 return ERROR_OK;
879
880 return stm32lx_probe(bank);
881 }
882
883 /* This method must return a string displaying information about the bank */
884 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
885 {
886 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
887 const struct stm32lx_part_info *info = &stm32lx_info->part_info;
888 uint16_t rev_id = stm32lx_info->idcode >> 16;
889 const char *rev_str = NULL;
890
891 if (!stm32lx_info->probed) {
892 int retval = stm32lx_probe(bank);
893 if (retval != ERROR_OK) {
894 snprintf(buf, buf_size,
895 "Unable to find bank information.");
896 return retval;
897 }
898 }
899
900 for (unsigned int i = 0; i < info->num_revs; i++)
901 if (rev_id == info->revs[i].rev)
902 rev_str = info->revs[i].str;
903
904 if (rev_str != NULL) {
905 snprintf(buf, buf_size,
906 "%s - Rev: %s",
907 info->device_str, rev_str);
908 } else {
909 snprintf(buf, buf_size,
910 "%s - Rev: unknown (0x%04x)",
911 info->device_str, rev_id);
912 }
913
914 return ERROR_OK;
915 }
916
917 static const struct command_registration stm32lx_exec_command_handlers[] = {
918 {
919 .name = "mass_erase",
920 .handler = stm32lx_handle_mass_erase_command,
921 .mode = COMMAND_EXEC,
922 .usage = "bank_id",
923 .help = "Erase entire flash device. including available EEPROM",
924 },
925 {
926 .name = "lock",
927 .handler = stm32lx_handle_lock_command,
928 .mode = COMMAND_EXEC,
929 .usage = "bank_id",
930 .help = "Increase the readout protection to Level 1.",
931 },
932 {
933 .name = "unlock",
934 .handler = stm32lx_handle_unlock_command,
935 .mode = COMMAND_EXEC,
936 .usage = "bank_id",
937 .help = "Lower the readout protection from Level 1 to 0.",
938 },
939 COMMAND_REGISTRATION_DONE
940 };
941
942 static const struct command_registration stm32lx_command_handlers[] = {
943 {
944 .name = "stm32lx",
945 .mode = COMMAND_ANY,
946 .help = "stm32lx flash command group",
947 .usage = "",
948 .chain = stm32lx_exec_command_handlers,
949 },
950 COMMAND_REGISTRATION_DONE
951 };
952
953 struct flash_driver stm32lx_flash = {
954 .name = "stm32lx",
955 .commands = stm32lx_command_handlers,
956 .flash_bank_command = stm32lx_flash_bank_command,
957 .erase = stm32lx_erase,
958 .protect = stm32lx_protect,
959 .write = stm32lx_write,
960 .read = default_flash_read,
961 .probe = stm32lx_probe,
962 .auto_probe = stm32lx_auto_probe,
963 .erase_check = default_flash_blank_check,
964 .protect_check = stm32lx_protect_check,
965 .info = stm32lx_get_info,
966 .free_driver_priv = default_flash_free_driver_priv,
967 };
968
969 /* Static methods implementation */
970 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
971 {
972 struct target *target = bank->target;
973 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
974 int retval;
975 uint32_t reg32;
976
977 /*
978 * Unlocking the program memory is done by unlocking the PECR,
979 * then by writing the 2 PRGKEY to the PRGKEYR register
980 */
981
982 /* check flash is not already unlocked */
983 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
984 &reg32);
985 if (retval != ERROR_OK)
986 return retval;
987
988 if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
989 return ERROR_OK;
990
991 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
992 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
993 PEKEY1);
994 if (retval != ERROR_OK)
995 return retval;
996
997 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
998 PEKEY2);
999 if (retval != ERROR_OK)
1000 return retval;
1001
1002 /* Make sure it worked */
1003 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1004 &reg32);
1005 if (retval != ERROR_OK)
1006 return retval;
1007
1008 if (reg32 & FLASH_PECR__PELOCK) {
1009 LOG_ERROR("PELOCK is not cleared :(");
1010 return ERROR_FLASH_OPERATION_FAILED;
1011 }
1012
1013 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1014 PRGKEY1);
1015 if (retval != ERROR_OK)
1016 return retval;
1017 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1018 PRGKEY2);
1019 if (retval != ERROR_OK)
1020 return retval;
1021
1022 /* Make sure it worked */
1023 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1024 &reg32);
1025 if (retval != ERROR_OK)
1026 return retval;
1027
1028 if (reg32 & FLASH_PECR__PRGLOCK) {
1029 LOG_ERROR("PRGLOCK is not cleared :(");
1030 return ERROR_FLASH_OPERATION_FAILED;
1031 }
1032
1033 return ERROR_OK;
1034 }
1035
1036 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
1037 {
1038 struct target *target = bank->target;
1039 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1040 int retval;
1041 uint32_t reg32;
1042
1043 /**
1044 * Unlock the program memory, then set the FPRG bit in the PECR register.
1045 */
1046 retval = stm32lx_unlock_program_memory(bank);
1047 if (retval != ERROR_OK)
1048 return retval;
1049
1050 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1051 &reg32);
1052 if (retval != ERROR_OK)
1053 return retval;
1054
1055 reg32 |= FLASH_PECR__FPRG;
1056 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1057 reg32);
1058 if (retval != ERROR_OK)
1059 return retval;
1060
1061 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1062 &reg32);
1063 if (retval != ERROR_OK)
1064 return retval;
1065
1066 reg32 |= FLASH_PECR__PROG;
1067 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1068 reg32);
1069
1070 return retval;
1071 }
1072
1073 static int stm32lx_lock_program_memory(struct flash_bank *bank)
1074 {
1075 struct target *target = bank->target;
1076 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1077 int retval;
1078 uint32_t reg32;
1079
1080 /* To lock the program memory, simply set the lock bit and lock PECR */
1081
1082 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1083 &reg32);
1084 if (retval != ERROR_OK)
1085 return retval;
1086
1087 reg32 |= FLASH_PECR__PRGLOCK;
1088 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1089 reg32);
1090 if (retval != ERROR_OK)
1091 return retval;
1092
1093 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1094 &reg32);
1095 if (retval != ERROR_OK)
1096 return retval;
1097
1098 reg32 |= FLASH_PECR__PELOCK;
1099 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1100 reg32);
1101 if (retval != ERROR_OK)
1102 return retval;
1103
1104 return ERROR_OK;
1105 }
1106
1107 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
1108 {
1109 struct target *target = bank->target;
1110 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1111 int retval;
1112 uint32_t reg32;
1113
1114 /*
1115 * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1116 * first unlock the memory, loop over the pages of this sector
1117 * and write 0x0 to its first word.
1118 */
1119
1120 retval = stm32lx_unlock_program_memory(bank);
1121 if (retval != ERROR_OK)
1122 return retval;
1123
1124 for (int page = 0; page < (int)stm32lx_info->part_info.pages_per_sector;
1125 page++) {
1126 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
1127 retval = target_write_u32(target,
1128 stm32lx_info->flash_base + FLASH_PECR, reg32);
1129 if (retval != ERROR_OK)
1130 return retval;
1131
1132 retval = stm32lx_wait_until_bsy_clear(bank);
1133 if (retval != ERROR_OK)
1134 return retval;
1135
1136 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
1137 * stm32lx_info->part_info.page_size);
1138 retval = target_write_u32(target, addr, 0x0);
1139 if (retval != ERROR_OK)
1140 return retval;
1141
1142 retval = stm32lx_wait_until_bsy_clear(bank);
1143 if (retval != ERROR_OK)
1144 return retval;
1145 }
1146
1147 retval = stm32lx_lock_program_memory(bank);
1148 if (retval != ERROR_OK)
1149 return retval;
1150
1151 return ERROR_OK;
1152 }
1153
1154 static inline int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
1155 {
1156 struct target *target = bank->target;
1157 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1158
1159 return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
1160 }
1161
1162 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
1163 {
1164 return stm32lx_wait_until_bsy_clear_timeout(bank, 100);
1165 }
1166
1167 static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
1168 {
1169 struct target *target = bank->target;
1170 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1171 int retval;
1172 uint32_t reg32;
1173
1174 /*
1175 * Unlocking the options bytes is done by unlocking the PECR,
1176 * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1177 */
1178
1179 /* check flash is not already unlocked */
1180 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1181 if (retval != ERROR_OK)
1182 return retval;
1183
1184 if ((reg32 & FLASH_PECR__OPTLOCK) == 0)
1185 return ERROR_OK;
1186
1187 if ((reg32 & FLASH_PECR__PELOCK) != 0) {
1188
1189 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY1);
1190 if (retval != ERROR_OK)
1191 return retval;
1192
1193 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY2);
1194 if (retval != ERROR_OK)
1195 return retval;
1196 }
1197
1198 /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1199 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY1);
1200 if (retval != ERROR_OK)
1201 return retval;
1202
1203 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY2);
1204 if (retval != ERROR_OK)
1205 return retval;
1206
1207 return ERROR_OK;
1208 }
1209
1210 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
1211 {
1212 struct target *target = bank->target;
1213 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1214 uint32_t status;
1215 int retval = ERROR_OK;
1216
1217 /* wait for busy to clear */
1218 for (;;) {
1219 retval = stm32lx_get_flash_status(bank, &status);
1220 if (retval != ERROR_OK)
1221 return retval;
1222
1223 LOG_DEBUG("status: 0x%" PRIx32 "", status);
1224 if ((status & FLASH_SR__BSY) == 0)
1225 break;
1226
1227 if (timeout-- <= 0) {
1228 LOG_ERROR("timed out waiting for flash");
1229 return ERROR_FAIL;
1230 }
1231 alive_sleep(1);
1232 }
1233
1234 if (status & FLASH_SR__WRPERR) {
1235 LOG_ERROR("access denied / write protected");
1236 retval = ERROR_FAIL;
1237 }
1238
1239 if (status & FLASH_SR__PGAERR) {
1240 LOG_ERROR("invalid program address");
1241 retval = ERROR_FAIL;
1242 }
1243
1244 /* Clear but report errors */
1245 if (status & FLASH_SR__OPTVERR) {
1246 /* If this operation fails, we ignore it and report the original retval */
1247 target_write_u32(target, stm32lx_info->flash_base + FLASH_SR, status & FLASH_SR__OPTVERR);
1248 }
1249
1250 return retval;
1251 }
1252
1253 static int stm32lx_obl_launch(struct flash_bank *bank)
1254 {
1255 struct target *target = bank->target;
1256 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1257 int retval;
1258
1259 /* This will fail as the target gets immediately rebooted */
1260 target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1261 FLASH_PECR__OBL_LAUNCH);
1262
1263 size_t tries = 10;
1264 do {
1265 target_halt(target);
1266 retval = target_poll(target);
1267 } while (--tries > 0 &&
1268 (retval != ERROR_OK || target->state != TARGET_HALTED));
1269
1270 return tries ? ERROR_OK : ERROR_FAIL;
1271 }
1272
1273 static int stm32lx_lock(struct flash_bank *bank)
1274 {
1275 int retval;
1276 struct target *target = bank->target;
1277
1278 if (target->state != TARGET_HALTED) {
1279 LOG_ERROR("Target not halted");
1280 return ERROR_TARGET_NOT_HALTED;
1281 }
1282
1283 retval = stm32lx_unlock_options_bytes(bank);
1284 if (retval != ERROR_OK)
1285 return retval;
1286
1287 /* set the RDP protection level to 1 */
1288 retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
1289 if (retval != ERROR_OK)
1290 return retval;
1291
1292 return ERROR_OK;
1293 }
1294
1295 static int stm32lx_unlock(struct flash_bank *bank)
1296 {
1297 int retval;
1298 struct target *target = bank->target;
1299
1300 if (target->state != TARGET_HALTED) {
1301 LOG_ERROR("Target not halted");
1302 return ERROR_TARGET_NOT_HALTED;
1303 }
1304
1305 retval = stm32lx_unlock_options_bytes(bank);
1306 if (retval != ERROR_OK)
1307 return retval;
1308
1309 /* set the RDP protection level to 0 */
1310 retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
1311 if (retval != ERROR_OK)
1312 return retval;
1313
1314 retval = stm32lx_wait_until_bsy_clear_timeout(bank, 30000);
1315 if (retval != ERROR_OK)
1316 return retval;
1317
1318 return ERROR_OK;
1319 }
1320
1321 static int stm32lx_mass_erase(struct flash_bank *bank)
1322 {
1323 int retval;
1324 struct target *target = bank->target;
1325 struct stm32lx_flash_bank *stm32lx_info = NULL;
1326 uint32_t reg32;
1327
1328 if (target->state != TARGET_HALTED) {
1329 LOG_ERROR("Target not halted");
1330 return ERROR_TARGET_NOT_HALTED;
1331 }
1332
1333 stm32lx_info = bank->driver_priv;
1334
1335 retval = stm32lx_lock(bank);
1336 if (retval != ERROR_OK)
1337 return retval;
1338
1339 retval = stm32lx_obl_launch(bank);
1340 if (retval != ERROR_OK)
1341 return retval;
1342
1343 retval = stm32lx_unlock(bank);
1344 if (retval != ERROR_OK)
1345 return retval;
1346
1347 retval = stm32lx_obl_launch(bank);
1348 if (retval != ERROR_OK)
1349 return retval;
1350
1351 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1352 if (retval != ERROR_OK)
1353 return retval;
1354
1355 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, reg32 | FLASH_PECR__OPTLOCK);
1356 if (retval != ERROR_OK)
1357 return retval;
1358
1359 return ERROR_OK;
1360 }
1361
1362 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb)
1363 {
1364 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1365
1366 switch (stm32lx_info->part_info.id) {
1367 case 0x447: /* STM32L0xx (Cat.5) devices */
1368 if (flash_size_in_kb == 192 || flash_size_in_kb == 128) {
1369 stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1370 stm32lx_info->part_info.has_dual_banks = true;
1371 }
1372 break;
1373 case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
1374 stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1375 break;
1376 }
1377
1378 return ERROR_OK;
1379 }
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