src/target/armv4_5_cache.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef ARMV4_5_CACHE_H
  20 #define ARMV4_5_CACHE_H
  21
  22 struct command_context;
  23
  24 struct armv4_5_cachesize {
  25         int linelen;
  26         int associativity;
  27         int nsets;
  28         int cachesize;
  29 };
  30
  31 struct armv4_5_cache_common {
  32         int ctype;      /* specify supported cache operations */
  33         int separate;   /* separate caches or unified cache */
  34         struct armv4_5_cachesize d_u_size;      /* data cache */
  35         struct armv4_5_cachesize i_size; /* instruction cache */
  36         int i_cache_enabled;
  37         int d_u_cache_enabled;
  38 };
  39
  40 int armv4_5_identify_cache(uint32_t cache_type_reg,
  41                 struct armv4_5_cache_common *cache);
  42 int armv4_5_cache_state(uint32_t cp15_control_reg,
  43                 struct armv4_5_cache_common *cache);
  44
  45 int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
  46                 struct armv4_5_cache_common *armv4_5_cache);
  47
  48 enum {
  49         ARMV4_5_D_U_CACHE_ENABLED = 0x4,
  50         ARMV4_5_I_CACHE_ENABLED = 0x1000,
  51         ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
  52         ARMV4_5_CACHE_RR_BIT = 0x5000,
  53 };
  54
  55 #endif /* ARMV4_5_CACHE_H */