1 /***************************************************************************
2 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
18 /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
19 * specifically designed for SPI memories.
20 * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
21 * Two working modes are available:
22 * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
24 * - HW mode: the SPI but is under SMI control. Memory content is directly
25 * accessible in CPU memory space. CPU can read, write and execute memory
29 * To have flash memory mapped in CPU memory space, the SMI controller
30 * have to be in "HW mode". This requires following constraints:
31 * 1) The command "reset init" have to initialize SMI controller and put
33 * 2) every command in this file have to return to prompt in HW mode. */
41 #include <jtag/jtag.h>
42 #include <helper/time_support.h>
44 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
45 #define _SMI_READ_REG(a) \
50 __a = target_read_u32(target, io_base + (a), &__v); \
51 if (__a != ERROR_OK) \
56 #define SMI_WRITE_REG(a, v) \
60 __r = target_write_u32(target, io_base + (a), (v)); \
61 if (__r != ERROR_OK) \
65 #define SMI_POLL_TFF(timeout) \
69 __r = poll_tff(target, io_base, timeout); \
70 if (__r != ERROR_OK) \
74 #define SMI_SET_SW_MODE() SMI_WRITE_REG(SMI_CR1, \
75 SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
76 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
77 (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
78 #define SMI_SET_HW_MODE() SMI_WRITE_REG(SMI_CR1, \
79 SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
80 #define SMI_CLEAR_TFF() SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
82 #define SMI_BANK_SIZE (0x01000000)
84 #define SMI_CR1 (0x00) /* Control register 1 */
85 #define SMI_CR2 (0x04) /* Control register 2 */
86 #define SMI_SR (0x08) /* Status register */
87 #define SMI_TR (0x0c) /* TX */
88 #define SMI_RR (0x10) /* RX */
90 /* fields in SMI_CR1 */
91 #define SMI_SW_MODE 0x10000000 /* set to enable SW Mode */
92 #define SMI_WB_MODE 0x20000000 /* Write Burst Mode */
94 /* fields in SMI_CR2 */
95 #define SMI_TX_LEN_1 0x00000001 /* data length = 1 byte */
96 #define SMI_TX_LEN_4 0x00000004 /* data length = 4 byte */
97 #define SMI_RX_LEN_3 0x00000030 /* data length = 3 byte */
98 #define SMI_SEND 0x00000080 /* Send data */
99 #define SMI_RSR 0x00000400 /* reads status reg */
100 #define SMI_WE 0x00000800 /* Write Enable */
101 #define SMI_SEL_BANK0 0x00000000 /* Select Bank0 */
102 #define SMI_SEL_BANK1 0x00001000 /* Select Bank1 */
103 #define SMI_SEL_BANK2 0x00002000 /* Select Bank2 */
104 #define SMI_SEL_BANK3 0x00003000 /* Select Bank3 */
106 /* fields in SMI_SR */
107 #define SMI_TFF 0x00000100 /* Transfer Finished Flag */
110 #define SMI_READ_ID 0x0000009F /* Read Flash Identification */
113 #define SMI_CMD_TIMEOUT (100)
114 #define SMI_PROBE_TIMEOUT (100)
115 #define SMI_MAX_TIMEOUT (3000)
117 struct stmsmi_flash_bank
{
121 const struct flash_device
*dev
;
124 struct stmsmi_target
{
131 static const struct stmsmi_target target_devices
[] = {
132 /* name, tap_idcode, smi_base, io_base */
133 { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
134 { "STR75x", 0x4f1f0041, 0x80000000, 0x90000000 },
138 FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command
)
140 struct stmsmi_flash_bank
*stmsmi_info
;
142 LOG_DEBUG("%s", __func__
);
145 return ERROR_COMMAND_SYNTAX_ERROR
;
147 stmsmi_info
= malloc(sizeof(struct stmsmi_flash_bank
));
148 if (stmsmi_info
== NULL
) {
149 LOG_ERROR("not enough memory");
153 bank
->driver_priv
= stmsmi_info
;
154 stmsmi_info
->probed
= 0;
159 /* Poll transmit finished flag */
161 static int poll_tff(struct target
*target
, uint32_t io_base
, int timeout
)
165 if (SMI_READ_REG(SMI_SR
) & SMI_TFF
)
168 endtime
= timeval_ms() + timeout
;
171 if (SMI_READ_REG(SMI_SR
) & SMI_TFF
)
173 } while (timeval_ms() < endtime
);
175 LOG_ERROR("Timeout while polling TFF");
176 return ERROR_FLASH_OPERATION_FAILED
;
179 /* Read the status register of the external SPI flash chip.
180 * The operation is triggered by setting SMI_RSR bit.
181 * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
182 static int read_status_reg(struct flash_bank
*bank
, uint32_t *status
)
184 struct target
*target
= bank
->target
;
185 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
186 uint32_t io_base
= stmsmi_info
->io_base
;
188 /* clear transmit finished flag */
192 SMI_WRITE_REG(SMI_CR2
, stmsmi_info
->bank_num
| SMI_RSR
);
194 /* Poll transmit finished flag */
195 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
197 /* clear transmit finished flag */
200 *status
= SMI_READ_REG(SMI_SR
) & 0x0000ffff;
202 /* clean-up SMI_CR2 */
203 SMI_WRITE_REG(SMI_CR2
, 0); /* AB: Required ? */
208 /* check for WIP (write in progress) bit in status register */
210 static int wait_till_ready(struct flash_bank
*bank
, int timeout
)
216 endtime
= timeval_ms() + timeout
;
218 /* read flash status register */
219 retval
= read_status_reg(bank
, &status
);
220 if (retval
!= ERROR_OK
)
223 if ((status
& SPIFLASH_BSY_BIT
) == 0)
226 } while (timeval_ms() < endtime
);
228 LOG_ERROR("timeout");
232 /* Send "write enable" command to SPI flash chip.
233 * The operation is triggered by setting SMI_WE bit, and SMI sends
234 * the proper SPI command (0x06) */
235 static int smi_write_enable(struct flash_bank
*bank
)
237 struct target
*target
= bank
->target
;
238 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
239 uint32_t io_base
= stmsmi_info
->io_base
;
243 /* Enter in HW mode */
244 SMI_SET_HW_MODE(); /* AB: is this correct ?*/
246 /* clear transmit finished flag */
249 /* Send write enable command */
250 SMI_WRITE_REG(SMI_CR2
, stmsmi_info
->bank_num
| SMI_WE
);
252 /* Poll transmit finished flag */
253 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
255 /* read flash status register */
256 retval
= read_status_reg(bank
, &status
);
257 if (retval
!= ERROR_OK
)
260 /* Check write enabled */
261 if ((status
& SPIFLASH_WE_BIT
) == 0) {
262 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32
, status
);
269 static uint32_t erase_command(struct stmsmi_flash_bank
*stmsmi_info
,
277 cmd
.x
[0] = stmsmi_info
->dev
->erase_cmd
;
278 cmd
.x
[1] = offset
>> 16;
279 cmd
.x
[2] = offset
>> 8;
285 static int smi_erase_sector(struct flash_bank
*bank
, int sector
)
287 struct target
*target
= bank
->target
;
288 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
289 uint32_t io_base
= stmsmi_info
->io_base
;
293 retval
= smi_write_enable(bank
);
294 if (retval
!= ERROR_OK
)
297 /* Switch to SW mode to send sector erase command */
300 /* clear transmit finished flag */
303 /* send SPI command "block erase" */
304 cmd
= erase_command(stmsmi_info
, bank
->sectors
[sector
].offset
);
305 SMI_WRITE_REG(SMI_TR
, cmd
);
306 SMI_WRITE_REG(SMI_CR2
, stmsmi_info
->bank_num
| SMI_SEND
| SMI_TX_LEN_4
);
308 /* Poll transmit finished flag */
309 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
311 /* poll WIP for end of self timed Sector Erase cycle */
312 retval
= wait_till_ready(bank
, SMI_MAX_TIMEOUT
);
313 if (retval
!= ERROR_OK
)
319 static int stmsmi_erase(struct flash_bank
*bank
, int first
, int last
)
321 struct target
*target
= bank
->target
;
322 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
323 uint32_t io_base
= stmsmi_info
->io_base
;
324 int retval
= ERROR_OK
;
327 LOG_DEBUG("%s: from sector %d to sector %d", __func__
, first
, last
);
329 if (target
->state
!= TARGET_HALTED
) {
330 LOG_ERROR("Target not halted");
331 return ERROR_TARGET_NOT_HALTED
;
334 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
)) {
335 LOG_ERROR("Flash sector invalid");
336 return ERROR_FLASH_SECTOR_INVALID
;
339 if (!(stmsmi_info
->probed
)) {
340 LOG_ERROR("Flash bank not probed");
341 return ERROR_FLASH_BANK_NOT_PROBED
;
344 for (sector
= first
; sector
<= last
; sector
++) {
345 if (bank
->sectors
[sector
].is_protected
) {
346 LOG_ERROR("Flash sector %d protected", sector
);
351 for (sector
= first
; sector
<= last
; sector
++) {
352 retval
= smi_erase_sector(bank
, sector
);
353 if (retval
!= ERROR_OK
)
358 /* Switch to HW mode before return to prompt */
363 static int stmsmi_protect(struct flash_bank
*bank
, int set
,
368 for (sector
= first
; sector
<= last
; sector
++)
369 bank
->sectors
[sector
].is_protected
= set
;
373 static int smi_write_buffer(struct flash_bank
*bank
, const uint8_t *buffer
,
374 uint32_t address
, uint32_t len
)
376 struct target
*target
= bank
->target
;
377 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
378 uint32_t io_base
= stmsmi_info
->io_base
;
381 LOG_DEBUG("%s: address=0x%08" PRIx32
" len=0x%08" PRIx32
,
382 __func__
, address
, len
);
384 retval
= smi_write_enable(bank
);
385 if (retval
!= ERROR_OK
)
388 /* HW mode, write burst mode */
391 retval
= target_write_buffer(target
, address
, len
, buffer
);
392 if (retval
!= ERROR_OK
)
398 static int stmsmi_write(struct flash_bank
*bank
, const uint8_t *buffer
,
399 uint32_t offset
, uint32_t count
)
401 struct target
*target
= bank
->target
;
402 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
403 uint32_t io_base
= stmsmi_info
->io_base
;
404 uint32_t cur_count
, page_size
, page_offset
;
406 int retval
= ERROR_OK
;
408 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
409 __func__
, offset
, count
);
411 if (target
->state
!= TARGET_HALTED
) {
412 LOG_ERROR("Target not halted");
413 return ERROR_TARGET_NOT_HALTED
;
416 if (offset
+ count
> stmsmi_info
->dev
->size_in_bytes
) {
417 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
418 count
= stmsmi_info
->dev
->size_in_bytes
- offset
;
421 /* Check sector protection */
422 for (sector
= 0; sector
< bank
->num_sectors
; sector
++) {
423 /* Start offset in or before this sector? */
424 /* End offset in or behind this sector? */
426 (bank
->sectors
[sector
].offset
+ bank
->sectors
[sector
].size
))
427 && ((offset
+ count
- 1) >= bank
->sectors
[sector
].offset
)
428 && bank
->sectors
[sector
].is_protected
) {
429 LOG_ERROR("Flash sector %d protected", sector
);
434 page_size
= stmsmi_info
->dev
->pagesize
;
436 /* unaligned buffer head */
437 if (count
> 0 && (offset
& 3) != 0) {
438 cur_count
= 4 - (offset
& 3);
439 if (cur_count
> count
)
441 retval
= smi_write_buffer(bank
, buffer
, bank
->base
+ offset
,
443 if (retval
!= ERROR_OK
)
450 page_offset
= offset
% page_size
;
451 /* central part, aligned words */
453 /* clip block at page boundary */
454 if (page_offset
+ count
> page_size
)
455 cur_count
= page_size
- page_offset
;
457 cur_count
= count
& ~3;
459 retval
= smi_write_buffer(bank
, buffer
, bank
->base
+ offset
,
461 if (retval
!= ERROR_OK
)
474 retval
= smi_write_buffer(bank
, buffer
, bank
->base
+ offset
, count
);
477 /* Switch to HW mode before return to prompt */
482 /* Return ID of flash device */
483 /* On exit, SW mode is kept */
484 static int read_flash_id(struct flash_bank
*bank
, uint32_t *id
)
486 struct target
*target
= bank
->target
;
487 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
488 uint32_t io_base
= stmsmi_info
->io_base
;
491 if (target
->state
!= TARGET_HALTED
) {
492 LOG_ERROR("Target not halted");
493 return ERROR_TARGET_NOT_HALTED
;
497 retval
= wait_till_ready(bank
, SMI_PROBE_TIMEOUT
);
498 if (retval
!= ERROR_OK
)
501 /* enter in SW mode */
504 /* clear transmit finished flag */
507 /* Send SPI command "read ID" */
508 SMI_WRITE_REG(SMI_TR
, SMI_READ_ID
);
509 SMI_WRITE_REG(SMI_CR2
,
510 stmsmi_info
->bank_num
| SMI_SEND
| SMI_RX_LEN_3
| SMI_TX_LEN_1
);
512 /* Poll transmit finished flag */
513 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
515 /* clear transmit finished flag */
518 /* read ID from Receive Register */
519 *id
= SMI_READ_REG(SMI_RR
) & 0x00ffffff;
523 static int stmsmi_probe(struct flash_bank
*bank
)
525 struct target
*target
= bank
->target
;
526 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
528 struct flash_sector
*sectors
;
529 uint32_t id
= 0; /* silence uninitialized warning */
530 const struct stmsmi_target
*target_device
;
533 if (stmsmi_info
->probed
)
535 stmsmi_info
->probed
= 0;
537 for (target_device
= target_devices
; target_device
->name
; ++target_device
)
538 if (target_device
->tap_idcode
== target
->tap
->idcode
)
540 if (!target_device
->name
) {
541 LOG_ERROR("Device ID 0x%" PRIx32
" is not known as SMI capable",
542 target
->tap
->idcode
);
546 switch (bank
->base
- target_device
->smi_base
) {
548 stmsmi_info
->bank_num
= SMI_SEL_BANK0
;
551 stmsmi_info
->bank_num
= SMI_SEL_BANK1
;
553 case 2*SMI_BANK_SIZE
:
554 stmsmi_info
->bank_num
= SMI_SEL_BANK2
;
556 case 3*SMI_BANK_SIZE
:
557 stmsmi_info
->bank_num
= SMI_SEL_BANK3
;
560 LOG_ERROR("Invalid SMI base address 0x%" PRIx32
, bank
->base
);
563 io_base
= target_device
->io_base
;
564 stmsmi_info
->io_base
= io_base
;
566 LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32
,
567 target_device
->name
, bank
->base
);
569 /* read and decode flash ID; returns in SW mode */
570 retval
= read_flash_id(bank
, &id
);
572 if (retval
!= ERROR_OK
)
575 stmsmi_info
->dev
= NULL
;
576 for (const struct flash_device
*p
= flash_devices
; p
->name
; p
++)
577 if (p
->device_id
== id
) {
578 stmsmi_info
->dev
= p
;
582 if (!stmsmi_info
->dev
) {
583 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32
")", id
);
587 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32
")",
588 stmsmi_info
->dev
->name
, stmsmi_info
->dev
->device_id
);
590 /* Set correct size value */
591 bank
->size
= stmsmi_info
->dev
->size_in_bytes
;
593 /* create and fill sectors array */
595 stmsmi_info
->dev
->size_in_bytes
/ stmsmi_info
->dev
->sectorsize
;
596 sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
597 if (sectors
== NULL
) {
598 LOG_ERROR("not enough memory");
602 for (int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
603 sectors
[sector
].offset
= sector
* stmsmi_info
->dev
->sectorsize
;
604 sectors
[sector
].size
= stmsmi_info
->dev
->sectorsize
;
605 sectors
[sector
].is_erased
= -1;
606 sectors
[sector
].is_protected
= 1;
609 bank
->sectors
= sectors
;
610 stmsmi_info
->probed
= 1;
614 static int stmsmi_auto_probe(struct flash_bank
*bank
)
616 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
617 if (stmsmi_info
->probed
)
619 return stmsmi_probe(bank
);
622 static int stmsmi_protect_check(struct flash_bank
*bank
)
624 /* Nothing to do. Protection is only handled in SW. */
628 static int get_stmsmi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
630 struct stmsmi_flash_bank
*stmsmi_info
= bank
->driver_priv
;
632 if (!(stmsmi_info
->probed
)) {
633 snprintf(buf
, buf_size
,
634 "\nSMI flash bank not probed yet\n");
638 snprintf(buf
, buf_size
, "\nSMI flash information:\n"
639 " Device \'%s\' (ID 0x%08" PRIx32
")\n",
640 stmsmi_info
->dev
->name
, stmsmi_info
->dev
->device_id
);
645 struct flash_driver stmsmi_flash
= {
647 .flash_bank_command
= stmsmi_flash_bank_command
,
648 .erase
= stmsmi_erase
,
649 .protect
= stmsmi_protect
,
650 .write
= stmsmi_write
,
651 .read
= default_flash_read
,
652 .probe
= stmsmi_probe
,
653 .auto_probe
= stmsmi_auto_probe
,
654 .erase_check
= default_flash_blank_check
,
655 .protect_check
= stmsmi_protect_check
,
656 .info
= get_stmsmi_info
,