src/flash/nand/core.h

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de>              *
   3  *   Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net>             *
   4  *                                                                         *
   5  *   Partially based on linux/include/linux/mtd/nand.h                     *
   6  *   Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com>                   *
   7  *   Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com>         *
   8  *   Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de>               *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  22  ***************************************************************************/
  23
  24 #ifndef FLASH_NAND_CORE_H
  25 #define FLASH_NAND_CORE_H
  26
  27 #include <flash/common.h>
  28
  29 /**
  30  * Representation of a single NAND block in a NAND device.
  31  */
  32 struct nand_block {
  33         /** Offset to the block. */
  34         uint32_t offset;
  35
  36         /** Size of the block. */
  37         uint32_t size;
  38
  39         /** True if the block has been erased. */
  40         int is_erased;
  41
  42         /** True if the block is bad. */
  43         int is_bad;
  44 };
  45
  46 struct nand_oobfree {
  47         int offset;
  48         int length;
  49 };
  50
  51 struct nand_ecclayout {
  52         int eccbytes;
  53         int eccpos[64];
  54         int oobavail;
  55         struct nand_oobfree oobfree[2];
  56 };
  57
  58 struct nand_device {
  59         const char *name;
  60         struct target *target;
  61         struct nand_flash_controller *controller;
  62         void *controller_priv;
  63         struct nand_manufacturer *manufacturer;
  64         struct nand_info *device;
  65         int bus_width;
  66         int address_cycles;
  67         int page_size;
  68         int erase_size;
  69         bool use_raw;
  70         int num_blocks;
  71         struct nand_block *blocks;
  72         struct nand_device *next;
  73 };
  74
  75 /* NAND Flash Manufacturer ID Codes
  76  */
  77 enum {
  78         NAND_MFR_TOSHIBA = 0x98,
  79         NAND_MFR_SAMSUNG = 0xec,
  80         NAND_MFR_FUJITSU = 0x04,
  81         NAND_MFR_NATIONAL = 0x8f,
  82         NAND_MFR_RENESAS = 0x07,
  83         NAND_MFR_STMICRO = 0x20,
  84         NAND_MFR_HYNIX = 0xad,
  85         NAND_MFR_MICRON = 0x2c,
  86 };
  87
  88 struct nand_manufacturer {
  89         int id;
  90         const char *name;
  91 };
  92
  93 struct nand_info {
  94         int mfr_id;
  95         int id;
  96         int page_size;
  97         int chip_size;
  98         int erase_size;
  99         int options;
 100         const char *name;
 101 };
 102
 103 /* Option constants for bizarre disfunctionality and real features
 104  */
 105 enum {
 106         /* Chip can not auto increment pages */
 107         NAND_NO_AUTOINCR = 0x00000001,
 108
 109         /* Buswitdh is 16 bit */
 110         NAND_BUSWIDTH_16 = 0x00000002,
 111
 112         /* Device supports partial programming without padding */
 113         NAND_NO_PADDING = 0x00000004,
 114
 115         /* Chip has cache program function */
 116         NAND_CACHEPRG = 0x00000008,
 117
 118         /* Chip has copy back function */
 119         NAND_COPYBACK = 0x00000010,
 120
 121         /* AND Chip which has 4 banks and a confusing page / block
 122          * assignment. See Renesas datasheet for further information */
 123         NAND_IS_AND = 0x00000020,
 124
 125         /* Chip has a array of 4 pages which can be read without
 126          * additional ready /busy waits */
 127         NAND_4PAGE_ARRAY = 0x00000040,
 128
 129         /* Chip requires that BBT is periodically rewritten to prevent
 130          * bits from adjacent blocks from 'leaking' in altering data.
 131          * This happens with the Renesas AG-AND chips, possibly others.  */
 132         BBT_AUTO_REFRESH = 0x00000080,
 133
 134         /* Chip does not require ready check on read. True
 135          * for all large page devices, as they do not support
 136          * autoincrement.*/
 137         NAND_NO_READRDY = 0x00000100,
 138
 139         /* Options valid for Samsung large page devices */
 140         NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
 141
 142         /* Options for new chips with large page size. The pagesize and the
 143          * erasesize is determined from the extended id bytes
 144          */
 145         LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
 146         LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
 147 };
 148
 149 enum {
 150         /* Standard NAND flash commands */
 151         NAND_CMD_READ0 = 0x0,
 152         NAND_CMD_READ1 = 0x1,
 153         NAND_CMD_RNDOUT = 0x5,
 154         NAND_CMD_PAGEPROG = 0x10,
 155         NAND_CMD_READOOB = 0x50,
 156         NAND_CMD_ERASE1 = 0x60,
 157         NAND_CMD_STATUS = 0x70,
 158         NAND_CMD_STATUS_MULTI = 0x71,
 159         NAND_CMD_SEQIN = 0x80,
 160         NAND_CMD_RNDIN = 0x85,
 161         NAND_CMD_READID = 0x90,
 162         NAND_CMD_ERASE2 = 0xd0,
 163         NAND_CMD_RESET = 0xff,
 164
 165         /* Extended commands for large page devices */
 166         NAND_CMD_READSTART = 0x30,
 167         NAND_CMD_RNDOUTSTART = 0xE0,
 168         NAND_CMD_CACHEDPROG = 0x15,
 169 };
 170
 171 /* Status bits */
 172 enum {
 173         NAND_STATUS_FAIL = 0x01,
 174         NAND_STATUS_FAIL_N1 = 0x02,
 175         NAND_STATUS_TRUE_READY = 0x20,
 176         NAND_STATUS_READY = 0x40,
 177         NAND_STATUS_WP = 0x80,
 178 };
 179
 180 /* OOB (spare) data formats */
 181 enum oob_formats {
 182         NAND_OOB_NONE = 0x0,    /* no OOB data at all */
 183         NAND_OOB_RAW = 0x1,             /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for
 184                                          *2048b page sizes) */
 185         NAND_OOB_ONLY = 0x2,    /* only OOB data */
 186         NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
 187         NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
 188         NAND_OOB_SW_ECC_KW = 0x40,      /* when writing, use Marvell's Kirkwood bootrom format */
 189         NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
 190         NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
 191 };
 192
 193
 194 struct nand_device *get_nand_device_by_num(int num);
 195
 196 int nand_page_command(struct nand_device *nand, uint32_t page,
 197                       uint8_t cmd, bool oob_only);
 198
 199 int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size);
 200 int nand_write_data_page(struct nand_device *nand,
 201                          uint8_t *data, uint32_t size);
 202
 203 int nand_write_finish(struct nand_device *nand);
 204
 205 int nand_read_page_raw(struct nand_device *nand, uint32_t page,
 206                        uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
 207 int nand_write_page_raw(struct nand_device *nand, uint32_t page,
 208                         uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
 209
 210 int nand_read_status(struct nand_device *nand, uint8_t *status);
 211
 212 int nand_calculate_ecc(struct nand_device *nand,
 213                        const uint8_t *dat, uint8_t *ecc_code);
 214 int nand_calculate_ecc_kw(struct nand_device *nand,
 215                           const uint8_t *dat, uint8_t *ecc_code);
 216
 217 int nand_register_commands(struct command_context *cmd_ctx);
 218
 219 /** helper for parsing a nand device command argument string */
 220 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
 221         struct nand_device **nand);
 222
 223
 224 #define         ERROR_NAND_DEVICE_INVALID               (-1100)
 225 #define         ERROR_NAND_OPERATION_FAILED             (-1101)
 226 #define         ERROR_NAND_OPERATION_TIMEOUT    (-1102)
 227 #define         ERROR_NAND_OPERATION_NOT_SUPPORTED      (-1103)
 228 #define         ERROR_NAND_DEVICE_NOT_PROBED    (-1104)
 229 #define         ERROR_NAND_ERROR_CORRECTION_FAILED      (-1105)
 230 #define         ERROR_NAND_NO_BUFFER                    (-1106)
 231
 232 #endif  /* FLASH_NAND_CORE_H */