src/target/arm11.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "target.h"
  27 #include "register.h"
  28 #include "jtag.h"
  29
  30 #define asizeof(x)      (sizeof(x) / sizeof((x)[0]))
  31
  32 #define NEW(type, variable, items)                      \
  33         type * variable = calloc(1, sizeof(type) * items)
  34
  35 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
  36
  37 #ifndef __MSVCRT__
  38 #define ZU              "%zu"
  39 #else
  40 #define ZU              "%Iu"
  41 #endif
  42
  43 #define ARM11_REGCACHE_MODEREGS         0
  44 #define ARM11_REGCACHE_FREGS            0
  45
  46 #define ARM11_REGCACHE_COUNT            (20 +                                   \
  47                                          23 * ARM11_REGCACHE_MODEREGS +                 \
  48                                           9 * ARM11_REGCACHE_FREGS)
  49
  50 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  51
  52
  53 #define CHECK_RETVAL(action)                                                            \
  54 do {                                                                                                            \
  55         int __retval = (action);                                                                \
  56                                                                                                                         \
  57         if (__retval != ERROR_OK)                                                               \
  58         {                                                                                                               \
  59                 LOG_DEBUG("error while calling \"" # action "\"");      \
  60                 return __retval;                                                                        \
  61         }                                                                                                               \
  62                                                                                                                         \
  63 } while (0)
  64
  65
  66 typedef struct arm11_register_history_s
  67 {
  68         uint32_t                value;
  69         uint8_t         valid;
  70 }arm11_register_history_t;
  71
  72 enum arm11_debug_version
  73 {
  74         ARM11_DEBUG_V6                  = 0x01,
  75         ARM11_DEBUG_V61                 = 0x02,
  76         ARM11_DEBUG_V7                  = 0x03,
  77         ARM11_DEBUG_V7_CP14             = 0x04,
  78 };
  79
  80 typedef struct arm11_common_s
  81 {
  82         target_t *      target;         /**< Reference back to the owner */
  83
  84         /** \name Processor type detection */
  85         /*@{*/
  86
  87         uint32_t                device_id;              /**< IDCODE readout                             */
  88         uint32_t                didr;                   /**< DIDR readout (debug capabilities)  */
  89         uint8_t         implementor;    /**< DIDR Implementor readout           */
  90
  91         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  92         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  93
  94         enum arm11_debug_version
  95                 debug_version;          /**< ARM debug architecture from DIDR   */
  96         /*@}*/
  97
  98         uint32_t                last_dscr;              /**< Last retrieved DSCR value;
  99                                                              Use only for debug message generation              */
 100
 101         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
 102
 103         /** \name Shadow registers to save processor state */
 104         /*@{*/
 105
 106         reg_t * reg_list;                                                       /**< target register list */
 107         uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
 108
 109         /*@}*/
 110
 111         arm11_register_history_t
 112                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
 113
 114         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
 115         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
 116
 117         // GA
 118         reg_cache_t *core_cache;
 119 } arm11_common_t;
 120
 121
 122 /**
 123  * ARM11 DBGTAP instructions
 124  *
 125  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 126  */
 127 enum arm11_instructions
 128 {
 129         ARM11_EXTEST    = 0x00,
 130         ARM11_SCAN_N    = 0x02,
 131         ARM11_RESTART   = 0x04,
 132         ARM11_HALT          = 0x08,
 133         ARM11_INTEST    = 0x0C,
 134         ARM11_ITRSEL    = 0x1D,
 135         ARM11_IDCODE    = 0x1E,
 136         ARM11_BYPASS    = 0x1F,
 137 };
 138
 139 enum arm11_dscr
 140 {
 141         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 142         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 143
 144         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 145         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 146         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 147         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 148         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 149         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 150         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 151
 152         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 153         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 154         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 155         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 156         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 157         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 158         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 159 };
 160
 161 enum arm11_cpsr
 162 {
 163         ARM11_CPSR_T                            = 1 << 5,
 164         ARM11_CPSR_J                            = 1 << 24,
 165 };
 166
 167 enum arm11_sc7
 168 {
 169         ARM11_SC7_NULL                          = 0,
 170         ARM11_SC7_VCR                           = 7,
 171         ARM11_SC7_PC                            = 8,
 172         ARM11_SC7_BVR0                          = 64,
 173         ARM11_SC7_BCR0                          = 80,
 174         ARM11_SC7_WVR0                          = 96,
 175         ARM11_SC7_WCR0                          = 112,
 176 };
 177
 178 typedef struct arm11_reg_state_s
 179 {
 180         uint32_t                                def_index;
 181         target_t *                      target;
 182 } arm11_reg_state_t;
 183
 184 /* poll current target status */
 185 int arm11_poll(struct target_s *target);
 186 /* architecture specific status reply */
 187 int arm11_arch_state(struct target_s *target);
 188
 189 /* target request support */
 190 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer);
 191
 192 /* target execution control */
 193 int arm11_halt(struct target_s *target);
 194 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
 195 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
 196 int arm11_examine(struct target_s *target);
 197
 198 /* target reset control */
 199 int arm11_assert_reset(struct target_s *target);
 200 int arm11_deassert_reset(struct target_s *target);
 201 int arm11_soft_reset_halt(struct target_s *target);
 202
 203 /* target register access for gdb */
 204 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
 205
 206 /* target memory access
 207 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 208 * count: number of items of <size>
 209 */
 210 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 211 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 212
 213 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
 214 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer);
 215
 216 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
 217
 218 /* target break-/watchpoint control
 219 * rw: 0 = write, 1 = read, 2 = access
 220 */
 221 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 222 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 223 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 224 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 225
 226 /* target algorithm support */
 227 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
 228
 229 int arm11_register_commands(struct command_context_s *cmd_ctx);
 230 int arm11_target_create(struct target_s *target, Jim_Interp *interp);
 231 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 232 int arm11_quit(void);
 233
 234 /* helpers */
 235 int arm11_build_reg_cache(target_t *target);
 236 int arm11_set_reg(reg_t *reg, uint8_t *buf);
 237 int arm11_get_reg(reg_t *reg);
 238
 239 void arm11_record_register_history(arm11_common_t * arm11);
 240 void arm11_dump_reg_changes(arm11_common_t * arm11);
 241
 242 /* internals */
 243
 244 void arm11_setup_field                  (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
 245 void arm11_add_IR                               (arm11_common_t * arm11, uint8_t instr, tap_state_t state);
 246 int arm11_add_debug_SCAN_N              (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
 247 void arm11_add_debug_INST               (arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state);
 248 int arm11_read_DSCR                             (arm11_common_t * arm11, uint32_t *dscr);
 249 int arm11_write_DSCR                    (arm11_common_t * arm11, uint32_t dscr);
 250
 251 enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
 252
 253 int arm11_run_instr_data_prepare                        (arm11_common_t * arm11);
 254 int arm11_run_instr_data_finish                         (arm11_common_t * arm11);
 255 int arm11_run_instr_no_data                                     (arm11_common_t * arm11, uint32_t * opcode, size_t count);
 256 int arm11_run_instr_no_data1                            (arm11_common_t * arm11, uint32_t opcode);
 257 int arm11_run_instr_data_to_core                        (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
 258 int arm11_run_instr_data_to_core_noack          (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
 259 int arm11_run_instr_data_to_core1                       (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
 260 int arm11_run_instr_data_from_core                      (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
 261 int arm11_run_instr_data_from_core_via_r0       (arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
 262 int arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
 263
 264 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
 265 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
 266
 267 /** Used to make a list of read/write commands for scan chain 7
 268  *
 269  *  Use with arm11_sc7_run()
 270  */
 271 typedef struct arm11_sc7_action_s
 272 {
 273         bool    write;                          /**< Access mode: true for write, false for read.       */
 274         uint8_t         address;                        /**< Register address mode. Use enum #arm11_sc7         */
 275         uint32_t                value;                          /**< If write then set this to value to be written.
 276                                                                          In read mode this receives the read value when the
 277                                                                          function returns.                                      */
 278 } arm11_sc7_action_t;
 279
 280 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
 281
 282 /* Mid-level helper functions */
 283 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
 284 void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value);
 285
 286 int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result);
 287
 288 #endif /* ARM11_H */