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- added autoprobe functionality
[openocd.git] / src / flash / stm32x.c
blobe87e0cceba8b95068ae5354687683c6d77a733d0
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "stm32x.h"
27 #include "flash.h"
28 #include "target.h"
29 #include "log.h"
30 #include "armv7m.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
33
34 #include <stdlib.h>
35 #include <string.h>
36
37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
42 int stm32x_probe(struct flash_bank_s *bank);
43 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int stm32x_protect_check(struct flash_bank_s *bank);
45 int stm32x_erase_check(struct flash_bank_s *bank);
46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
47
48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 flash_driver_t stm32x_flash =
55 {
56 .name = "stm32x",
57 .register_commands = stm32x_register_commands,
58 .flash_bank_command = stm32x_flash_bank_command,
59 .erase = stm32x_erase,
60 .protect = stm32x_protect,
61 .write = stm32x_write,
62 .probe = stm32x_probe,
63 .auto_probe = stm32x_probe,
64 .erase_check = stm32x_erase_check,
65 .protect_check = stm32x_protect_check,
66 .info = stm32x_info
67 };
68
69 int stm32x_register_commands(struct command_context_s *cmd_ctx)
70 {
71 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
72
73 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
74 "lock device");
75 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
76 "unlock protected device");
77 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
78 "mass erase device");
79 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
80 "read device option bytes");
81 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
82 "write device option bytes");
83 return ERROR_OK;
84 }
85
86 int stm32x_build_block_list(struct flash_bank_s *bank)
87 {
88 int i;
89 int num_sectors = 0;
90
91 switch (bank->size)
92 {
93 case 32 * 1024:
94 num_sectors = 32;
95 break;
96 case 64 * 1024:
97 num_sectors = 64;
98 break;
99 case 128 * 1024:
100 num_sectors = 128;
101 break;
102 default:
103 ERROR("BUG: unknown bank->size encountered");
104 exit(-1);
105 }
106
107 bank->num_sectors = num_sectors;
108 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
109
110 for (i = 0; i < num_sectors; i++)
111 {
112 bank->sectors[i].offset = i * 1024;
113 bank->sectors[i].size = 1024;
114 bank->sectors[i].is_erased = -1;
115 bank->sectors[i].is_protected = 1;
116 }
117
118 return ERROR_OK;
119 }
120
121 /* flash bank stm32x <base> <size> 0 0 <target#>
122 */
123 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
124 {
125 stm32x_flash_bank_t *stm32x_info;
126
127 if (argc < 6)
128 {
129 WARNING("incomplete flash_bank stm32x configuration");
130 return ERROR_FLASH_BANK_INVALID;
131 }
132
133 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
134 bank->driver_priv = stm32x_info;
135
136 if (bank->base != 0x08000000)
137 {
138 WARNING("overriding flash base address for STM32x device with 0x08000000");
139 bank->base = 0x08000000;
140 }
141
142 stm32x_build_block_list(bank);
143
144 stm32x_info->write_algorithm = NULL;
145
146 return ERROR_OK;
147 }
148
149 u32 stm32x_get_flash_status(flash_bank_t *bank)
150 {
151 target_t *target = bank->target;
152 u32 status;
153
154 target_read_u32(target, STM32_FLASH_SR, &status);
155
156 return status;
157 }
158
159 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
160 {
161 u32 status;
162
163 /* wait for busy to clear */
164 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
165 {
166 DEBUG("status: 0x%x", status);
167 usleep(1000);
168 }
169
170 return status;
171 }
172
173 int stm32x_read_options(struct flash_bank_s *bank)
174 {
175 u32 optiondata;
176 stm32x_flash_bank_t *stm32x_info = NULL;
177 target_t *target = bank->target;
178
179 stm32x_info = bank->driver_priv;
180
181 /* read current option bytes */
182 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
183
184 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
185 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
186
187 if (optiondata & (1 << OPT_READOUT))
188 INFO("Device Security Bit Set");
189
190 /* each bit refers to a 4bank protection */
191 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
192
193 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
194 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
195 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
196 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
197
198 return ERROR_OK;
199 }
200
201 int stm32x_erase_options(struct flash_bank_s *bank)
202 {
203 stm32x_flash_bank_t *stm32x_info = NULL;
204 target_t *target = bank->target;
205 u32 status;
206
207 stm32x_info = bank->driver_priv;
208
209 /* read current options */
210 stm32x_read_options(bank);
211
212 /* unlock flash registers */
213 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
214 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
215
216 /* unlock option flash registers */
217 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
218 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
219
220 /* erase option bytes */
221 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
222 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
223
224 status = stm32x_wait_status_busy(bank, 10);
225
226 if( status & FLASH_WRPRTERR )
227 return ERROR_FLASH_OPERATION_FAILED;
228 if( status & FLASH_PGERR )
229 return ERROR_FLASH_OPERATION_FAILED;
230
231 /* clear readout protection and complementary option bytes
232 * this will also force a device unlock if set */
233 stm32x_info->option_bytes.RDP = 0x5AA5;
234
235 return ERROR_OK;
236 }
237
238 int stm32x_write_options(struct flash_bank_s *bank)
239 {
240 stm32x_flash_bank_t *stm32x_info = NULL;
241 target_t *target = bank->target;
242 u32 status;
243
244 stm32x_info = bank->driver_priv;
245
246 /* unlock flash registers */
247 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
248 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
249
250 /* unlock option flash registers */
251 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
252 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
253
254 /* program option bytes */
255 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
256
257 /* write user option byte */
258 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
259
260 status = stm32x_wait_status_busy(bank, 10);
261
262 if( status & FLASH_WRPRTERR )
263 return ERROR_FLASH_OPERATION_FAILED;
264 if( status & FLASH_PGERR )
265 return ERROR_FLASH_OPERATION_FAILED;
266
267 /* write protection byte 1 */
268 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
269
270 status = stm32x_wait_status_busy(bank, 10);
271
272 if( status & FLASH_WRPRTERR )
273 return ERROR_FLASH_OPERATION_FAILED;
274 if( status & FLASH_PGERR )
275 return ERROR_FLASH_OPERATION_FAILED;
276
277 /* write protection byte 2 */
278 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
279
280 status = stm32x_wait_status_busy(bank, 10);
281
282 if( status & FLASH_WRPRTERR )
283 return ERROR_FLASH_OPERATION_FAILED;
284 if( status & FLASH_PGERR )
285 return ERROR_FLASH_OPERATION_FAILED;
286
287 /* write protection byte 3 */
288 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
289
290 status = stm32x_wait_status_busy(bank, 10);
291
292 if( status & FLASH_WRPRTERR )
293 return ERROR_FLASH_OPERATION_FAILED;
294 if( status & FLASH_PGERR )
295 return ERROR_FLASH_OPERATION_FAILED;
296
297 /* write protection byte 4 */
298 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
299
300 status = stm32x_wait_status_busy(bank, 10);
301
302 if( status & FLASH_WRPRTERR )
303 return ERROR_FLASH_OPERATION_FAILED;
304 if( status & FLASH_PGERR )
305 return ERROR_FLASH_OPERATION_FAILED;
306
307 /* write readout protection bit */
308 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
309
310 status = stm32x_wait_status_busy(bank, 10);
311
312 if( status & FLASH_WRPRTERR )
313 return ERROR_FLASH_OPERATION_FAILED;
314 if( status & FLASH_PGERR )
315 return ERROR_FLASH_OPERATION_FAILED;
316
317 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
318
319 return ERROR_OK;
320 }
321
322 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
323 {
324 target_t *target = bank->target;
325 u8 *buffer;
326 int i;
327 int nBytes;
328
329 if ((first < 0) || (last > bank->num_sectors))
330 return ERROR_FLASH_SECTOR_INVALID;
331
332 if (target->state != TARGET_HALTED)
333 {
334 return ERROR_TARGET_NOT_HALTED;
335 }
336
337 buffer = malloc(256);
338
339 for (i = first; i <= last; i++)
340 {
341 bank->sectors[i].is_erased = 1;
342
343 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
344
345 for (nBytes = 0; nBytes < 256; nBytes++)
346 {
347 if (buffer[nBytes] != 0xFF)
348 {
349 bank->sectors[i].is_erased = 0;
350 break;
351 }
352 }
353 }
354
355 free(buffer);
356
357 return ERROR_OK;
358 }
359
360 int stm32x_protect_check(struct flash_bank_s *bank)
361 {
362 target_t *target = bank->target;
363
364 u32 protection;
365 int i, s;
366 int num_bits;
367
368 if (target->state != TARGET_HALTED)
369 {
370 return ERROR_TARGET_NOT_HALTED;
371 }
372
373 /* each bit refers to a 4bank protection */
374 target_read_u32(target, STM32_FLASH_WRPR, &protection);
375
376 /* each protection bit is for 4 1K pages */
377 num_bits = (bank->num_sectors / 4);
378
379 for (i = 0; i < num_bits; i++)
380 {
381 int set = 1;
382
383 if( protection & (1 << i))
384 set = 0;
385
386 for (s = 0; s < 4; s++)
387 bank->sectors[(i * 4) + s].is_protected = set;
388 }
389
390 return ERROR_OK;
391 }
392
393 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
394 {
395 target_t *target = bank->target;
396
397 int i;
398 u32 status;
399
400 if (target->state != TARGET_HALTED)
401 {
402 return ERROR_TARGET_NOT_HALTED;
403 }
404
405 /* unlock flash registers */
406 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
407 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
408
409 for (i = first; i <= last; i++)
410 {
411 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
412 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
413 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
414
415 status = stm32x_wait_status_busy(bank, 10);
416
417 if( status & FLASH_WRPRTERR )
418 return ERROR_FLASH_OPERATION_FAILED;
419 if( status & FLASH_PGERR )
420 return ERROR_FLASH_OPERATION_FAILED;
421 bank->sectors[i].is_erased = 1;
422 }
423
424 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
425
426 return ERROR_OK;
427 }
428
429 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
430 {
431 stm32x_flash_bank_t *stm32x_info = NULL;
432 target_t *target = bank->target;
433 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
434 int i, reg, bit;
435 int status;
436 u32 protection;
437
438 stm32x_info = bank->driver_priv;
439
440 if (target->state != TARGET_HALTED)
441 {
442 return ERROR_TARGET_NOT_HALTED;
443 }
444
445 if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
446 {
447 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
448 return ERROR_FLASH_SECTOR_INVALID;
449 }
450
451 /* each bit refers to a 4bank protection */
452 target_read_u32(target, STM32_FLASH_WRPR, &protection);
453
454 prot_reg[0] = (u16)protection;
455 prot_reg[1] = (u16)(protection >> 8);
456 prot_reg[2] = (u16)(protection >> 16);
457 prot_reg[3] = (u16)(protection >> 24);
458
459 for (i = first; i <= last; i++)
460 {
461 reg = (i / 4) / 8;
462 bit = (i / 4) - (reg * 8);
463
464 if( set )
465 prot_reg[reg] &= ~(1 << bit);
466 else
467 prot_reg[reg] |= (1 << bit);
468 }
469
470 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
471 return status;
472
473 stm32x_info->option_bytes.protection[0] = prot_reg[0];
474 stm32x_info->option_bytes.protection[1] = prot_reg[1];
475 stm32x_info->option_bytes.protection[2] = prot_reg[2];
476 stm32x_info->option_bytes.protection[3] = prot_reg[3];
477
478 return stm32x_write_options(bank);
479 }
480
481 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
482 {
483 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
484 target_t *target = bank->target;
485 u32 buffer_size = 8192;
486 working_area_t *source;
487 u32 address = bank->base + offset;
488 reg_param_t reg_params[4];
489 armv7m_algorithm_t armv7m_info;
490 int retval = ERROR_OK;
491
492 u8 stm32x_flash_write_code[] = {
493 /* write: */
494 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
495 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
496 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
497 0x23, 0x60, /* str r3, [r4, #0] */
498 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
499 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
500 /* busy: */
501 0x2B, 0x68, /* ldr r3, [r5, #0] */
502 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
503 0xFB, 0xD0, /* beq busy */
504 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
505 0x01, 0xD1, /* bne exit */
506 0x01, 0x3A, /* subs r2, r2, #1 */
507 0xED, 0xD1, /* bne write */
508 /* exit: */
509 0xFE, 0xE7, /* b exit */
510 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
511 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
512 };
513
514 /* flash write code */
515 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
516 {
517 WARNING("no working area available, can't do block memory writes");
518 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
519 };
520
521 target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
522
523 /* memory buffer */
524 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
525 {
526 buffer_size /= 2;
527 if (buffer_size <= 256)
528 {
529 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
530 if (stm32x_info->write_algorithm)
531 target_free_working_area(target, stm32x_info->write_algorithm);
532
533 WARNING("no large enough working area available, can't do block memory writes");
534 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
535 }
536 };
537
538 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
539 armv7m_info.core_mode = ARMV7M_MODE_ANY;
540 armv7m_info.core_state = ARMV7M_STATE_THUMB;
541
542 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
543 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
544 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
545 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
546
547 while (count > 0)
548 {
549 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
550
551 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
552
553 buf_set_u32(reg_params[0].value, 0, 32, source->address);
554 buf_set_u32(reg_params[1].value, 0, 32, address);
555 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
556
557 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
558 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
559 {
560 ERROR("error executing str7x flash write algorithm");
561 break;
562 }
563
564 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
565 {
566 retval = ERROR_FLASH_OPERATION_FAILED;
567 break;
568 }
569
570 buffer += thisrun_count * 2;
571 address += thisrun_count * 2;
572 count -= thisrun_count;
573 }
574
575 target_free_working_area(target, source);
576 target_free_working_area(target, stm32x_info->write_algorithm);
577
578 destroy_reg_param(&reg_params[0]);
579 destroy_reg_param(&reg_params[1]);
580 destroy_reg_param(&reg_params[2]);
581 destroy_reg_param(&reg_params[3]);
582
583 return retval;
584 }
585
586 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
587 {
588 target_t *target = bank->target;
589 u32 words_remaining = (count / 2);
590 u32 bytes_remaining = (count & 0x00000001);
591 u32 address = bank->base + offset;
592 u32 bytes_written = 0;
593 u8 status;
594 u32 retval;
595
596 if (target->state != TARGET_HALTED)
597 {
598 return ERROR_TARGET_NOT_HALTED;
599 }
600
601 if (offset & 0x1)
602 {
603 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
604 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
605 }
606
607 /* unlock flash registers */
608 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
609 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
610
611 /* multiple half words (2-byte) to be programmed? */
612 if (words_remaining > 0)
613 {
614 /* try using a block write */
615 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
616 {
617 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
618 {
619 /* if block write failed (no sufficient working area),
620 * we use normal (slow) single dword accesses */
621 WARNING("couldn't use block writes, falling back to single memory accesses");
622 }
623 else if (retval == ERROR_FLASH_OPERATION_FAILED)
624 {
625 ERROR("flash writing failed with error code: 0x%x", retval);
626 return ERROR_FLASH_OPERATION_FAILED;
627 }
628 }
629 else
630 {
631 buffer += words_remaining * 2;
632 address += words_remaining * 2;
633 words_remaining = 0;
634 }
635 }
636
637 while (words_remaining > 0)
638 {
639 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
640 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
641
642 status = stm32x_wait_status_busy(bank, 5);
643
644 if( status & FLASH_WRPRTERR )
645 return ERROR_FLASH_OPERATION_FAILED;
646 if( status & FLASH_PGERR )
647 return ERROR_FLASH_OPERATION_FAILED;
648
649 bytes_written += 2;
650 words_remaining--;
651 address += 2;
652 }
653
654 if (bytes_remaining)
655 {
656 u8 last_halfword[2] = {0xff, 0xff};
657 int i = 0;
658
659 while(bytes_remaining > 0)
660 {
661 last_halfword[i++] = *(buffer + bytes_written);
662 bytes_remaining--;
663 bytes_written++;
664 }
665
666 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
667 target_write_u16(target, address, *(u16*)last_halfword);
668
669 status = stm32x_wait_status_busy(bank, 5);
670
671 if( status & FLASH_WRPRTERR )
672 return ERROR_FLASH_OPERATION_FAILED;
673 if( status & FLASH_PGERR )
674 return ERROR_FLASH_OPERATION_FAILED;
675 }
676
677 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
678
679 return ERROR_OK;
680 }
681
682 int stm32x_probe(struct flash_bank_s *bank)
683 {
684 return ERROR_OK;
685 }
686
687 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
688 {
689 return ERROR_OK;
690 }
691
692 int stm32x_erase_check(struct flash_bank_s *bank)
693 {
694 return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
695 }
696
697 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
698 {
699 snprintf(buf, buf_size, "stm32x flash driver info" );
700 return ERROR_OK;
701 }
702
703 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
704 {
705 flash_bank_t *bank;
706 target_t *target = NULL;
707 stm32x_flash_bank_t *stm32x_info = NULL;
708
709 if (argc < 1)
710 {
711 command_print(cmd_ctx, "stm32x lock <bank>");
712 return ERROR_OK;
713 }
714
715 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
716 if (!bank)
717 {
718 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
719 return ERROR_OK;
720 }
721
722 stm32x_info = bank->driver_priv;
723
724 target = bank->target;
725
726 if (target->state != TARGET_HALTED)
727 {
728 return ERROR_TARGET_NOT_HALTED;
729 }
730
731 if (stm32x_erase_options(bank) != ERROR_OK)
732 {
733 command_print(cmd_ctx, "stm32x failed to erase options");
734 return ERROR_OK;
735 }
736
737 /* set readout protection */
738 stm32x_info->option_bytes.RDP = 0;
739
740 if (stm32x_write_options(bank) != ERROR_OK)
741 {
742 command_print(cmd_ctx, "stm32x failed to lock device");
743 return ERROR_OK;
744 }
745
746 command_print(cmd_ctx, "stm32x locked");
747
748 return ERROR_OK;
749 }
750
751 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
752 {
753 flash_bank_t *bank;
754 target_t *target = NULL;
755 stm32x_flash_bank_t *stm32x_info = NULL;
756
757 if (argc < 1)
758 {
759 command_print(cmd_ctx, "stm32x unlock <bank>");
760 return ERROR_OK;
761 }
762
763 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
764 if (!bank)
765 {
766 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
767 return ERROR_OK;
768 }
769
770 stm32x_info = bank->driver_priv;
771
772 target = bank->target;
773
774 if (target->state != TARGET_HALTED)
775 {
776 return ERROR_TARGET_NOT_HALTED;
777 }
778
779 if (stm32x_erase_options(bank) != ERROR_OK)
780 {
781 command_print(cmd_ctx, "stm32x failed to unlock device");
782 return ERROR_OK;
783 }
784
785 if (stm32x_write_options(bank) != ERROR_OK)
786 {
787 command_print(cmd_ctx, "stm32x failed to lock device");
788 return ERROR_OK;
789 }
790
791 command_print(cmd_ctx, "stm32x unlocked");
792
793 return ERROR_OK;
794 }
795
796 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
797 {
798 flash_bank_t *bank;
799 u32 optionbyte;
800 target_t *target = NULL;
801 stm32x_flash_bank_t *stm32x_info = NULL;
802
803 if (argc < 1)
804 {
805 command_print(cmd_ctx, "stm32x options_read <bank>");
806 return ERROR_OK;
807 }
808
809 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
810 if (!bank)
811 {
812 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
813 return ERROR_OK;
814 }
815
816 stm32x_info = bank->driver_priv;
817
818 target = bank->target;
819
820 if (target->state != TARGET_HALTED)
821 {
822 return ERROR_TARGET_NOT_HALTED;
823 }
824
825 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
826 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
827
828 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
829 command_print(cmd_ctx, "Option Byte Complement Error");
830
831 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
832 command_print(cmd_ctx, "Readout Protection On");
833 else
834 command_print(cmd_ctx, "Readout Protection Off");
835
836 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
837 command_print(cmd_ctx, "Software Watchdog");
838 else
839 command_print(cmd_ctx, "Hardware Watchdog");
840
841 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
842 command_print(cmd_ctx, "Stop: No reset generated");
843 else
844 command_print(cmd_ctx, "Stop: Reset generated");
845
846 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
847 command_print(cmd_ctx, "Standby: No reset generated");
848 else
849 command_print(cmd_ctx, "Standby: Reset generated");
850
851 return ERROR_OK;
852 }
853
854 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
855 {
856 flash_bank_t *bank;
857 target_t *target = NULL;
858 stm32x_flash_bank_t *stm32x_info = NULL;
859 u16 optionbyte = 0xF8;
860
861 if (argc < 4)
862 {
863 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
864 return ERROR_OK;
865 }
866
867 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
868 if (!bank)
869 {
870 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
871 return ERROR_OK;
872 }
873
874 stm32x_info = bank->driver_priv;
875
876 target = bank->target;
877
878 if (target->state != TARGET_HALTED)
879 {
880 return ERROR_TARGET_NOT_HALTED;
881 }
882
883 if (strcmp(args[1], "SWWDG") == 0)
884 {
885 optionbyte |= (1<<0);
886 }
887 else
888 {
889 optionbyte &= ~(1<<0);
890 }
891
892 if (strcmp(args[2], "NORSTSTNDBY") == 0)
893 {
894 optionbyte |= (1<<1);
895 }
896 else
897 {
898 optionbyte &= ~(1<<1);
899 }
900
901 if (strcmp(args[3], "NORSTSTOP") == 0)
902 {
903 optionbyte |= (1<<2);
904 }
905 else
906 {
907 optionbyte &= ~(1<<2);
908 }
909
910 if (stm32x_erase_options(bank) != ERROR_OK)
911 {
912 command_print(cmd_ctx, "stm32x failed to erase options");
913 return ERROR_OK;
914 }
915
916 stm32x_info->option_bytes.user_options = optionbyte;
917
918 if (stm32x_write_options(bank) != ERROR_OK)
919 {
920 command_print(cmd_ctx, "stm32x failed to write options");
921 return ERROR_OK;
922 }
923
924 command_print(cmd_ctx, "stm32x write options complete");
925
926 return ERROR_OK;
927 }
928
929 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
930 {
931 target_t *target = NULL;
932 stm32x_flash_bank_t *stm32x_info = NULL;
933 flash_bank_t *bank;
934 u32 status;
935
936 if (argc < 1)
937 {
938 command_print(cmd_ctx, "stm32x mass_erase <bank>");
939 return ERROR_OK;
940 }
941
942 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
943 if (!bank)
944 {
945 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
946 return ERROR_OK;
947 }
948
949 stm32x_info = bank->driver_priv;
950
951 target = bank->target;
952
953 if (target->state != TARGET_HALTED)
954 {
955 return ERROR_TARGET_NOT_HALTED;
956 }
957
958 /* unlock option flash registers */
959 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
960 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
961
962 /* mass erase flash memory */
963 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
964 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
965
966 status = stm32x_wait_status_busy(bank, 10);
967
968 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
969
970 if( status & FLASH_WRPRTERR )
971 {
972 command_print(cmd_ctx, "stm32x device protected");
973 return ERROR_OK;
974 }
975
976 if( status & FLASH_PGERR )
977 {
978 command_print(cmd_ctx, "stm32x device programming failed");
979 return ERROR_OK;
980 }
981
982 command_print(cmd_ctx, "stm32x mass erase complete");
983
984 return ERROR_OK;
985 }
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