1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
40 int cfi_register_commands(struct command_context_s
*cmd_ctx
);
41 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
42 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
);
43 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
44 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
45 int cfi_probe(struct flash_bank_s
*bank
);
46 int cfi_auto_probe(struct flash_bank_s
*bank
);
47 int cfi_erase_check(struct flash_bank_s
*bank
);
48 int cfi_protect_check(struct flash_bank_s
*bank
);
49 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
51 int cfi_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 #define CFI_MAX_BUS_WIDTH 4
54 #define CFI_MAX_CHIP_WIDTH 4
56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
57 #define CFI_MAX_INTEL_CODESIZE 256
59 flash_driver_t cfi_flash
=
62 .register_commands
= cfi_register_commands
,
63 .flash_bank_command
= cfi_flash_bank_command
,
65 .protect
= cfi_protect
,
68 .auto_probe
= cfi_auto_probe
,
69 .erase_check
= cfi_erase_check
,
70 .protect_check
= cfi_protect_check
,
74 cfi_unlock_addresses_t cfi_unlock_addresses
[] =
76 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
77 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
80 /* CFI fixups foward declarations */
81 void cfi_fixup_non_cfi(flash_bank_t
*flash
, void *param
);
82 void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
83 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
84 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
86 /* fixup after identifying JEDEC manufactuer and ID */
87 cfi_fixup_t cfi_jedec_fixups
[] = {
88 {CFI_MFR_SST
, 0x00D4, cfi_fixup_non_cfi
, NULL
},
89 {CFI_MFR_SST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
90 {CFI_MFR_SST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
91 {CFI_MFR_SST
, 0x00D7, cfi_fixup_non_cfi
, NULL
},
92 {CFI_MFR_ST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
93 {CFI_MFR_ST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
94 {CFI_MFR_AMD
, 0x2223, cfi_fixup_non_cfi
, NULL
},
95 {CFI_MFR_AMD
, 0x22ab, cfi_fixup_non_cfi
, NULL
},
99 /* fixup after reading cmdset 0002 primary query table */
100 cfi_fixup_t cfi_0002_fixups
[] = {
101 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
102 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
103 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
104 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
105 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
106 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
110 /* fixup after reading cmdset 0001 primary query table */
111 cfi_fixup_t cfi_0001_fixups
[] = {
115 void cfi_fixup(flash_bank_t
*bank
, cfi_fixup_t
*fixups
)
117 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
120 for (f
= fixups
; f
->fixup
; f
++)
122 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
123 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
125 f
->fixup(bank
, f
->param
);
130 inline u32
flash_address(flash_bank_t
*bank
, int sector
, u32 offset
)
132 /* while the sector list isn't built, only accesses to sector 0 work */
134 return bank
->base
+ offset
* bank
->bus_width
;
139 ERROR("BUG: sector list not yet built");
142 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
147 void cfi_command(flash_bank_t
*bank
, u8 cmd
, u8
*cmd_buf
)
151 /* clear whole buffer, to ensure bits that exceed the bus_width
154 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
157 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
159 for (i
= bank
->bus_width
; i
> 0; i
--)
161 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
166 for (i
= 1; i
<= bank
->bus_width
; i
++)
168 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
173 /* read unsigned 8-bit value from the bank
174 * flash banks are expected to be made of similar chips
175 * the query result should be the same for all
177 u8
cfi_query_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
179 target_t
*target
= bank
->target
;
180 u8 data
[CFI_MAX_BUS_WIDTH
];
182 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
184 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
187 return data
[bank
->bus_width
- 1];
190 /* read unsigned 8-bit value from the bank
191 * in case of a bank made of multiple chips,
192 * the individual values are ORed
194 u8
cfi_get_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
196 target_t
*target
= bank
->target
;
197 u8 data
[CFI_MAX_BUS_WIDTH
];
200 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
202 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
204 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
212 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
213 value
|= data
[bank
->bus_width
- 1 - i
];
219 u16
cfi_query_u16(flash_bank_t
*bank
, int sector
, u32 offset
)
221 target_t
*target
= bank
->target
;
222 u8 data
[CFI_MAX_BUS_WIDTH
* 2];
224 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
226 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
227 return data
[0] | data
[bank
->bus_width
] << 8;
229 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
232 u32
cfi_query_u32(flash_bank_t
*bank
, int sector
, u32 offset
)
234 target_t
*target
= bank
->target
;
235 u8 data
[CFI_MAX_BUS_WIDTH
* 4];
237 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
239 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
240 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
242 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
243 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
246 void cfi_intel_clear_status_register(flash_bank_t
*bank
)
248 target_t
*target
= bank
->target
;
251 if (target
->state
!= TARGET_HALTED
)
253 ERROR("BUG: attempted to clear status register while target wasn't halted");
257 cfi_command(bank
, 0x50, command
);
258 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
261 u8
cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
265 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
267 DEBUG("status: 0x%x", status
);
271 /* mask out bit 0 (reserved) */
272 status
= status
& 0xfe;
274 DEBUG("status: 0x%x", status
);
276 if ((status
& 0x80) != 0x80)
278 ERROR("timeout while waiting for WSM to become ready");
280 else if (status
!= 0x80)
282 ERROR("status register: 0x%x", status
);
284 ERROR("Block Lock-Bit Detected, Operation Abort");
286 ERROR("Program suspended");
288 ERROR("Low Programming Voltage Detected, Operation Aborted");
290 ERROR("Program Error / Error in Setting Lock-Bit");
292 ERROR("Error in Block Erasure or Clear Lock-Bits");
294 ERROR("Block Erase Suspended");
296 cfi_intel_clear_status_register(bank
);
302 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
304 u8 status
, oldstatus
;
306 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
309 status
= cfi_get_u8(bank
, 0, 0x0);
310 if ((status
^ oldstatus
) & 0x40) {
312 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
313 status
= cfi_get_u8(bank
, 0, 0x0);
314 if ((status
^ oldstatus
) & 0x40) {
315 ERROR("dq5 timeout, status: 0x%x", status
);
316 return(ERROR_FLASH_OPERATION_FAILED
);
318 DEBUG("status: 0x%x", status
);
323 DEBUG("status: 0x%x", status
);
329 } while (timeout
-- > 0);
331 ERROR("timeout, status: 0x%x", status
);
333 return(ERROR_FLASH_BUSY
);
336 int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
338 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
339 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
340 target_t
*target
= bank
->target
;
343 cfi_info
->pri_ext
= pri_ext
;
345 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
346 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
347 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
349 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
351 cfi_command(bank
, 0xf0, command
);
352 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
353 cfi_command(bank
, 0xff, command
);
354 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
355 return ERROR_FLASH_BANK_INVALID
;
358 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
359 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
361 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
363 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
364 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
365 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
367 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
369 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
370 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
372 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
373 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
374 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
376 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
377 if (pri_ext
->num_protection_fields
!= 1)
379 WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
382 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
383 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
384 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
386 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
391 int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
393 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
394 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
395 target_t
*target
= bank
->target
;
398 cfi_info
->pri_ext
= pri_ext
;
400 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
401 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
402 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
404 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
406 cfi_command(bank
, 0xf0, command
);
407 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
408 return ERROR_FLASH_BANK_INVALID
;
411 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
412 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
414 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
416 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
417 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
418 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
419 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
420 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
421 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
422 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
423 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
424 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
425 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
426 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
428 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
429 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
431 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
432 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
434 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
437 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
438 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
439 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
441 DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
443 /* default values for implementation specific workarounds */
444 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
445 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
446 pri_ext
->_reversed_geometry
= 0;
451 int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
453 cfi_atmel_pri_ext_t atmel_pri_ext
;
454 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
455 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
456 target_t
*target
= bank
->target
;
459 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
460 * but a different primary extended query table.
461 * We read the atmel table, and prepare a valid AMD/Spansion query table.
464 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
466 cfi_info
->pri_ext
= pri_ext
;
468 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
469 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
470 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
472 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
474 cfi_command(bank
, 0xf0, command
);
475 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
476 return ERROR_FLASH_BANK_INVALID
;
479 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
480 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
481 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
483 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
484 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
486 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
488 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
489 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
491 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
492 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
493 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
494 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
496 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
497 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
499 if (atmel_pri_ext
.features
& 0x02)
500 pri_ext
->EraseSuspend
= 2;
502 if (atmel_pri_ext
.bottom_boot
)
503 pri_ext
->TopBottom
= 2;
505 pri_ext
->TopBottom
= 3;
507 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
508 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
513 int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
515 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
517 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
519 return cfi_read_atmel_pri_ext(bank
);
523 return cfi_read_spansion_pri_ext(bank
);
527 int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
530 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
531 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
533 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
537 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
538 pri_ext
->pri
[1], pri_ext
->pri
[2],
539 pri_ext
->major_version
, pri_ext
->minor_version
);
543 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
544 (pri_ext
->SiliconRevision
) >> 2,
545 (pri_ext
->SiliconRevision
) & 0x03);
549 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
550 pri_ext
->EraseSuspend
,
555 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
556 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
557 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
562 int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
565 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
566 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
568 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
572 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
576 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
580 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
581 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
582 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
586 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
591 int cfi_register_commands(struct command_context_s
*cmd_ctx
)
593 /*command_t *cfi_cmd = */register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, NULL
);
595 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
596 "print part id of cfi flash bank <num>");
601 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
603 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
605 cfi_flash_bank_t
*cfi_info
;
610 WARNING("incomplete flash_bank cfi configuration");
611 return ERROR_FLASH_BANK_INVALID
;
614 if ((strtoul(args
[4], NULL
, 0) > CFI_MAX_CHIP_WIDTH
)
615 || (strtoul(args
[3], NULL
, 0) > CFI_MAX_BUS_WIDTH
))
617 ERROR("chip and bus width have to specified in bytes");
618 return ERROR_FLASH_BANK_INVALID
;
621 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
622 cfi_info
->probed
= 0;
623 bank
->driver_priv
= cfi_info
;
625 cfi_info
->write_algorithm
= NULL
;
626 cfi_info
->erase_check_algorithm
= NULL
;
628 cfi_info
->x16_as_x8
= 0;
629 cfi_info
->jedec_probe
= 0;
630 cfi_info
->not_cfi
= 0;
632 for (i
= 6; i
< argc
; i
++)
634 if (strcmp(args
[i
], "x16_as_x8") == 0)
636 cfi_info
->x16_as_x8
= 1;
638 else if (strcmp(args
[i
], "jedec_probe") == 0)
640 cfi_info
->jedec_probe
= 1;
644 cfi_info
->write_algorithm
= NULL
;
646 /* bank wasn't probed yet */
647 cfi_info
->qry
[0] = -1;
652 int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
654 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
655 target_t
*target
= bank
->target
;
659 cfi_intel_clear_status_register(bank
);
661 for (i
= first
; i
<= last
; i
++)
663 cfi_command(bank
, 0x20, command
);
664 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
666 cfi_command(bank
, 0xd0, command
);
667 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
669 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
670 bank
->sectors
[i
].is_erased
= 1;
673 cfi_command(bank
, 0xff, command
);
674 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
676 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
677 return ERROR_FLASH_OPERATION_FAILED
;
681 cfi_command(bank
, 0xff, command
);
682 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
687 int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
689 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
690 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
691 target_t
*target
= bank
->target
;
695 for (i
= first
; i
<= last
; i
++)
697 cfi_command(bank
, 0xaa, command
);
698 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
700 cfi_command(bank
, 0x55, command
);
701 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
703 cfi_command(bank
, 0x80, command
);
704 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
706 cfi_command(bank
, 0xaa, command
);
707 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
709 cfi_command(bank
, 0x55, command
);
710 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
712 cfi_command(bank
, 0x30, command
);
713 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
715 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
716 bank
->sectors
[i
].is_erased
= 1;
719 cfi_command(bank
, 0xf0, command
);
720 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
722 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
723 return ERROR_FLASH_OPERATION_FAILED
;
727 cfi_command(bank
, 0xf0, command
);
728 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
733 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
735 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
737 if (bank
->target
->state
!= TARGET_HALTED
)
739 return ERROR_TARGET_NOT_HALTED
;
742 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
744 return ERROR_FLASH_SECTOR_INVALID
;
747 if (cfi_info
->qry
[0] != 'Q')
748 return ERROR_FLASH_BANK_NOT_PROBED
;
750 switch(cfi_info
->pri_id
)
754 return cfi_intel_erase(bank
, first
, last
);
757 return cfi_spansion_erase(bank
, first
, last
);
760 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
767 int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
769 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
770 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
771 target_t
*target
= bank
->target
;
776 /* if the device supports neither legacy lock/unlock (bit 3) nor
777 * instant individual block locking (bit 5).
779 if (!(pri_ext
->feature_support
& 0x28))
780 return ERROR_FLASH_OPERATION_FAILED
;
782 cfi_intel_clear_status_register(bank
);
784 for (i
= first
; i
<= last
; i
++)
786 cfi_command(bank
, 0x60, command
);
787 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
788 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
791 cfi_command(bank
, 0x01, command
);
792 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
793 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
794 bank
->sectors
[i
].is_protected
= 1;
798 cfi_command(bank
, 0xd0, command
);
799 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
800 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
801 bank
->sectors
[i
].is_protected
= 0;
804 /* instant individual block locking doesn't require reading of the status register */
805 if (!(pri_ext
->feature_support
& 0x20))
807 /* Clear lock bits operation may take up to 1.4s */
808 cfi_intel_wait_status_busy(bank
, 1400);
813 /* read block lock bit, to verify status */
814 cfi_command(bank
, 0x90, command
);
815 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
816 block_status
= cfi_get_u8(bank
, i
, 0x2);
818 if ((block_status
& 0x1) != set
)
820 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
821 cfi_command(bank
, 0x70, command
);
822 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
823 cfi_intel_wait_status_busy(bank
, 10);
826 return ERROR_FLASH_OPERATION_FAILED
;
836 /* if the device doesn't support individual block lock bits set/clear,
837 * all blocks have been unlocked in parallel, so we set those that should be protected
839 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
841 for (i
= 0; i
< bank
->num_sectors
; i
++)
843 if (bank
->sectors
[i
].is_protected
== 1)
845 cfi_intel_clear_status_register(bank
);
847 cfi_command(bank
, 0x60, command
);
848 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
850 cfi_command(bank
, 0x01, command
);
851 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
853 cfi_intel_wait_status_busy(bank
, 100);
858 cfi_command(bank
, 0xff, command
);
859 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
864 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
866 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
868 if (bank
->target
->state
!= TARGET_HALTED
)
870 return ERROR_TARGET_NOT_HALTED
;
873 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
875 return ERROR_FLASH_SECTOR_INVALID
;
878 if (cfi_info
->qry
[0] != 'Q')
879 return ERROR_FLASH_BANK_NOT_PROBED
;
881 switch(cfi_info
->pri_id
)
885 cfi_intel_protect(bank
, set
, first
, last
);
888 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
895 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
896 static void cfi_add_byte(struct flash_bank_s
*bank
, u8
*word
, u8 byte
)
898 //target_t *target = bank->target;
903 // The data to flash must not be changed in endian! We write a bytestrem in
904 // target byte order already. Only the control and status byte lane of the flash
905 // WSM is interpreted by the CPU in different ways, when read a u16 or u32
906 // word (data seems to be in the upper or lower byte lane for u16 accesses).
908 //if (target->endianness == TARGET_LITTLE_ENDIAN)
911 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
912 word
[i
] = word
[i
+ 1];
913 word
[bank
->bus_width
- 1] = byte
;
918 // for (i = bank->bus_width - 1; i > 0; i--)
919 // word[i] = word[i - 1];
924 /* Convert code image to target endian */
925 /* FIXME create general block conversion fcts in target.c?) */ static
926 void cfi_fix_code_endian(target_t
*target
, u32
*dest
, const u32
*src
, u32 count
)
929 for (i
=0; i
< count
; i
++)
931 target_buffer_set_u32(target
, (u8
*)dest
, *src
);
937 int cfi_intel_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
939 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
940 target_t
*target
= bank
->target
;
941 reg_param_t reg_params
[7];
942 armv4_5_algorithm_t armv4_5_info
;
943 working_area_t
*source
;
944 u32 buffer_size
= 32768;
945 u8 write_command_buf
[CFI_MAX_BUS_WIDTH
];
946 u8 busy_pattern_buf
[CFI_MAX_BUS_WIDTH
];
947 u8 error_pattern_buf
[CFI_MAX_BUS_WIDTH
];
948 u32 write_command_val
, busy_pattern_val
, error_pattern_val
;
950 /* algorithm register usage:
951 * r0: source address (in RAM)
952 * r1: target address (in Flash)
954 * r3: flash write command
955 * r4: status byte (returned to host)
956 * r5: busy test pattern
957 * r6: error test pattern
960 static const u32 word_32_code
[] = {
961 0xe4904004, /* loop: ldr r4, [r0], #4 */
962 0xe5813000, /* str r3, [r1] */
963 0xe5814000, /* str r4, [r1] */
964 0xe5914000, /* busy: ldr r4, [r1] */
965 0xe0047005, /* and r7, r4, r5 */
966 0xe1570005, /* cmp r7, r5 */
967 0x1afffffb, /* bne busy */
968 0xe1140006, /* tst r4, r6 */
969 0x1a000003, /* bne done */
970 0xe2522001, /* subs r2, r2, #1 */
971 0x0a000001, /* beq done */
972 0xe2811004, /* add r1, r1 #4 */
973 0xeafffff2, /* b loop */
974 0xeafffffe /* done: b -2 */
977 static const u32 word_16_code
[] = {
978 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
979 0xe1c130b0, /* strh r3, [r1] */
980 0xe1c140b0, /* strh r4, [r1] */
981 0xe1d140b0, /* busy ldrh r4, [r1] */
982 0xe0047005, /* and r7, r4, r5 */
983 0xe1570005, /* cmp r7, r5 */
984 0x1afffffb, /* bne busy */
985 0xe1140006, /* tst r4, r6 */
986 0x1a000003, /* bne done */
987 0xe2522001, /* subs r2, r2, #1 */
988 0x0a000001, /* beq done */
989 0xe2811002, /* add r1, r1 #2 */
990 0xeafffff2, /* b loop */
991 0xeafffffe /* done: b -2 */
994 static const u32 word_8_code
[] = {
995 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
996 0xe5c13000, /* strb r3, [r1] */
997 0xe5c14000, /* strb r4, [r1] */
998 0xe5d14000, /* busy ldrb r4, [r1] */
999 0xe0047005, /* and r7, r4, r5 */
1000 0xe1570005, /* cmp r7, r5 */
1001 0x1afffffb, /* bne busy */
1002 0xe1140006, /* tst r4, r6 */
1003 0x1a000003, /* bne done */
1004 0xe2522001, /* subs r2, r2, #1 */
1005 0x0a000001, /* beq done */
1006 0xe2811001, /* add r1, r1 #1 */
1007 0xeafffff2, /* b loop */
1008 0xeafffffe /* done: b -2 */
1010 u32 target_code
[CFI_MAX_INTEL_CODESIZE
];
1011 const u32
*target_code_src
;
1012 int target_code_size
;
1013 int retval
= ERROR_OK
;
1016 cfi_intel_clear_status_register(bank
);
1018 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1019 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1020 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1022 /* If we are setting up the write_algorith, we need target_code_src */
1023 /* if not we only need target_code_size. */
1025 /* However, we don't want to create multiple code paths, so we */
1026 /* do the unecessary evaluation of target_code_src, which the */
1027 /* compiler will probably nicely optimize away if not needed */
1029 /* prepare algorithm code for target endian */
1030 switch (bank
->bus_width
)
1033 target_code_src
= word_8_code
;
1034 target_code_size
= sizeof(word_8_code
);
1037 target_code_src
= word_16_code
;
1038 target_code_size
= sizeof(word_16_code
);
1041 target_code_src
= word_32_code
;
1042 target_code_size
= sizeof(word_32_code
);
1045 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1046 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1049 /* flash write code */
1050 if (!cfi_info
->write_algorithm
)
1052 if ( target_code_size
> sizeof(target_code
) )
1054 WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1055 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1057 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
);
1059 /* Get memory for block write handler */
1060 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1061 if (retval
!= ERROR_OK
)
1063 WARNING("No working area available, can't do block memory writes");
1064 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1067 /* write algorithm code to working area */
1068 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, (u8
*)target_code
);
1069 if (retval
!= ERROR_OK
)
1071 ERROR("Unable to write block write code to target");
1076 /* Get a workspace buffer for the data to flash starting with 32k size.
1077 Half size until buffer would be smaller 256 Bytem then fail back */
1078 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1079 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1082 if (buffer_size
<= 256)
1084 WARNING("no large enough working area available, can't do block memory writes");
1085 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1090 /* setup algo registers */
1091 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1092 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1093 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1094 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1095 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1096 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1097 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1099 /* prepare command and status register patterns */
1100 cfi_command(bank
, 0x40, write_command_buf
);
1101 cfi_command(bank
, 0x80, busy_pattern_buf
);
1102 cfi_command(bank
, 0x7e, error_pattern_buf
);
1104 switch (bank
->bus_width
)
1107 write_command_val
= write_command_buf
[0];
1108 busy_pattern_val
= busy_pattern_buf
[0];
1109 error_pattern_val
= error_pattern_buf
[0];
1112 write_command_val
= target_buffer_get_u16(target
, write_command_buf
);
1113 busy_pattern_val
= target_buffer_get_u16(target
, busy_pattern_buf
);
1114 error_pattern_val
= target_buffer_get_u16(target
, error_pattern_buf
);
1117 write_command_val
= target_buffer_get_u32(target
, write_command_buf
);
1118 busy_pattern_val
= target_buffer_get_u32(target
, busy_pattern_buf
);
1119 error_pattern_val
= target_buffer_get_u32(target
, error_pattern_buf
);
1122 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1123 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1127 INFO("Using target buffer at 0x%08x and of size 0x%04x", source
->address
, buffer_size
);
1129 /* Programming main loop */
1132 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1135 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1137 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1138 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1139 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1141 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1142 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1143 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1145 INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count
, address
);
1147 /* Execute algorithm, assume breakpoint for last instruction */
1148 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 7, reg_params
,
1149 cfi_info
->write_algorithm
->address
,
1150 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(u32
),
1151 10000, /* 10s should be enough for max. 32k of data */
1154 /* On failure try a fall back to direct word writes */
1155 if (retval
!= ERROR_OK
)
1157 cfi_intel_clear_status_register(bank
);
1158 ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1159 retval
= ERROR_FLASH_OPERATION_FAILED
;
1160 //retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1161 // FIXME To allow fall back or recovery, we must save the actual status
1162 // somewhere, so that a higher level code can start recovery.
1166 /* Check return value from algo code */
1167 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1170 /* read status register (outputs debug inforation) */
1171 cfi_intel_wait_status_busy(bank
, 100);
1172 cfi_intel_clear_status_register(bank
);
1173 retval
= ERROR_FLASH_OPERATION_FAILED
;
1177 buffer
+= thisrun_count
;
1178 address
+= thisrun_count
;
1179 count
-= thisrun_count
;
1182 /* free up resources */
1185 target_free_working_area(target
, source
);
1187 if (cfi_info
->write_algorithm
)
1189 target_free_working_area(target
, cfi_info
->write_algorithm
);
1190 cfi_info
->write_algorithm
= NULL
;
1193 destroy_reg_param(®_params
[0]);
1194 destroy_reg_param(®_params
[1]);
1195 destroy_reg_param(®_params
[2]);
1196 destroy_reg_param(®_params
[3]);
1197 destroy_reg_param(®_params
[4]);
1198 destroy_reg_param(®_params
[5]);
1199 destroy_reg_param(®_params
[6]);
1204 int cfi_spansion_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1206 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1207 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1208 target_t
*target
= bank
->target
;
1209 reg_param_t reg_params
[10];
1210 armv4_5_algorithm_t armv4_5_info
;
1211 working_area_t
*source
;
1212 u32 buffer_size
= 32768;
1213 u8 write_command
[CFI_MAX_BUS_WIDTH
];
1217 int exit_code
= ERROR_OK
;
1219 /* input parameters - */
1220 /* R0 = source address */
1221 /* R1 = destination address */
1222 /* R2 = number of writes */
1223 /* R3 = flash write command */
1224 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1225 /* output parameters - */
1226 /* R5 = 0x80 ok 0x00 bad */
1227 /* temp registers - */
1228 /* R6 = value read from flash to test status */
1229 /* R7 = holding register */
1230 /* unlock registers - */
1231 /* R8 = unlock1_addr */
1232 /* R9 = unlock1_cmd */
1233 /* R10 = unlock2_addr */
1234 /* R11 = unlock2_cmd */
1236 u32 word_32_code
[] = {
1237 /* 00008100 <sp_32_code>: */
1238 0xe4905004, /* ldr r5, [r0], #4 */
1239 0xe5889000, /* str r9, [r8] */
1240 0xe58ab000, /* str r11, [r10] */
1241 0xe5883000, /* str r3, [r8] */
1242 0xe5815000, /* str r5, [r1] */
1243 0xe1a00000, /* nop */
1245 /* 00008110 <sp_32_busy>: */
1246 0xe5916000, /* ldr r6, [r1] */
1247 0xe0257006, /* eor r7, r5, r6 */
1248 0xe0147007, /* ands r7, r4, r7 */
1249 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1250 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1251 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1252 0xe5916000, /* ldr r6, [r1] */
1253 0xe0257006, /* eor r7, r5, r6 */
1254 0xe0147007, /* ands r7, r4, r7 */
1255 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1256 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1257 0x1a000004, /* bne 8154 <sp_32_done> */
1259 /* 00008140 <sp_32_cont>: */
1260 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1261 0x03a05080, /* moveq r5, #128 ; 0x80 */
1262 0x0a000001, /* beq 8154 <sp_32_done> */
1263 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1264 0xeaffffe8, /* b 8100 <sp_32_code> */
1266 /* 00008154 <sp_32_done>: */
1267 0xeafffffe /* b 8154 <sp_32_done> */
1270 u32 word_16_code
[] = {
1271 /* 00008158 <sp_16_code>: */
1272 0xe0d050b2, /* ldrh r5, [r0], #2 */
1273 0xe1c890b0, /* strh r9, [r8] */
1274 0xe1cab0b0, /* strh r11, [r10] */
1275 0xe1c830b0, /* strh r3, [r8] */
1276 0xe1c150b0, /* strh r5, [r1] */
1277 0xe1a00000, /* nop (mov r0,r0) */
1279 /* 00008168 <sp_16_busy>: */
1280 0xe1d160b0, /* ldrh r6, [r1] */
1281 0xe0257006, /* eor r7, r5, r6 */
1282 0xe0147007, /* ands r7, r4, r7 */
1283 0x0a000007, /* beq 8198 <sp_16_cont> */
1284 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1285 0x0afffff9, /* beq 8168 <sp_16_busy> */
1286 0xe1d160b0, /* ldrh r6, [r1] */
1287 0xe0257006, /* eor r7, r5, r6 */
1288 0xe0147007, /* ands r7, r4, r7 */
1289 0x0a000001, /* beq 8198 <sp_16_cont> */
1290 0xe3a05000, /* mov r5, #0 ; 0x0 */
1291 0x1a000004, /* bne 81ac <sp_16_done> */
1293 /* 00008198 <sp_16_cont>: */
1294 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1295 0x03a05080, /* moveq r5, #128 ; 0x80 */
1296 0x0a000001, /* beq 81ac <sp_16_done> */
1297 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1298 0xeaffffe8, /* b 8158 <sp_16_code> */
1300 /* 000081ac <sp_16_done>: */
1301 0xeafffffe /* b 81ac <sp_16_done> */
1304 u32 word_8_code
[] = {
1305 /* 000081b0 <sp_16_code_end>: */
1306 0xe4d05001, /* ldrb r5, [r0], #1 */
1307 0xe5c89000, /* strb r9, [r8] */
1308 0xe5cab000, /* strb r11, [r10] */
1309 0xe5c83000, /* strb r3, [r8] */
1310 0xe5c15000, /* strb r5, [r1] */
1311 0xe1a00000, /* nop (mov r0,r0) */
1313 /* 000081c0 <sp_8_busy>: */
1314 0xe5d16000, /* ldrb r6, [r1] */
1315 0xe0257006, /* eor r7, r5, r6 */
1316 0xe0147007, /* ands r7, r4, r7 */
1317 0x0a000007, /* beq 81f0 <sp_8_cont> */
1318 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1319 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1320 0xe5d16000, /* ldrb r6, [r1] */
1321 0xe0257006, /* eor r7, r5, r6 */
1322 0xe0147007, /* ands r7, r4, r7 */
1323 0x0a000001, /* beq 81f0 <sp_8_cont> */
1324 0xe3a05000, /* mov r5, #0 ; 0x0 */
1325 0x1a000004, /* bne 8204 <sp_8_done> */
1327 /* 000081f0 <sp_8_cont>: */
1328 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1329 0x03a05080, /* moveq r5, #128 ; 0x80 */
1330 0x0a000001, /* beq 8204 <sp_8_done> */
1331 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1332 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1334 /* 00008204 <sp_8_done>: */
1335 0xeafffffe /* b 8204 <sp_8_done> */
1338 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1339 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1340 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1342 /* flash write code */
1343 if (!cfi_info
->write_algorithm
)
1347 /* convert bus-width dependent algorithm code to correct endiannes */
1348 if (bank
->bus_width
== 1)
1350 code_p
= malloc(24 * 4);
1352 for (i
= 0; i
< 24; i
++)
1353 target_buffer_set_u32(target
, code_p
+ (i
*4), word_8_code
[i
]);
1355 else if (bank
->bus_width
== 2)
1357 code_p
= malloc(24 * 4);
1359 for (i
= 0; i
< 24; i
++)
1360 target_buffer_set_u32(target
, code_p
+ (i
*4), word_16_code
[i
]);
1362 else if (bank
->bus_width
== 4)
1364 code_p
= malloc(24 * 4);
1366 for (i
= 0; i
< 24; i
++)
1367 target_buffer_set_u32(target
, code_p
+ (i
*4), word_32_code
[i
]);
1371 return ERROR_FLASH_OPERATION_FAILED
;
1374 /* allocate working area */
1375 if (target_alloc_working_area(target
, 24 * 4,
1376 &cfi_info
->write_algorithm
) != ERROR_OK
)
1378 WARNING("no working area available, can't do block memory writes");
1379 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1382 /* write algorithm code to working area */
1383 target_write_buffer(target
, cfi_info
->write_algorithm
->address
, 24 * 4, code_p
);
1388 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1391 if (buffer_size
<= 256)
1393 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1394 if (cfi_info
->write_algorithm
)
1395 target_free_working_area(target
, cfi_info
->write_algorithm
);
1397 WARNING("not enough working area available, can't do block memory writes");
1398 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1402 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1403 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1404 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1405 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1406 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1407 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1408 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1409 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1410 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1411 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1415 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1417 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1419 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1420 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1421 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1422 cfi_command(bank
, 0xA0, write_command
);
1423 buf_set_u32(reg_params
[3].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1424 cfi_command(bank
, 0x80, write_command
);
1425 buf_set_u32(reg_params
[4].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1426 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1427 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaa);
1428 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1429 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55);
1431 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 10, reg_params
,
1432 cfi_info
->write_algorithm
->address
,
1433 cfi_info
->write_algorithm
->address
+ ((24 * 4) - 4),
1434 10000, &armv4_5_info
);
1436 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1438 if ((retval
!= ERROR_OK
) || status
!= 0x80)
1440 DEBUG("status: 0x%x", status
);
1441 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1445 buffer
+= thisrun_count
;
1446 address
+= thisrun_count
;
1447 count
-= thisrun_count
;
1450 target_free_working_area(target
, source
);
1452 destroy_reg_param(®_params
[0]);
1453 destroy_reg_param(®_params
[1]);
1454 destroy_reg_param(®_params
[2]);
1455 destroy_reg_param(®_params
[3]);
1456 destroy_reg_param(®_params
[4]);
1457 destroy_reg_param(®_params
[5]);
1458 destroy_reg_param(®_params
[6]);
1459 destroy_reg_param(®_params
[7]);
1460 destroy_reg_param(®_params
[8]);
1461 destroy_reg_param(®_params
[9]);
1466 int cfi_intel_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1468 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1469 target_t
*target
= bank
->target
;
1472 cfi_intel_clear_status_register(bank
);
1473 cfi_command(bank
, 0x40, command
);
1474 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1476 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1478 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1480 cfi_command(bank
, 0xff, command
);
1481 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1483 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1484 return ERROR_FLASH_OPERATION_FAILED
;
1490 int cfi_intel_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1492 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1493 target_t
*target
= bank
->target
;
1496 /* Calculate buffer size and boundary mask */
1497 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1498 u32 buffermask
= buffersize
-1;
1501 /* Check for valid range */
1502 if (address
& buffermask
)
1504 ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1505 return ERROR_FLASH_OPERATION_FAILED
;
1507 switch(bank
->chip_width
)
1509 case 4 : bufferwsize
= buffersize
/ 4; break;
1510 case 2 : bufferwsize
= buffersize
/ 2; break;
1511 case 1 : bufferwsize
= buffersize
; break;
1513 ERROR("Unsupported chip width %d", bank
->chip_width
);
1514 return ERROR_FLASH_OPERATION_FAILED
;
1517 /* Check for valid size */
1518 if (wordcount
> bufferwsize
)
1520 ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1521 return ERROR_FLASH_OPERATION_FAILED
;
1524 /* Write to flash buffer */
1525 cfi_intel_clear_status_register(bank
);
1527 /* Initiate buffer operation _*/
1528 cfi_command(bank
, 0xE8, command
);
1529 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1530 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1532 cfi_command(bank
, 0xff, command
);
1533 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1535 ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank
->base
, address
);
1536 return ERROR_FLASH_OPERATION_FAILED
;
1539 /* Write buffer wordcount-1 and data words */
1540 cfi_command(bank
, bufferwsize
-1, command
);
1541 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1543 target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
);
1545 /* Commit write operation */
1546 cfi_command(bank
, 0xd0, command
);
1547 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1548 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1550 cfi_command(bank
, 0xff, command
);
1551 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1553 ERROR("Buffer write at base 0x%x, address %x failed.", bank
->base
, address
);
1554 return ERROR_FLASH_OPERATION_FAILED
;
1560 int cfi_spansion_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1562 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1563 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1564 target_t
*target
= bank
->target
;
1567 cfi_command(bank
, 0xaa, command
);
1568 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1570 cfi_command(bank
, 0x55, command
);
1571 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
1573 cfi_command(bank
, 0xa0, command
);
1574 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1576 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1578 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1580 cfi_command(bank
, 0xf0, command
);
1581 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1583 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1584 return ERROR_FLASH_OPERATION_FAILED
;
1590 int cfi_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1592 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1594 switch(cfi_info
->pri_id
)
1598 return cfi_intel_write_word(bank
, word
, address
);
1601 return cfi_spansion_write_word(bank
, word
, address
);
1604 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1608 return ERROR_FLASH_OPERATION_FAILED
;
1611 int cfi_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1613 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1615 switch(cfi_info
->pri_id
)
1619 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1622 //return cfi_spansion_write_words(bank, word, address);
1623 ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info
->pri_id
);
1626 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1630 return ERROR_FLASH_OPERATION_FAILED
;
1633 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
1635 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1636 target_t
*target
= bank
->target
;
1637 u32 address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1638 u32 write_p
, copy_p
;
1639 int align
; /* number of unaligned bytes */
1640 int blk_count
; /* number of bus_width bytes for block copy */
1641 u8 current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1645 if (bank
->target
->state
!= TARGET_HALTED
)
1647 return ERROR_TARGET_NOT_HALTED
;
1650 if (offset
+ count
> bank
->size
)
1651 return ERROR_FLASH_DST_OUT_OF_BANK
;
1653 if (cfi_info
->qry
[0] != 'Q')
1654 return ERROR_FLASH_BANK_NOT_PROBED
;
1656 /* start at the first byte of the first word (bus_width size) */
1657 write_p
= address
& ~(bank
->bus_width
- 1);
1658 if ((align
= address
- write_p
) != 0)
1660 INFO("Fixup %d unaligned head bytes", align
);
1662 for (i
= 0; i
< bank
->bus_width
; i
++)
1663 current_word
[i
] = 0;
1666 /* copy bytes before the first write address */
1667 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1670 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1671 cfi_add_byte(bank
, current_word
, byte
);
1674 /* add bytes from the buffer */
1675 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1677 cfi_add_byte(bank
, current_word
, *buffer
++);
1682 /* if the buffer is already finished, copy bytes after the last write address */
1683 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1686 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1687 cfi_add_byte(bank
, current_word
, byte
);
1690 retval
= cfi_write_word(bank
, current_word
, write_p
);
1691 if (retval
!= ERROR_OK
)
1696 /* handle blocks of bus_size aligned bytes */
1697 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1698 switch(cfi_info
->pri_id
)
1700 /* try block writes (fails without working area) */
1703 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1706 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1709 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1710 retval
= ERROR_FLASH_OPERATION_FAILED
;
1713 if (retval
== ERROR_OK
)
1715 /* Increment pointers and decrease count on succesful block write */
1716 buffer
+= blk_count
;
1717 write_p
+= blk_count
;
1722 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1724 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1725 u32 buffermask
= buffersize
-1;
1728 switch(bank
->chip_width
)
1730 case 4 : bufferwsize
= buffersize
/ 4; break;
1731 case 2 : bufferwsize
= buffersize
/ 2; break;
1732 case 1 : bufferwsize
= buffersize
; break;
1734 ERROR("Unsupported chip width %d", bank
->chip_width
);
1735 return ERROR_FLASH_OPERATION_FAILED
;
1738 /* fall back to memory writes */
1739 while (count
> bank
->bus_width
)
1741 if ((write_p
& 0xff) == 0)
1743 INFO("Programming at %08x, count %08x bytes remaining", write_p
, count
);
1745 if ((count
> bufferwsize
) && !(write_p
& buffermask
))
1747 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1748 if (retval
!= ERROR_OK
)
1751 buffer
+= buffersize
;
1752 write_p
+= buffersize
;
1753 count
-= buffersize
;
1757 for (i
= 0; i
< bank
->bus_width
; i
++)
1758 current_word
[i
] = 0;
1760 for (i
= 0; i
< bank
->bus_width
; i
++)
1762 cfi_add_byte(bank
, current_word
, *buffer
++);
1765 retval
= cfi_write_word(bank
, current_word
, write_p
);
1766 if (retval
!= ERROR_OK
)
1769 write_p
+= bank
->bus_width
;
1770 count
-= bank
->bus_width
;
1778 /* return to read array mode, so we can read from flash again for padding */
1779 cfi_command(bank
, 0xf0, current_word
);
1780 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1781 cfi_command(bank
, 0xff, current_word
);
1782 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1784 /* handle unaligned tail bytes */
1787 INFO("Fixup %d unaligned tail bytes", count
);
1790 for (i
= 0; i
< bank
->bus_width
; i
++)
1791 current_word
[i
] = 0;
1793 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
1795 cfi_add_byte(bank
, current_word
, *buffer
++);
1798 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
1801 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1802 cfi_add_byte(bank
, current_word
, byte
);
1804 retval
= cfi_write_word(bank
, current_word
, write_p
);
1805 if (retval
!= ERROR_OK
)
1809 /* return to read array mode */
1810 cfi_command(bank
, 0xf0, current_word
);
1811 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1812 cfi_command(bank
, 0xff, current_word
);
1813 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1818 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
1820 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1821 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1823 pri_ext
->_reversed_geometry
= 1;
1826 void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
1829 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1830 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1832 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
1834 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1836 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
1838 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
1841 swap
= cfi_info
->erase_region_info
[i
];
1842 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
1843 cfi_info
->erase_region_info
[j
] = swap
;
1848 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
1850 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1851 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1852 cfi_unlock_addresses_t
*unlock_addresses
= param
;
1854 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
1855 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
1858 int cfi_probe(struct flash_bank_s
*bank
)
1860 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1861 target_t
*target
= bank
->target
;
1863 int num_sectors
= 0;
1867 u32 unlock1
= 0x555;
1868 u32 unlock2
= 0x2aa;
1870 cfi_info
->probed
= 0;
1872 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1873 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1875 if (cfi_info
->jedec_probe
)
1881 /* switch to read identifier codes mode ("AUTOSELECT") */
1882 cfi_command(bank
, 0xaa, command
);
1883 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1884 cfi_command(bank
, 0x55, command
);
1885 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
);
1886 cfi_command(bank
, 0x90, command
);
1887 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1889 if (bank
->chip_width
== 1)
1891 u8 manufacturer
, device_id
;
1892 target_read_u8(target
, bank
->base
+ 0x0, &manufacturer
);
1893 target_read_u8(target
, bank
->base
+ 0x1, &device_id
);
1894 cfi_info
->manufacturer
= manufacturer
;
1895 cfi_info
->device_id
= device_id
;
1897 else if (bank
->chip_width
== 2)
1899 target_read_u16(target
, bank
->base
+ 0x0, &cfi_info
->manufacturer
);
1900 target_read_u16(target
, bank
->base
+ 0x2, &cfi_info
->device_id
);
1903 /* switch back to read array mode */
1904 cfi_command(bank
, 0xf0, command
);
1905 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1906 cfi_command(bank
, 0xff, command
);
1907 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1909 cfi_fixup(bank
, cfi_jedec_fixups
);
1911 /* query only if this is a CFI compatible flash,
1912 * otherwise the relevant info has already been filled in
1914 if (cfi_info
->not_cfi
== 0)
1916 /* enter CFI query mode
1917 * according to JEDEC Standard No. 68.01,
1918 * a single bus sequence with address = 0x55, data = 0x98 should put
1919 * the device into CFI query mode.
1921 * SST flashes clearly violate this, and we will consider them incompatbile for now
1923 cfi_command(bank
, 0x98, command
);
1924 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
1926 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
1927 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
1928 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
1930 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
1932 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
1934 cfi_command(bank
, 0xf0, command
);
1935 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1936 cfi_command(bank
, 0xff, command
);
1937 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1938 return ERROR_FLASH_BANK_INVALID
;
1941 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
1942 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
1943 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
1944 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
1946 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
1948 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
1949 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
1950 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
1951 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
1952 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
1953 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
1954 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
1955 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
1956 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
1957 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
1958 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
1959 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
1961 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1962 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
1963 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
1964 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
1965 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
1966 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
1967 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
1968 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
1969 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
1970 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
1971 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
1973 cfi_info
->dev_size
= cfi_query_u8(bank
, 0, 0x27);
1974 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
1975 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
1976 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
1978 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
1980 if (((1 << cfi_info
->dev_size
) * bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
1982 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank
->size
, 1 << cfi_info
->dev_size
);
1985 if (cfi_info
->num_erase_regions
)
1987 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
1988 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
1990 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
1991 DEBUG("erase region[%i]: %i blocks of size 0x%x", i
, (cfi_info
->erase_region_info
[i
] & 0xffff) + 1, (cfi_info
->erase_region_info
[i
] >> 16) * 256);
1996 cfi_info
->erase_region_info
= NULL
;
1999 /* We need to read the primary algorithm extended query table before calculating
2000 * the sector layout to be able to apply fixups
2002 switch(cfi_info
->pri_id
)
2004 /* Intel command set (standard and extended) */
2007 cfi_read_intel_pri_ext(bank
);
2009 /* AMD/Spansion, Atmel, ... command set */
2011 cfi_read_0002_pri_ext(bank
);
2014 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2018 /* return to read array mode
2019 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2021 cfi_command(bank
, 0xf0, command
);
2022 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2023 cfi_command(bank
, 0xff, command
);
2024 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2027 /* apply fixups depending on the primary command set */
2028 switch(cfi_info
->pri_id
)
2030 /* Intel command set (standard and extended) */
2033 cfi_fixup(bank
, cfi_0001_fixups
);
2035 /* AMD/Spansion, Atmel, ... command set */
2037 cfi_fixup(bank
, cfi_0002_fixups
);
2040 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2044 if (cfi_info
->num_erase_regions
== 0)
2046 /* a device might have only one erase block, spanning the whole device */
2047 bank
->num_sectors
= 1;
2048 bank
->sectors
= malloc(sizeof(flash_sector_t
));
2050 bank
->sectors
[sector
].offset
= 0x0;
2051 bank
->sectors
[sector
].size
= bank
->size
;
2052 bank
->sectors
[sector
].is_erased
= -1;
2053 bank
->sectors
[sector
].is_protected
= -1;
2057 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2059 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2062 bank
->num_sectors
= num_sectors
;
2063 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
2065 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2068 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2070 bank
->sectors
[sector
].offset
= offset
;
2071 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2072 offset
+= bank
->sectors
[sector
].size
;
2073 bank
->sectors
[sector
].is_erased
= -1;
2074 bank
->sectors
[sector
].is_protected
= -1;
2080 cfi_info
->probed
= 1;
2085 int cfi_auto_probe(struct flash_bank_s
*bank
)
2087 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2088 if (cfi_info
->probed
)
2090 return cfi_probe(bank
);
2093 int cfi_erase_check(struct flash_bank_s
*bank
)
2095 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2096 target_t
*target
= bank
->target
;
2100 if (!cfi_info
->erase_check_algorithm
)
2102 u32 erase_check_code
[] =
2104 0xe4d03001, /* ldrb r3, [r0], #1 */
2105 0xe0022003, /* and r2, r2, r3 */
2106 0xe2511001, /* subs r1, r1, #1 */
2107 0x1afffffb, /* b -4 */
2108 0xeafffffe /* b 0 */
2111 /* make sure we have a working area */
2112 if (target_alloc_working_area(target
, 20, &cfi_info
->erase_check_algorithm
) != ERROR_OK
)
2114 WARNING("no working area available, falling back to slow memory reads");
2118 u8 erase_check_code_buf
[5 * 4];
2120 for (i
= 0; i
< 5; i
++)
2121 target_buffer_set_u32(target
, erase_check_code_buf
+ (i
*4), erase_check_code
[i
]);
2123 /* write algorithm code to working area */
2124 target
->type
->write_memory(target
, cfi_info
->erase_check_algorithm
->address
, 4, 5, erase_check_code_buf
);
2128 if (!cfi_info
->erase_check_algorithm
)
2130 u32
*buffer
= malloc(4096);
2132 for (i
= 0; i
< bank
->num_sectors
; i
++)
2134 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2135 u32 size
= bank
->sectors
[i
].size
;
2136 u32 check
= 0xffffffffU
;
2141 u32 thisrun_size
= (size
> 4096) ? 4096 : size
;
2144 target
->type
->read_memory(target
, address
, 4, thisrun_size
/ 4, (u8
*)buffer
);
2146 for (j
= 0; j
< thisrun_size
/ 4; j
++)
2149 if (check
!= 0xffffffff)
2155 size
-= thisrun_size
;
2156 address
+= thisrun_size
;
2159 bank
->sectors
[i
].is_erased
= erased
;
2166 for (i
= 0; i
< bank
->num_sectors
; i
++)
2168 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2169 u32 size
= bank
->sectors
[i
].size
;
2171 reg_param_t reg_params
[3];
2172 armv4_5_algorithm_t armv4_5_info
;
2174 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2175 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2176 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2178 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
2179 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2181 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2182 buf_set_u32(reg_params
[1].value
, 0, 32, size
);
2184 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
2185 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
2187 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
, cfi_info
->erase_check_algorithm
->address
, cfi_info
->erase_check_algorithm
->address
+ 0x10, 10000, &armv4_5_info
)) != ERROR_OK
)
2188 return ERROR_FLASH_OPERATION_FAILED
;
2190 if (buf_get_u32(reg_params
[2].value
, 0, 32) == 0xff)
2191 bank
->sectors
[i
].is_erased
= 1;
2193 bank
->sectors
[i
].is_erased
= 0;
2195 destroy_reg_param(®_params
[0]);
2196 destroy_reg_param(®_params
[1]);
2197 destroy_reg_param(®_params
[2]);
2204 int cfi_intel_protect_check(struct flash_bank_s
*bank
)
2206 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2207 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2208 target_t
*target
= bank
->target
;
2209 u8 command
[CFI_MAX_BUS_WIDTH
];
2212 /* check if block lock bits are supported on this device */
2213 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2214 return ERROR_FLASH_OPERATION_FAILED
;
2216 cfi_command(bank
, 0x90, command
);
2217 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
2219 for (i
= 0; i
< bank
->num_sectors
; i
++)
2221 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2223 if (block_status
& 1)
2224 bank
->sectors
[i
].is_protected
= 1;
2226 bank
->sectors
[i
].is_protected
= 0;
2229 cfi_command(bank
, 0xff, command
);
2230 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2235 int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
2237 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2238 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2239 target_t
*target
= bank
->target
;
2243 cfi_command(bank
, 0xaa, command
);
2244 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2246 cfi_command(bank
, 0x55, command
);
2247 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
2249 cfi_command(bank
, 0x90, command
);
2250 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2252 for (i
= 0; i
< bank
->num_sectors
; i
++)
2254 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2256 if (block_status
& 1)
2257 bank
->sectors
[i
].is_protected
= 1;
2259 bank
->sectors
[i
].is_protected
= 0;
2262 cfi_command(bank
, 0xf0, command
);
2263 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2268 int cfi_protect_check(struct flash_bank_s
*bank
)
2270 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2272 if (cfi_info
->qry
[0] != 'Q')
2273 return ERROR_FLASH_BANK_NOT_PROBED
;
2275 switch(cfi_info
->pri_id
)
2279 return cfi_intel_protect_check(bank
);
2282 return cfi_spansion_protect_check(bank
);
2285 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2292 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2295 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2297 if (cfi_info
->qry
[0] == (char)-1)
2299 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2303 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2305 buf_size
-= printed
;
2307 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2308 cfi_info
->manufacturer
, cfi_info
->device_id
);
2310 buf_size
-= printed
;
2312 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2314 buf_size
-= printed
;
2316 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2317 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2318 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2319 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2321 buf_size
-= printed
;
2323 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2324 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2326 buf_size
-= printed
;
2328 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2329 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2330 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2331 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2333 buf_size
-= printed
;
2335 printed
= snprintf(buf
, buf_size
, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, cfi_info
->max_buf_write_size
);
2337 buf_size
-= printed
;
2339 switch(cfi_info
->pri_id
)
2343 cfi_intel_info(bank
, buf
, buf_size
);
2346 cfi_spansion_info(bank
, buf
, buf_size
);
2349 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);