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cortexm: use Cortex-M rather than cortex-m3 for dwt registers
[openocd.git] / src / target / cortex_m.c
blobdc8d344401abe7d83f0db75d7b379b4f45489f61
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
36 #include "cortex_m.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
40 #include "register.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
44
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
50 *
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
53 * any longer.
54 */
55
56 /**
57 * Returns the type of a break point required by address location
58 */
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
60
61 /* forward declarations */
62 static int cortex_m_store_core_reg_u32(struct target *target,
63 uint32_t num, uint32_t value);
64
65 static int cortexm_dap_read_coreregister_u32(struct target *target,
66 uint32_t *value, int regnum)
67 {
68 struct armv7m_common *armv7m = target_to_armv7m(target);
69 struct adiv5_dap *swjdp = armv7m->arm.dap;
70 int retval;
71 uint32_t dcrdr;
72
73 /* because the DCB_DCRDR is used for the emulated dcc channel
74 * we have to save/restore the DCB_DCRDR when used */
75 if (target->dbg_msg_enabled) {
76 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
77 if (retval != ERROR_OK)
78 return retval;
79 }
80
81 retval = mem_ap_write_u32(swjdp, DCB_DCRSR, regnum);
82 if (retval != ERROR_OK)
83 return retval;
84
85 retval = mem_ap_read_atomic_u32(swjdp, DCB_DCRDR, value);
86 if (retval != ERROR_OK)
87 return retval;
88
89 if (target->dbg_msg_enabled) {
90 /* restore DCB_DCRDR - this needs to be in a separate
91 * transaction otherwise the emulated DCC channel breaks */
92 if (retval == ERROR_OK)
93 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
94 }
95
96 return retval;
97 }
98
99 static int cortexm_dap_write_coreregister_u32(struct target *target,
100 uint32_t value, int regnum)
101 {
102 struct armv7m_common *armv7m = target_to_armv7m(target);
103 struct adiv5_dap *swjdp = armv7m->arm.dap;
104 int retval;
105 uint32_t dcrdr;
106
107 /* because the DCB_DCRDR is used for the emulated dcc channel
108 * we have to save/restore the DCB_DCRDR when used */
109 if (target->dbg_msg_enabled) {
110 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
111 if (retval != ERROR_OK)
112 return retval;
113 }
114
115 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, value);
116 if (retval != ERROR_OK)
117 return retval;
118
119 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRSR, regnum | DCRSR_WnR);
120 if (retval != ERROR_OK)
121 return retval;
122
123 if (target->dbg_msg_enabled) {
124 /* restore DCB_DCRDR - this needs to be in a seperate
125 * transaction otherwise the emulated DCC channel breaks */
126 if (retval == ERROR_OK)
127 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
128 }
129
130 return retval;
131 }
132
133 static int cortex_m_write_debug_halt_mask(struct target *target,
134 uint32_t mask_on, uint32_t mask_off)
135 {
136 struct cortex_m_common *cortex_m = target_to_cm(target);
137 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
138
139 /* mask off status bits */
140 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
141 /* create new register mask */
142 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
143
144 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m->dcb_dhcsr);
145 }
146
147 static int cortex_m_clear_halt(struct target *target)
148 {
149 struct cortex_m_common *cortex_m = target_to_cm(target);
150 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
151 int retval;
152
153 /* clear step if any */
154 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
155
156 /* Read Debug Fault Status Register */
157 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m->nvic_dfsr);
158 if (retval != ERROR_OK)
159 return retval;
160
161 /* Clear Debug Fault Status */
162 retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m->nvic_dfsr);
163 if (retval != ERROR_OK)
164 return retval;
165 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
166
167 return ERROR_OK;
168 }
169
170 static int cortex_m_single_step_core(struct target *target)
171 {
172 struct cortex_m_common *cortex_m = target_to_cm(target);
173 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
174 uint32_t dhcsr_save;
175 int retval;
176
177 /* backup dhcsr reg */
178 dhcsr_save = cortex_m->dcb_dhcsr;
179
180 /* Mask interrupts before clearing halt, if done already. This avoids
181 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
182 * HALT can put the core into an unknown state.
183 */
184 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
185 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
186 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
187 if (retval != ERROR_OK)
188 return retval;
189 }
190 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
191 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
192 if (retval != ERROR_OK)
193 return retval;
194 LOG_DEBUG(" ");
195
196 /* restore dhcsr reg */
197 cortex_m->dcb_dhcsr = dhcsr_save;
198 cortex_m_clear_halt(target);
199
200 return ERROR_OK;
201 }
202
203 static int cortex_m_enable_fpb(struct target *target)
204 {
205 int retval = target_write_u32(target, FP_CTRL, 3);
206 if (retval != ERROR_OK)
207 return retval;
208
209 /* check the fpb is actually enabled */
210 uint32_t fpctrl;
211 retval = target_read_u32(target, FP_CTRL, &fpctrl);
212 if (retval != ERROR_OK)
213 return retval;
214
215 if (fpctrl & 1)
216 return ERROR_OK;
217
218 return ERROR_FAIL;
219 }
220
221 static int cortex_m_endreset_event(struct target *target)
222 {
223 int i;
224 int retval;
225 uint32_t dcb_demcr;
226 struct cortex_m_common *cortex_m = target_to_cm(target);
227 struct armv7m_common *armv7m = &cortex_m->armv7m;
228 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
229 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
230 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
231
232 /* REVISIT The four debug monitor bits are currently ignored... */
233 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
234 if (retval != ERROR_OK)
235 return retval;
236 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
237
238 /* this register is used for emulated dcc channel */
239 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
240 if (retval != ERROR_OK)
241 return retval;
242
243 /* Enable debug requests */
244 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
245 if (retval != ERROR_OK)
246 return retval;
247 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
248 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
249 if (retval != ERROR_OK)
250 return retval;
251 }
252
253 /* clear any interrupt masking */
254 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
255
256 /* Enable features controlled by ITM and DWT blocks, and catch only
257 * the vectors we were told to pay attention to.
258 *
259 * Target firmware is responsible for all fault handling policy
260 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
261 * or manual updates to the NVIC SHCSR and CCR registers.
262 */
263 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
264 if (retval != ERROR_OK)
265 return retval;
266
267 /* Paranoia: evidently some (early?) chips don't preserve all the
268 * debug state (including FBP, DWT, etc) across reset...
269 */
270
271 /* Enable FPB */
272 retval = cortex_m_enable_fpb(target);
273 if (retval != ERROR_OK) {
274 LOG_ERROR("Failed to enable the FPB");
275 return retval;
276 }
277
278 cortex_m->fpb_enabled = 1;
279
280 /* Restore FPB registers */
281 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
282 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
283 if (retval != ERROR_OK)
284 return retval;
285 }
286
287 /* Restore DWT registers */
288 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
289 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
290 dwt_list[i].comp);
291 if (retval != ERROR_OK)
292 return retval;
293 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
294 dwt_list[i].mask);
295 if (retval != ERROR_OK)
296 return retval;
297 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
298 dwt_list[i].function);
299 if (retval != ERROR_OK)
300 return retval;
301 }
302 retval = dap_run(swjdp);
303 if (retval != ERROR_OK)
304 return retval;
305
306 register_cache_invalidate(armv7m->arm.core_cache);
307
308 /* make sure we have latest dhcsr flags */
309 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
310
311 return retval;
312 }
313
314 static int cortex_m_examine_debug_reason(struct target *target)
315 {
316 struct cortex_m_common *cortex_m = target_to_cm(target);
317
318 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
319 * only check the debug reason if we don't know it already */
320
321 if ((target->debug_reason != DBG_REASON_DBGRQ)
322 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
323 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
324 target->debug_reason = DBG_REASON_BREAKPOINT;
325 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
326 target->debug_reason = DBG_REASON_WPTANDBKPT;
327 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
328 target->debug_reason = DBG_REASON_WATCHPOINT;
329 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
330 target->debug_reason = DBG_REASON_BREAKPOINT;
331 else /* EXTERNAL, HALTED */
332 target->debug_reason = DBG_REASON_UNDEFINED;
333 }
334
335 return ERROR_OK;
336 }
337
338 static int cortex_m_examine_exception_reason(struct target *target)
339 {
340 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
341 struct armv7m_common *armv7m = target_to_armv7m(target);
342 struct adiv5_dap *swjdp = armv7m->arm.dap;
343 int retval;
344
345 retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
346 if (retval != ERROR_OK)
347 return retval;
348 switch (armv7m->exception_number) {
349 case 2: /* NMI */
350 break;
351 case 3: /* Hard Fault */
352 retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
353 if (retval != ERROR_OK)
354 return retval;
355 if (except_sr & 0x40000000) {
356 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
357 if (retval != ERROR_OK)
358 return retval;
359 }
360 break;
361 case 4: /* Memory Management */
362 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
363 if (retval != ERROR_OK)
364 return retval;
365 retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
366 if (retval != ERROR_OK)
367 return retval;
368 break;
369 case 5: /* Bus Fault */
370 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
371 if (retval != ERROR_OK)
372 return retval;
373 retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
374 if (retval != ERROR_OK)
375 return retval;
376 break;
377 case 6: /* Usage Fault */
378 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
379 if (retval != ERROR_OK)
380 return retval;
381 break;
382 case 11: /* SVCall */
383 break;
384 case 12: /* Debug Monitor */
385 retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
386 if (retval != ERROR_OK)
387 return retval;
388 break;
389 case 14: /* PendSV */
390 break;
391 case 15: /* SysTick */
392 break;
393 default:
394 except_sr = 0;
395 break;
396 }
397 retval = dap_run(swjdp);
398 if (retval == ERROR_OK)
399 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
400 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
401 armv7m_exception_string(armv7m->exception_number),
402 shcsr, except_sr, cfsr, except_ar);
403 return retval;
404 }
405
406 static int cortex_m_debug_entry(struct target *target)
407 {
408 int i;
409 uint32_t xPSR;
410 int retval;
411 struct cortex_m_common *cortex_m = target_to_cm(target);
412 struct armv7m_common *armv7m = &cortex_m->armv7m;
413 struct arm *arm = &armv7m->arm;
414 struct adiv5_dap *swjdp = armv7m->arm.dap;
415 struct reg *r;
416
417 LOG_DEBUG(" ");
418
419 cortex_m_clear_halt(target);
420 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
421 if (retval != ERROR_OK)
422 return retval;
423
424 retval = armv7m->examine_debug_reason(target);
425 if (retval != ERROR_OK)
426 return retval;
427
428 /* Examine target state and mode
429 * First load register accessible through core debug port */
430 int num_regs = arm->core_cache->num_regs;
431
432 for (i = 0; i < num_regs; i++) {
433 r = &armv7m->arm.core_cache->reg_list[i];
434 if (!r->valid)
435 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
436 }
437
438 r = arm->cpsr;
439 xPSR = buf_get_u32(r->value, 0, 32);
440
441 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
442 if (xPSR & 0xf00) {
443 r->dirty = r->valid;
444 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
445 }
446
447 /* Are we in an exception handler */
448 if (xPSR & 0x1FF) {
449 armv7m->exception_number = (xPSR & 0x1FF);
450
451 arm->core_mode = ARM_MODE_HANDLER;
452 arm->map = armv7m_msp_reg_map;
453 } else {
454 unsigned control = buf_get_u32(arm->core_cache
455 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
456
457 /* is this thread privileged? */
458 arm->core_mode = control & 1
459 ? ARM_MODE_USER_THREAD
460 : ARM_MODE_THREAD;
461
462 /* which stack is it using? */
463 if (control & 2)
464 arm->map = armv7m_psp_reg_map;
465 else
466 arm->map = armv7m_msp_reg_map;
467
468 armv7m->exception_number = 0;
469 }
470
471 if (armv7m->exception_number)
472 cortex_m_examine_exception_reason(target);
473
474 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
475 arm_mode_name(arm->core_mode),
476 *(uint32_t *)(arm->pc->value),
477 target_state_name(target));
478
479 if (armv7m->post_debug_entry) {
480 retval = armv7m->post_debug_entry(target);
481 if (retval != ERROR_OK)
482 return retval;
483 }
484
485 return ERROR_OK;
486 }
487
488 static int cortex_m_poll(struct target *target)
489 {
490 int detected_failure = ERROR_OK;
491 int retval = ERROR_OK;
492 enum target_state prev_target_state = target->state;
493 struct cortex_m_common *cortex_m = target_to_cm(target);
494 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
495
496 /* Read from Debug Halting Control and Status Register */
497 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
498 if (retval != ERROR_OK) {
499 target->state = TARGET_UNKNOWN;
500 return retval;
501 }
502
503 /* Recover from lockup. See ARMv7-M architecture spec,
504 * section B1.5.15 "Unrecoverable exception cases".
505 */
506 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
507 LOG_ERROR("%s -- clearing lockup after double fault",
508 target_name(target));
509 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
510 target->debug_reason = DBG_REASON_DBGRQ;
511
512 /* We have to execute the rest (the "finally" equivalent, but
513 * still throw this exception again).
514 */
515 detected_failure = ERROR_FAIL;
516
517 /* refresh status bits */
518 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
519 if (retval != ERROR_OK)
520 return retval;
521 }
522
523 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
524 /* check if still in reset */
525 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
526 if (retval != ERROR_OK)
527 return retval;
528
529 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
530 target->state = TARGET_RESET;
531 return ERROR_OK;
532 }
533 }
534
535 if (target->state == TARGET_RESET) {
536 /* Cannot switch context while running so endreset is
537 * called with target->state == TARGET_RESET
538 */
539 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
540 cortex_m->dcb_dhcsr);
541 cortex_m_endreset_event(target);
542 target->state = TARGET_RUNNING;
543 prev_target_state = TARGET_RUNNING;
544 }
545
546 if (cortex_m->dcb_dhcsr & S_HALT) {
547 target->state = TARGET_HALTED;
548
549 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
550 retval = cortex_m_debug_entry(target);
551 if (retval != ERROR_OK)
552 return retval;
553
554 if (arm_semihosting(target, &retval) != 0)
555 return retval;
556
557 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
558 }
559 if (prev_target_state == TARGET_DEBUG_RUNNING) {
560 LOG_DEBUG(" ");
561 retval = cortex_m_debug_entry(target);
562 if (retval != ERROR_OK)
563 return retval;
564
565 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
566 }
567 }
568
569 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
570 * How best to model low power modes?
571 */
572
573 if (target->state == TARGET_UNKNOWN) {
574 /* check if processor is retiring instructions */
575 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
576 target->state = TARGET_RUNNING;
577 retval = ERROR_OK;
578 }
579 }
580
581 /* Did we detect a failure condition that we cleared? */
582 if (detected_failure != ERROR_OK)
583 retval = detected_failure;
584 return retval;
585 }
586
587 static int cortex_m_halt(struct target *target)
588 {
589 LOG_DEBUG("target->state: %s",
590 target_state_name(target));
591
592 if (target->state == TARGET_HALTED) {
593 LOG_DEBUG("target was already halted");
594 return ERROR_OK;
595 }
596
597 if (target->state == TARGET_UNKNOWN)
598 LOG_WARNING("target was in unknown state when halt was requested");
599
600 if (target->state == TARGET_RESET) {
601 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
602 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
603 return ERROR_TARGET_FAILURE;
604 } else {
605 /* we came here in a reset_halt or reset_init sequence
606 * debug entry was already prepared in cortex_m3_assert_reset()
607 */
608 target->debug_reason = DBG_REASON_DBGRQ;
609
610 return ERROR_OK;
611 }
612 }
613
614 /* Write to Debug Halting Control and Status Register */
615 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
616
617 target->debug_reason = DBG_REASON_DBGRQ;
618
619 return ERROR_OK;
620 }
621
622 static int cortex_m_soft_reset_halt(struct target *target)
623 {
624 struct cortex_m_common *cortex_m = target_to_cm(target);
625 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
626 uint32_t dcb_dhcsr = 0;
627 int retval, timeout = 0;
628
629 /* soft_reset_halt is deprecated on cortex_m as the same functionality
630 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
631 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
632 * core, not the peripherals */
633 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
634
635 /* Enter debug state on reset; restore DEMCR in endreset_event() */
636 retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
637 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
638 if (retval != ERROR_OK)
639 return retval;
640
641 /* Request a core-only reset */
642 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
643 AIRCR_VECTKEY | AIRCR_VECTRESET);
644 if (retval != ERROR_OK)
645 return retval;
646 target->state = TARGET_RESET;
647
648 /* registers are now invalid */
649 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
650
651 while (timeout < 100) {
652 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
653 if (retval == ERROR_OK) {
654 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
655 &cortex_m->nvic_dfsr);
656 if (retval != ERROR_OK)
657 return retval;
658 if ((dcb_dhcsr & S_HALT)
659 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
660 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
661 "DFSR 0x%08x",
662 (unsigned) dcb_dhcsr,
663 (unsigned) cortex_m->nvic_dfsr);
664 cortex_m_poll(target);
665 /* FIXME restore user's vector catch config */
666 return ERROR_OK;
667 } else
668 LOG_DEBUG("waiting for system reset-halt, "
669 "DHCSR 0x%08x, %d ms",
670 (unsigned) dcb_dhcsr, timeout);
671 }
672 timeout++;
673 alive_sleep(1);
674 }
675
676 return ERROR_OK;
677 }
678
679 void cortex_m_enable_breakpoints(struct target *target)
680 {
681 struct breakpoint *breakpoint = target->breakpoints;
682
683 /* set any pending breakpoints */
684 while (breakpoint) {
685 if (!breakpoint->set)
686 cortex_m_set_breakpoint(target, breakpoint);
687 breakpoint = breakpoint->next;
688 }
689 }
690
691 static int cortex_m_resume(struct target *target, int current,
692 uint32_t address, int handle_breakpoints, int debug_execution)
693 {
694 struct armv7m_common *armv7m = target_to_armv7m(target);
695 struct breakpoint *breakpoint = NULL;
696 uint32_t resume_pc;
697 struct reg *r;
698
699 if (target->state != TARGET_HALTED) {
700 LOG_WARNING("target not halted");
701 return ERROR_TARGET_NOT_HALTED;
702 }
703
704 if (!debug_execution) {
705 target_free_all_working_areas(target);
706 cortex_m_enable_breakpoints(target);
707 cortex_m_enable_watchpoints(target);
708 }
709
710 if (debug_execution) {
711 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
712
713 /* Disable interrupts */
714 /* We disable interrupts in the PRIMASK register instead of
715 * masking with C_MASKINTS. This is probably the same issue
716 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
717 * in parallel with disabled interrupts can cause local faults
718 * to not be taken.
719 *
720 * REVISIT this clearly breaks non-debug execution, since the
721 * PRIMASK register state isn't saved/restored... workaround
722 * by never resuming app code after debug execution.
723 */
724 buf_set_u32(r->value, 0, 1, 1);
725 r->dirty = true;
726 r->valid = true;
727
728 /* Make sure we are in Thumb mode */
729 r = armv7m->arm.cpsr;
730 buf_set_u32(r->value, 24, 1, 1);
731 r->dirty = true;
732 r->valid = true;
733 }
734
735 /* current = 1: continue on current pc, otherwise continue at <address> */
736 r = armv7m->arm.pc;
737 if (!current) {
738 buf_set_u32(r->value, 0, 32, address);
739 r->dirty = true;
740 r->valid = true;
741 }
742
743 /* if we halted last time due to a bkpt instruction
744 * then we have to manually step over it, otherwise
745 * the core will break again */
746
747 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
748 && !debug_execution)
749 armv7m_maybe_skip_bkpt_inst(target, NULL);
750
751 resume_pc = buf_get_u32(r->value, 0, 32);
752
753 armv7m_restore_context(target);
754
755 /* the front-end may request us not to handle breakpoints */
756 if (handle_breakpoints) {
757 /* Single step past breakpoint at current address */
758 breakpoint = breakpoint_find(target, resume_pc);
759 if (breakpoint) {
760 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")",
761 breakpoint->address,
762 breakpoint->unique_id);
763 cortex_m_unset_breakpoint(target, breakpoint);
764 cortex_m_single_step_core(target);
765 cortex_m_set_breakpoint(target, breakpoint);
766 }
767 }
768
769 /* Restart core */
770 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
771
772 target->debug_reason = DBG_REASON_NOTHALTED;
773
774 /* registers are now invalid */
775 register_cache_invalidate(armv7m->arm.core_cache);
776
777 if (!debug_execution) {
778 target->state = TARGET_RUNNING;
779 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
780 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
781 } else {
782 target->state = TARGET_DEBUG_RUNNING;
783 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
784 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
785 }
786
787 return ERROR_OK;
788 }
789
790 /* int irqstepcount = 0; */
791 static int cortex_m_step(struct target *target, int current,
792 uint32_t address, int handle_breakpoints)
793 {
794 struct cortex_m_common *cortex_m = target_to_cm(target);
795 struct armv7m_common *armv7m = &cortex_m->armv7m;
796 struct adiv5_dap *swjdp = armv7m->arm.dap;
797 struct breakpoint *breakpoint = NULL;
798 struct reg *pc = armv7m->arm.pc;
799 bool bkpt_inst_found = false;
800 int retval;
801 bool isr_timed_out = false;
802
803 if (target->state != TARGET_HALTED) {
804 LOG_WARNING("target not halted");
805 return ERROR_TARGET_NOT_HALTED;
806 }
807
808 /* current = 1: continue on current pc, otherwise continue at <address> */
809 if (!current)
810 buf_set_u32(pc->value, 0, 32, address);
811
812 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
813
814 /* the front-end may request us not to handle breakpoints */
815 if (handle_breakpoints) {
816 breakpoint = breakpoint_find(target, pc_value);
817 if (breakpoint)
818 cortex_m_unset_breakpoint(target, breakpoint);
819 }
820
821 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
822
823 target->debug_reason = DBG_REASON_SINGLESTEP;
824
825 armv7m_restore_context(target);
826
827 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
828
829 /* if no bkpt instruction is found at pc then we can perform
830 * a normal step, otherwise we have to manually step over the bkpt
831 * instruction - as such simulate a step */
832 if (bkpt_inst_found == false) {
833 /* Automatic ISR masking mode off: Just step over the next instruction */
834 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
835 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
836 else {
837 /* Process interrupts during stepping in a way they don't interfere
838 * debugging.
839 *
840 * Principle:
841 *
842 * Set a temporary break point at the current pc and let the core run
843 * with interrupts enabled. Pending interrupts get served and we run
844 * into the breakpoint again afterwards. Then we step over the next
845 * instruction with interrupts disabled.
846 *
847 * If the pending interrupts don't complete within time, we leave the
848 * core running. This may happen if the interrupts trigger faster
849 * than the core can process them or the handler doesn't return.
850 *
851 * If no more breakpoints are available we simply do a step with
852 * interrupts enabled.
853 *
854 */
855
856 /* 2012-09-29 ph
857 *
858 * If a break point is already set on the lower half word then a break point on
859 * the upper half word will not break again when the core is restarted. So we
860 * just step over the instruction with interrupts disabled.
861 *
862 * The documentation has no information about this, it was found by observation
863 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
864 * suffer from this problem.
865 *
866 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
867 * address has it always cleared. The former is done to indicate thumb mode
868 * to gdb.
869 *
870 */
871 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
872 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
873 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
874 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
875 /* Re-enable interrupts */
876 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
877 }
878 else {
879
880 /* Set a temporary break point */
881 if (breakpoint)
882 retval = cortex_m_set_breakpoint(target, breakpoint);
883 else
884 retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
885 bool tmp_bp_set = (retval == ERROR_OK);
886
887 /* No more breakpoints left, just do a step */
888 if (!tmp_bp_set)
889 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
890 else {
891 /* Start the core */
892 LOG_DEBUG("Starting core to serve pending interrupts");
893 int64_t t_start = timeval_ms();
894 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
895
896 /* Wait for pending handlers to complete or timeout */
897 do {
898 retval = mem_ap_read_atomic_u32(swjdp,
899 DCB_DHCSR,
900 &cortex_m->dcb_dhcsr);
901 if (retval != ERROR_OK) {
902 target->state = TARGET_UNKNOWN;
903 return retval;
904 }
905 isr_timed_out = ((timeval_ms() - t_start) > 500);
906 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
907
908 /* only remove breakpoint if we created it */
909 if (breakpoint)
910 cortex_m_unset_breakpoint(target, breakpoint);
911 else {
912 /* Remove the temporary breakpoint */
913 breakpoint_remove(target, pc_value);
914 }
915
916 if (isr_timed_out) {
917 LOG_DEBUG("Interrupt handlers didn't complete within time, "
918 "leaving target running");
919 } else {
920 /* Step over next instruction with interrupts disabled */
921 cortex_m_write_debug_halt_mask(target,
922 C_HALT | C_MASKINTS,
923 0);
924 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
925 /* Re-enable interrupts */
926 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
927 }
928 }
929 }
930 }
931 }
932
933 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
934 if (retval != ERROR_OK)
935 return retval;
936
937 /* registers are now invalid */
938 register_cache_invalidate(armv7m->arm.core_cache);
939
940 if (breakpoint)
941 cortex_m_set_breakpoint(target, breakpoint);
942
943 if (isr_timed_out) {
944 /* Leave the core running. The user has to stop execution manually. */
945 target->debug_reason = DBG_REASON_NOTHALTED;
946 target->state = TARGET_RUNNING;
947 return ERROR_OK;
948 }
949
950 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
951 " nvic_icsr = 0x%" PRIx32,
952 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
953
954 retval = cortex_m_debug_entry(target);
955 if (retval != ERROR_OK)
956 return retval;
957 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
958
959 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
960 " nvic_icsr = 0x%" PRIx32,
961 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
962
963 return ERROR_OK;
964 }
965
966 static int cortex_m_assert_reset(struct target *target)
967 {
968 struct cortex_m_common *cortex_m = target_to_cm(target);
969 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
970 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
971
972 LOG_DEBUG("target->state: %s",
973 target_state_name(target));
974
975 enum reset_types jtag_reset_config = jtag_get_reset_config();
976
977 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
978 /* allow scripts to override the reset event */
979
980 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
981 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
982 target->state = TARGET_RESET;
983
984 return ERROR_OK;
985 }
986
987 /* some cores support connecting while srst is asserted
988 * use that mode is it has been configured */
989
990 bool srst_asserted = false;
991
992 if ((jtag_reset_config & RESET_HAS_SRST) &&
993 (jtag_reset_config & RESET_SRST_NO_GATING)) {
994 adapter_assert_reset();
995 srst_asserted = true;
996 }
997
998 /* Enable debug requests */
999 int retval;
1000 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1001 if (retval != ERROR_OK)
1002 return retval;
1003 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
1004 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
1005 if (retval != ERROR_OK)
1006 return retval;
1007 }
1008
1009 /* If the processor is sleeping in a WFI or WFE instruction, the
1010 * C_HALT bit must be asserted to regain control */
1011 if (cortex_m->dcb_dhcsr & S_SLEEP) {
1012 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1013 if (retval != ERROR_OK)
1014 return retval;
1015 }
1016
1017 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
1018 if (retval != ERROR_OK)
1019 return retval;
1020
1021 if (!target->reset_halt) {
1022 /* Set/Clear C_MASKINTS in a separate operation */
1023 if (cortex_m->dcb_dhcsr & C_MASKINTS) {
1024 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
1025 DBGKEY | C_DEBUGEN | C_HALT);
1026 if (retval != ERROR_OK)
1027 return retval;
1028 }
1029
1030 /* clear any debug flags before resuming */
1031 cortex_m_clear_halt(target);
1032
1033 /* clear C_HALT in dhcsr reg */
1034 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1035 } else {
1036 /* Halt in debug on reset; endreset_event() restores DEMCR.
1037 *
1038 * REVISIT catching BUSERR presumably helps to defend against
1039 * bad vector table entries. Should this include MMERR or
1040 * other flags too?
1041 */
1042 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
1043 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1044 if (retval != ERROR_OK)
1045 return retval;
1046 }
1047
1048 if (jtag_reset_config & RESET_HAS_SRST) {
1049 /* default to asserting srst */
1050 if (!srst_asserted)
1051 adapter_assert_reset();
1052 } else {
1053 /* Use a standard Cortex-M3 software reset mechanism.
1054 * We default to using VECRESET as it is supported on all current cores.
1055 * This has the disadvantage of not resetting the peripherals, so a
1056 * reset-init event handler is needed to perform any peripheral resets.
1057 */
1058 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1059 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1060 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1061 if (retval != ERROR_OK)
1062 return retval;
1063
1064 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1065 ? "SYSRESETREQ" : "VECTRESET");
1066
1067 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1068 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1069 "handler to reset any peripherals or configure hardware srst support.");
1070 }
1071
1072 {
1073 /* I do not know why this is necessary, but it
1074 * fixes strange effects (step/resume cause NMI
1075 * after reset) on LM3S6918 -- Michael Schwingen
1076 */
1077 uint32_t tmp;
1078 retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1079 if (retval != ERROR_OK)
1080 return retval;
1081 }
1082 }
1083
1084 target->state = TARGET_RESET;
1085 jtag_add_sleep(50000);
1086
1087 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1088
1089 if (target->reset_halt) {
1090 retval = target_halt(target);
1091 if (retval != ERROR_OK)
1092 return retval;
1093 }
1094
1095 return ERROR_OK;
1096 }
1097
1098 static int cortex_m_deassert_reset(struct target *target)
1099 {
1100 LOG_DEBUG("target->state: %s",
1101 target_state_name(target));
1102
1103 /* deassert reset lines */
1104 adapter_deassert_reset();
1105
1106 return ERROR_OK;
1107 }
1108
1109 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1110 {
1111 int retval;
1112 int fp_num = 0;
1113 uint32_t hilo;
1114 struct cortex_m_common *cortex_m = target_to_cm(target);
1115 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1116
1117 if (breakpoint->set) {
1118 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1119 return ERROR_OK;
1120 }
1121
1122 if (cortex_m->auto_bp_type)
1123 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1124
1125 if (breakpoint->type == BKPT_HARD) {
1126 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1127 fp_num++;
1128 if (fp_num >= cortex_m->fp_num_code) {
1129 LOG_ERROR("Can not find free FPB Comparator!");
1130 return ERROR_FAIL;
1131 }
1132 breakpoint->set = fp_num + 1;
1133 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1134 comparator_list[fp_num].used = 1;
1135 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1136 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1137 comparator_list[fp_num].fpcr_value);
1138 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1139 fp_num,
1140 comparator_list[fp_num].fpcr_value);
1141 if (!cortex_m->fpb_enabled) {
1142 LOG_DEBUG("FPB wasn't enabled, do it now");
1143 retval = cortex_m_enable_fpb(target);
1144 if (retval != ERROR_OK) {
1145 LOG_ERROR("Failed to enable the FPB");
1146 return retval;
1147 }
1148
1149 cortex_m->fpb_enabled = 1;
1150 }
1151 } else if (breakpoint->type == BKPT_SOFT) {
1152 uint8_t code[4];
1153
1154 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1155 * semihosting; don't use that. Otherwise the BKPT
1156 * parameter is arbitrary.
1157 */
1158 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1159 retval = target_read_memory(target,
1160 breakpoint->address & 0xFFFFFFFE,
1161 breakpoint->length, 1,
1162 breakpoint->orig_instr);
1163 if (retval != ERROR_OK)
1164 return retval;
1165 retval = target_write_memory(target,
1166 breakpoint->address & 0xFFFFFFFE,
1167 breakpoint->length, 1,
1168 code);
1169 if (retval != ERROR_OK)
1170 return retval;
1171 breakpoint->set = true;
1172 }
1173
1174 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1175 breakpoint->unique_id,
1176 (int)(breakpoint->type),
1177 breakpoint->address,
1178 breakpoint->length,
1179 breakpoint->set);
1180
1181 return ERROR_OK;
1182 }
1183
1184 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1185 {
1186 int retval;
1187 struct cortex_m_common *cortex_m = target_to_cm(target);
1188 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1189
1190 if (!breakpoint->set) {
1191 LOG_WARNING("breakpoint not set");
1192 return ERROR_OK;
1193 }
1194
1195 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1196 breakpoint->unique_id,
1197 (int)(breakpoint->type),
1198 breakpoint->address,
1199 breakpoint->length,
1200 breakpoint->set);
1201
1202 if (breakpoint->type == BKPT_HARD) {
1203 int fp_num = breakpoint->set - 1;
1204 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1205 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1206 return ERROR_OK;
1207 }
1208 comparator_list[fp_num].used = 0;
1209 comparator_list[fp_num].fpcr_value = 0;
1210 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1211 comparator_list[fp_num].fpcr_value);
1212 } else {
1213 /* restore original instruction (kept in target endianness) */
1214 if (breakpoint->length == 4) {
1215 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1216 breakpoint->orig_instr);
1217 if (retval != ERROR_OK)
1218 return retval;
1219 } else {
1220 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1221 breakpoint->orig_instr);
1222 if (retval != ERROR_OK)
1223 return retval;
1224 }
1225 }
1226 breakpoint->set = false;
1227
1228 return ERROR_OK;
1229 }
1230
1231 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1232 {
1233 struct cortex_m_common *cortex_m = target_to_cm(target);
1234
1235 if (cortex_m->auto_bp_type)
1236 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1237
1238 if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1239 if (breakpoint->type == BKPT_HARD) {
1240 LOG_INFO("flash patch comparator requested outside code memory region");
1241 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1242 }
1243
1244 if (breakpoint->type == BKPT_SOFT) {
1245 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1246 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1247 }
1248 }
1249
1250 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1251 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1252 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1253 }
1254
1255 if ((breakpoint->length != 2)) {
1256 LOG_INFO("only breakpoints of two bytes length supported");
1257 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1258 }
1259
1260 if (breakpoint->type == BKPT_HARD)
1261 cortex_m->fp_code_available--;
1262
1263 return cortex_m_set_breakpoint(target, breakpoint);
1264 }
1265
1266 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1267 {
1268 struct cortex_m_common *cortex_m = target_to_cm(target);
1269
1270 /* REVISIT why check? FBP can be updated with core running ... */
1271 if (target->state != TARGET_HALTED) {
1272 LOG_WARNING("target not halted");
1273 return ERROR_TARGET_NOT_HALTED;
1274 }
1275
1276 if (cortex_m->auto_bp_type)
1277 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1278
1279 if (breakpoint->set)
1280 cortex_m_unset_breakpoint(target, breakpoint);
1281
1282 if (breakpoint->type == BKPT_HARD)
1283 cortex_m->fp_code_available++;
1284
1285 return ERROR_OK;
1286 }
1287
1288 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1289 {
1290 int dwt_num = 0;
1291 uint32_t mask, temp;
1292 struct cortex_m_common *cortex_m = target_to_cm(target);
1293
1294 /* watchpoint params were validated earlier */
1295 mask = 0;
1296 temp = watchpoint->length;
1297 while (temp) {
1298 temp >>= 1;
1299 mask++;
1300 }
1301 mask--;
1302
1303 /* REVISIT Don't fully trust these "not used" records ... users
1304 * may set up breakpoints by hand, e.g. dual-address data value
1305 * watchpoint using comparator #1; comparator #0 matching cycle
1306 * count; send data trace info through ITM and TPIU; etc
1307 */
1308 struct cortex_m_dwt_comparator *comparator;
1309
1310 for (comparator = cortex_m->dwt_comparator_list;
1311 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1312 comparator++, dwt_num++)
1313 continue;
1314 if (dwt_num >= cortex_m->dwt_num_comp) {
1315 LOG_ERROR("Can not find free DWT Comparator");
1316 return ERROR_FAIL;
1317 }
1318 comparator->used = 1;
1319 watchpoint->set = dwt_num + 1;
1320
1321 comparator->comp = watchpoint->address;
1322 target_write_u32(target, comparator->dwt_comparator_address + 0,
1323 comparator->comp);
1324
1325 comparator->mask = mask;
1326 target_write_u32(target, comparator->dwt_comparator_address + 4,
1327 comparator->mask);
1328
1329 switch (watchpoint->rw) {
1330 case WPT_READ:
1331 comparator->function = 5;
1332 break;
1333 case WPT_WRITE:
1334 comparator->function = 6;
1335 break;
1336 case WPT_ACCESS:
1337 comparator->function = 7;
1338 break;
1339 }
1340 target_write_u32(target, comparator->dwt_comparator_address + 8,
1341 comparator->function);
1342
1343 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1344 watchpoint->unique_id, dwt_num,
1345 (unsigned) comparator->comp,
1346 (unsigned) comparator->mask,
1347 (unsigned) comparator->function);
1348 return ERROR_OK;
1349 }
1350
1351 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1352 {
1353 struct cortex_m_common *cortex_m = target_to_cm(target);
1354 struct cortex_m_dwt_comparator *comparator;
1355 int dwt_num;
1356
1357 if (!watchpoint->set) {
1358 LOG_WARNING("watchpoint (wpid: %d) not set",
1359 watchpoint->unique_id);
1360 return ERROR_OK;
1361 }
1362
1363 dwt_num = watchpoint->set - 1;
1364
1365 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1366 watchpoint->unique_id, dwt_num,
1367 (unsigned) watchpoint->address);
1368
1369 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1370 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1371 return ERROR_OK;
1372 }
1373
1374 comparator = cortex_m->dwt_comparator_list + dwt_num;
1375 comparator->used = 0;
1376 comparator->function = 0;
1377 target_write_u32(target, comparator->dwt_comparator_address + 8,
1378 comparator->function);
1379
1380 watchpoint->set = false;
1381
1382 return ERROR_OK;
1383 }
1384
1385 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1386 {
1387 struct cortex_m_common *cortex_m = target_to_cm(target);
1388
1389 if (cortex_m->dwt_comp_available < 1) {
1390 LOG_DEBUG("no comparators?");
1391 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1392 }
1393
1394 /* hardware doesn't support data value masking */
1395 if (watchpoint->mask != ~(uint32_t)0) {
1396 LOG_DEBUG("watchpoint value masks not supported");
1397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1398 }
1399
1400 /* hardware allows address masks of up to 32K */
1401 unsigned mask;
1402
1403 for (mask = 0; mask < 16; mask++) {
1404 if ((1u << mask) == watchpoint->length)
1405 break;
1406 }
1407 if (mask == 16) {
1408 LOG_DEBUG("unsupported watchpoint length");
1409 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1410 }
1411 if (watchpoint->address & ((1 << mask) - 1)) {
1412 LOG_DEBUG("watchpoint address is unaligned");
1413 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1414 }
1415
1416 /* Caller doesn't seem to be able to describe watching for data
1417 * values of zero; that flags "no value".
1418 *
1419 * REVISIT This DWT may well be able to watch for specific data
1420 * values. Requires comparator #1 to set DATAVMATCH and match
1421 * the data, and another comparator (DATAVADDR0) matching addr.
1422 */
1423 if (watchpoint->value) {
1424 LOG_DEBUG("data value watchpoint not YET supported");
1425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1426 }
1427
1428 cortex_m->dwt_comp_available--;
1429 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1430
1431 return ERROR_OK;
1432 }
1433
1434 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1435 {
1436 struct cortex_m_common *cortex_m = target_to_cm(target);
1437
1438 /* REVISIT why check? DWT can be updated with core running ... */
1439 if (target->state != TARGET_HALTED) {
1440 LOG_WARNING("target not halted");
1441 return ERROR_TARGET_NOT_HALTED;
1442 }
1443
1444 if (watchpoint->set)
1445 cortex_m_unset_watchpoint(target, watchpoint);
1446
1447 cortex_m->dwt_comp_available++;
1448 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1449
1450 return ERROR_OK;
1451 }
1452
1453 void cortex_m_enable_watchpoints(struct target *target)
1454 {
1455 struct watchpoint *watchpoint = target->watchpoints;
1456
1457 /* set any pending watchpoints */
1458 while (watchpoint) {
1459 if (!watchpoint->set)
1460 cortex_m_set_watchpoint(target, watchpoint);
1461 watchpoint = watchpoint->next;
1462 }
1463 }
1464
1465 static int cortex_m_load_core_reg_u32(struct target *target,
1466 uint32_t num, uint32_t *value)
1467 {
1468 int retval;
1469
1470 /* NOTE: we "know" here that the register identifiers used
1471 * in the v7m header match the Cortex-M3 Debug Core Register
1472 * Selector values for R0..R15, xPSR, MSP, and PSP.
1473 */
1474 switch (num) {
1475 case 0 ... 18:
1476 /* read a normal core register */
1477 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1478
1479 if (retval != ERROR_OK) {
1480 LOG_ERROR("JTAG failure %i", retval);
1481 return ERROR_JTAG_DEVICE_ERROR;
1482 }
1483 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1484 break;
1485
1486 case ARMV7M_PRIMASK:
1487 case ARMV7M_BASEPRI:
1488 case ARMV7M_FAULTMASK:
1489 case ARMV7M_CONTROL:
1490 /* Cortex-M3 packages these four registers as bitfields
1491 * in one Debug Core register. So say r0 and r2 docs;
1492 * it was removed from r1 docs, but still works.
1493 */
1494 cortexm_dap_read_coreregister_u32(target, value, 20);
1495
1496 switch (num) {
1497 case ARMV7M_PRIMASK:
1498 *value = buf_get_u32((uint8_t *)value, 0, 1);
1499 break;
1500
1501 case ARMV7M_BASEPRI:
1502 *value = buf_get_u32((uint8_t *)value, 8, 8);
1503 break;
1504
1505 case ARMV7M_FAULTMASK:
1506 *value = buf_get_u32((uint8_t *)value, 16, 1);
1507 break;
1508
1509 case ARMV7M_CONTROL:
1510 *value = buf_get_u32((uint8_t *)value, 24, 2);
1511 break;
1512 }
1513
1514 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1515 break;
1516
1517 default:
1518 return ERROR_COMMAND_SYNTAX_ERROR;
1519 }
1520
1521 return ERROR_OK;
1522 }
1523
1524 static int cortex_m_store_core_reg_u32(struct target *target,
1525 uint32_t num, uint32_t value)
1526 {
1527 int retval;
1528 uint32_t reg;
1529 struct armv7m_common *armv7m = target_to_armv7m(target);
1530
1531 /* NOTE: we "know" here that the register identifiers used
1532 * in the v7m header match the Cortex-M3 Debug Core Register
1533 * Selector values for R0..R15, xPSR, MSP, and PSP.
1534 */
1535 switch (num) {
1536 case 0 ... 18:
1537 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1538 if (retval != ERROR_OK) {
1539 struct reg *r;
1540
1541 LOG_ERROR("JTAG failure");
1542 r = armv7m->arm.core_cache->reg_list + num;
1543 r->dirty = r->valid;
1544 return ERROR_JTAG_DEVICE_ERROR;
1545 }
1546 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1547 break;
1548
1549 case ARMV7M_PRIMASK:
1550 case ARMV7M_BASEPRI:
1551 case ARMV7M_FAULTMASK:
1552 case ARMV7M_CONTROL:
1553 /* Cortex-M3 packages these four registers as bitfields
1554 * in one Debug Core register. So say r0 and r2 docs;
1555 * it was removed from r1 docs, but still works.
1556 */
1557 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1558
1559 switch (num) {
1560 case ARMV7M_PRIMASK:
1561 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1562 break;
1563
1564 case ARMV7M_BASEPRI:
1565 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1566 break;
1567
1568 case ARMV7M_FAULTMASK:
1569 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1570 break;
1571
1572 case ARMV7M_CONTROL:
1573 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1574 break;
1575 }
1576
1577 cortexm_dap_write_coreregister_u32(target, reg, 20);
1578
1579 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1580 break;
1581
1582 default:
1583 return ERROR_COMMAND_SYNTAX_ERROR;
1584 }
1585
1586 return ERROR_OK;
1587 }
1588
1589 static int cortex_m_read_memory(struct target *target, uint32_t address,
1590 uint32_t size, uint32_t count, uint8_t *buffer)
1591 {
1592 struct armv7m_common *armv7m = target_to_armv7m(target);
1593 struct adiv5_dap *swjdp = armv7m->arm.dap;
1594
1595 if (armv7m->arm.is_armv6m) {
1596 /* armv6m does not handle unaligned memory access */
1597 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1598 return ERROR_TARGET_UNALIGNED_ACCESS;
1599 }
1600
1601 return mem_ap_read(swjdp, buffer, size, count, address, true);
1602 }
1603
1604 static int cortex_m_write_memory(struct target *target, uint32_t address,
1605 uint32_t size, uint32_t count, const uint8_t *buffer)
1606 {
1607 struct armv7m_common *armv7m = target_to_armv7m(target);
1608 struct adiv5_dap *swjdp = armv7m->arm.dap;
1609
1610 if (armv7m->arm.is_armv6m) {
1611 /* armv6m does not handle unaligned memory access */
1612 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1613 return ERROR_TARGET_UNALIGNED_ACCESS;
1614 }
1615
1616 return mem_ap_write(swjdp, buffer, size, count, address, true);
1617 }
1618
1619 static int cortex_m_init_target(struct command_context *cmd_ctx,
1620 struct target *target)
1621 {
1622 armv7m_build_reg_cache(target);
1623 return ERROR_OK;
1624 }
1625
1626 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1627 * on r/w if the core is not running, and clear on resume or reset ... or
1628 * at least, in a post_restore_context() method.
1629 */
1630
1631 struct dwt_reg_state {
1632 struct target *target;
1633 uint32_t addr;
1634 uint32_t value; /* scratch/cache */
1635 };
1636
1637 static int cortex_m_dwt_get_reg(struct reg *reg)
1638 {
1639 struct dwt_reg_state *state = reg->arch_info;
1640
1641 return target_read_u32(state->target, state->addr, &state->value);
1642 }
1643
1644 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1645 {
1646 struct dwt_reg_state *state = reg->arch_info;
1647
1648 return target_write_u32(state->target, state->addr,
1649 buf_get_u32(buf, 0, reg->size));
1650 }
1651
1652 struct dwt_reg {
1653 uint32_t addr;
1654 char *name;
1655 unsigned size;
1656 };
1657
1658 static struct dwt_reg dwt_base_regs[] = {
1659 { DWT_CTRL, "dwt_ctrl", 32, },
1660 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1661 * increments while the core is asleep.
1662 */
1663 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1664 /* plus some 8 bit counters, useful for profiling with TPIU */
1665 };
1666
1667 static struct dwt_reg dwt_comp[] = {
1668 #define DWT_COMPARATOR(i) \
1669 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1670 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1671 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1672 DWT_COMPARATOR(0),
1673 DWT_COMPARATOR(1),
1674 DWT_COMPARATOR(2),
1675 DWT_COMPARATOR(3),
1676 #undef DWT_COMPARATOR
1677 };
1678
1679 static const struct reg_arch_type dwt_reg_type = {
1680 .get = cortex_m_dwt_get_reg,
1681 .set = cortex_m_dwt_set_reg,
1682 };
1683
1684 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1685 {
1686 struct dwt_reg_state *state;
1687
1688 state = calloc(1, sizeof *state);
1689 if (!state)
1690 return;
1691 state->addr = d->addr;
1692 state->target = t;
1693
1694 r->name = d->name;
1695 r->size = d->size;
1696 r->value = &state->value;
1697 r->arch_info = state;
1698 r->type = &dwt_reg_type;
1699 }
1700
1701 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1702 {
1703 uint32_t dwtcr;
1704 struct reg_cache *cache;
1705 struct cortex_m_dwt_comparator *comparator;
1706 int reg, i;
1707
1708 target_read_u32(target, DWT_CTRL, &dwtcr);
1709 if (!dwtcr) {
1710 LOG_DEBUG("no DWT");
1711 return;
1712 }
1713
1714 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1715 cm->dwt_comp_available = cm->dwt_num_comp;
1716 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1717 sizeof(struct cortex_m_dwt_comparator));
1718 if (!cm->dwt_comparator_list) {
1719 fail0:
1720 cm->dwt_num_comp = 0;
1721 LOG_ERROR("out of mem");
1722 return;
1723 }
1724
1725 cache = calloc(1, sizeof *cache);
1726 if (!cache) {
1727 fail1:
1728 free(cm->dwt_comparator_list);
1729 goto fail0;
1730 }
1731 cache->name = "Cortex-M DWT registers";
1732 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1733 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1734 if (!cache->reg_list) {
1735 free(cache);
1736 goto fail1;
1737 }
1738
1739 for (reg = 0; reg < 2; reg++)
1740 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1741 dwt_base_regs + reg);
1742
1743 comparator = cm->dwt_comparator_list;
1744 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1745 int j;
1746
1747 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1748 for (j = 0; j < 3; j++, reg++)
1749 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1750 dwt_comp + 3 * i + j);
1751
1752 /* make sure we clear any watchpoints enabled on the target */
1753 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1754 }
1755
1756 *register_get_last_cache_p(&target->reg_cache) = cache;
1757 cm->dwt_cache = cache;
1758
1759 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1760 dwtcr, cm->dwt_num_comp,
1761 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1762
1763 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1764 * implement single-address data value watchpoints ... so we
1765 * won't need to check it later, when asked to set one up.
1766 */
1767 }
1768
1769 #define MVFR0 0xe000ef40
1770 #define MVFR1 0xe000ef44
1771
1772 #define MVFR0_DEFAULT_M4 0x10110021
1773 #define MVFR1_DEFAULT_M4 0x11000011
1774
1775 int cortex_m_examine(struct target *target)
1776 {
1777 int retval;
1778 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1779 int i;
1780 struct cortex_m_common *cortex_m = target_to_cm(target);
1781 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1782 struct armv7m_common *armv7m = target_to_armv7m(target);
1783
1784 /* stlink shares the examine handler but does not support
1785 * all its calls */
1786 if (!armv7m->stlink) {
1787 retval = ahbap_debugport_init(swjdp);
1788 if (retval != ERROR_OK)
1789 return retval;
1790 }
1791
1792 if (!target_was_examined(target)) {
1793 target_set_examined(target);
1794
1795 /* Read from Device Identification Registers */
1796 retval = target_read_u32(target, CPUID, &cpuid);
1797 if (retval != ERROR_OK)
1798 return retval;
1799
1800 /* Get CPU Type */
1801 i = (cpuid >> 4) & 0xf;
1802
1803 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1804 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1805 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1806
1807 /* test for floating point feature on cortex-m4 */
1808 if (i == 4) {
1809 target_read_u32(target, MVFR0, &mvfr0);
1810 target_read_u32(target, MVFR1, &mvfr1);
1811
1812 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
1813 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
1814 armv7m->fp_feature = FPv4_SP;
1815 }
1816 } else if (i == 0) {
1817 /* Cortex-M0 does not support unaligned memory access */
1818 armv7m->arm.is_armv6m = true;
1819 }
1820
1821 if (i == 4 || i == 3) {
1822 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1823 armv7m->dap.tar_autoincr_block = (1 << 12);
1824 }
1825
1826 /* NOTE: FPB and DWT are both optional. */
1827
1828 /* Setup FPB */
1829 target_read_u32(target, FP_CTRL, &fpcr);
1830 cortex_m->auto_bp_type = 1;
1831 /* bits [14:12] and [7:4] */
1832 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
1833 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
1834 cortex_m->fp_code_available = cortex_m->fp_num_code;
1835 cortex_m->fp_comparator_list = calloc(
1836 cortex_m->fp_num_code + cortex_m->fp_num_lit,
1837 sizeof(struct cortex_m_fp_comparator));
1838 cortex_m->fpb_enabled = fpcr & 1;
1839 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
1840 cortex_m->fp_comparator_list[i].type =
1841 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1842 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1843
1844 /* make sure we clear any breakpoints enabled on the target */
1845 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
1846 }
1847 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
1848 fpcr,
1849 cortex_m->fp_num_code,
1850 cortex_m->fp_num_lit);
1851
1852 /* Setup DWT */
1853 cortex_m_dwt_setup(cortex_m, target);
1854
1855 /* These hardware breakpoints only work for code in flash! */
1856 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1857 target_name(target),
1858 cortex_m->fp_num_code,
1859 cortex_m->dwt_num_comp);
1860 }
1861
1862 return ERROR_OK;
1863 }
1864
1865 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
1866 {
1867 struct armv7m_common *armv7m = target_to_armv7m(target);
1868 struct adiv5_dap *swjdp = armv7m->arm.dap;
1869 uint16_t dcrdr;
1870 uint8_t buf[2];
1871 int retval;
1872
1873 retval = mem_ap_read(swjdp, buf, 2, 1, DCB_DCRDR, false);
1874 if (retval != ERROR_OK)
1875 return retval;
1876
1877 dcrdr = target_buffer_get_u16(target, buf);
1878 *ctrl = (uint8_t)dcrdr;
1879 *value = (uint8_t)(dcrdr >> 8);
1880
1881 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1882
1883 /* write ack back to software dcc register
1884 * signify we have read data */
1885 if (dcrdr & (1 << 0)) {
1886 target_buffer_set_u16(target, buf, 0);
1887 retval = mem_ap_write(swjdp, buf, 2, 1, DCB_DCRDR, false);
1888 if (retval != ERROR_OK)
1889 return retval;
1890 }
1891
1892 return ERROR_OK;
1893 }
1894
1895 static int cortex_m_target_request_data(struct target *target,
1896 uint32_t size, uint8_t *buffer)
1897 {
1898 uint8_t data;
1899 uint8_t ctrl;
1900 uint32_t i;
1901
1902 for (i = 0; i < (size * 4); i++) {
1903 cortex_m_dcc_read(target, &data, &ctrl);
1904 buffer[i] = data;
1905 }
1906
1907 return ERROR_OK;
1908 }
1909
1910 static int cortex_m_handle_target_request(void *priv)
1911 {
1912 struct target *target = priv;
1913 if (!target_was_examined(target))
1914 return ERROR_OK;
1915
1916 if (!target->dbg_msg_enabled)
1917 return ERROR_OK;
1918
1919 if (target->state == TARGET_RUNNING) {
1920 uint8_t data;
1921 uint8_t ctrl;
1922
1923 cortex_m_dcc_read(target, &data, &ctrl);
1924
1925 /* check if we have data */
1926 if (ctrl & (1 << 0)) {
1927 uint32_t request;
1928
1929 /* we assume target is quick enough */
1930 request = data;
1931 cortex_m_dcc_read(target, &data, &ctrl);
1932 request |= (data << 8);
1933 cortex_m_dcc_read(target, &data, &ctrl);
1934 request |= (data << 16);
1935 cortex_m_dcc_read(target, &data, &ctrl);
1936 request |= (data << 24);
1937 target_request(target, request);
1938 }
1939 }
1940
1941 return ERROR_OK;
1942 }
1943
1944 static int cortex_m_init_arch_info(struct target *target,
1945 struct cortex_m_common *cortex_m, struct jtag_tap *tap)
1946 {
1947 int retval;
1948 struct armv7m_common *armv7m = &cortex_m->armv7m;
1949
1950 armv7m_init_arch_info(target, armv7m);
1951
1952 /* prepare JTAG information for the new target */
1953 cortex_m->jtag_info.tap = tap;
1954 cortex_m->jtag_info.scann_size = 4;
1955
1956 /* default reset mode is to use srst if fitted
1957 * if not it will use CORTEX_M3_RESET_VECTRESET */
1958 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
1959
1960 armv7m->arm.dap = &armv7m->dap;
1961
1962 /* Leave (only) generic DAP stuff for debugport_init(); */
1963 armv7m->dap.jtag_info = &cortex_m->jtag_info;
1964 armv7m->dap.memaccess_tck = 8;
1965
1966 /* Cortex-M3/M4 has 4096 bytes autoincrement range
1967 * but set a safe default to 1024 to support Cortex-M0
1968 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
1969 armv7m->dap.tar_autoincr_block = (1 << 10);
1970
1971 /* register arch-specific functions */
1972 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
1973
1974 armv7m->post_debug_entry = NULL;
1975
1976 armv7m->pre_restore_context = NULL;
1977
1978 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
1979 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
1980
1981 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
1982
1983 retval = arm_jtag_setup_connection(&cortex_m->jtag_info);
1984 if (retval != ERROR_OK)
1985 return retval;
1986
1987 return ERROR_OK;
1988 }
1989
1990 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
1991 {
1992 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
1993
1994 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
1995 cortex_m_init_arch_info(target, cortex_m, target->tap);
1996
1997 return ERROR_OK;
1998 }
1999
2000 /*--------------------------------------------------------------------------*/
2001
2002 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2003 struct cortex_m_common *cm)
2004 {
2005 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2006 command_print(cmd_ctx, "target is not a Cortex-M");
2007 return ERROR_TARGET_INVALID;
2008 }
2009 return ERROR_OK;
2010 }
2011
2012 /*
2013 * Only stuff below this line should need to verify that its target
2014 * is a Cortex-M3. Everything else should have indirected through the
2015 * cortexm3_target structure, which is only used with CM3 targets.
2016 */
2017
2018 static const struct {
2019 char name[10];
2020 unsigned mask;
2021 } vec_ids[] = {
2022 { "hard_err", VC_HARDERR, },
2023 { "int_err", VC_INTERR, },
2024 { "bus_err", VC_BUSERR, },
2025 { "state_err", VC_STATERR, },
2026 { "chk_err", VC_CHKERR, },
2027 { "nocp_err", VC_NOCPERR, },
2028 { "mm_err", VC_MMERR, },
2029 { "reset", VC_CORERESET, },
2030 };
2031
2032 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2033 {
2034 struct target *target = get_current_target(CMD_CTX);
2035 struct cortex_m_common *cortex_m = target_to_cm(target);
2036 struct armv7m_common *armv7m = &cortex_m->armv7m;
2037 struct adiv5_dap *swjdp = armv7m->arm.dap;
2038 uint32_t demcr = 0;
2039 int retval;
2040
2041 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2042 if (retval != ERROR_OK)
2043 return retval;
2044
2045 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2046 if (retval != ERROR_OK)
2047 return retval;
2048
2049 if (CMD_ARGC > 0) {
2050 unsigned catch = 0;
2051
2052 if (CMD_ARGC == 1) {
2053 if (strcmp(CMD_ARGV[0], "all") == 0) {
2054 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2055 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2056 | VC_MMERR | VC_CORERESET;
2057 goto write;
2058 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2059 goto write;
2060 }
2061 while (CMD_ARGC-- > 0) {
2062 unsigned i;
2063 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2064 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2065 continue;
2066 catch |= vec_ids[i].mask;
2067 break;
2068 }
2069 if (i == ARRAY_SIZE(vec_ids)) {
2070 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2071 return ERROR_COMMAND_SYNTAX_ERROR;
2072 }
2073 }
2074 write:
2075 /* For now, armv7m->demcr only stores vector catch flags. */
2076 armv7m->demcr = catch;
2077
2078 demcr &= ~0xffff;
2079 demcr |= catch;
2080
2081 /* write, but don't assume it stuck (why not??) */
2082 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2083 if (retval != ERROR_OK)
2084 return retval;
2085 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2086 if (retval != ERROR_OK)
2087 return retval;
2088
2089 /* FIXME be sure to clear DEMCR on clean server shutdown.
2090 * Otherwise the vector catch hardware could fire when there's
2091 * no debugger hooked up, causing much confusion...
2092 */
2093 }
2094
2095 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2096 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2097 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2098 }
2099
2100 return ERROR_OK;
2101 }
2102
2103 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2104 {
2105 struct target *target = get_current_target(CMD_CTX);
2106 struct cortex_m_common *cortex_m = target_to_cm(target);
2107 int retval;
2108
2109 static const Jim_Nvp nvp_maskisr_modes[] = {
2110 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2111 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2112 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2113 { .name = NULL, .value = -1 },
2114 };
2115 const Jim_Nvp *n;
2116
2117
2118 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2119 if (retval != ERROR_OK)
2120 return retval;
2121
2122 if (target->state != TARGET_HALTED) {
2123 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2124 return ERROR_OK;
2125 }
2126
2127 if (CMD_ARGC > 0) {
2128 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2129 if (n->name == NULL)
2130 return ERROR_COMMAND_SYNTAX_ERROR;
2131 cortex_m->isrmasking_mode = n->value;
2132
2133
2134 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2135 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2136 else
2137 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2138 }
2139
2140 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2141 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2142
2143 return ERROR_OK;
2144 }
2145
2146 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2147 {
2148 struct target *target = get_current_target(CMD_CTX);
2149 struct cortex_m_common *cortex_m = target_to_cm(target);
2150 int retval;
2151 char *reset_config;
2152
2153 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2154 if (retval != ERROR_OK)
2155 return retval;
2156
2157 if (CMD_ARGC > 0) {
2158 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2159 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2160 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2161 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2162 }
2163
2164 switch (cortex_m->soft_reset_config) {
2165 case CORTEX_M_RESET_SYSRESETREQ:
2166 reset_config = "sysresetreq";
2167 break;
2168
2169 case CORTEX_M_RESET_VECTRESET:
2170 reset_config = "vectreset";
2171 break;
2172
2173 default:
2174 reset_config = "unknown";
2175 break;
2176 }
2177
2178 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2179
2180 return ERROR_OK;
2181 }
2182
2183 static const struct command_registration cortex_m_exec_command_handlers[] = {
2184 {
2185 .name = "maskisr",
2186 .handler = handle_cortex_m_mask_interrupts_command,
2187 .mode = COMMAND_EXEC,
2188 .help = "mask cortex_m interrupts",
2189 .usage = "['auto'|'on'|'off']",
2190 },
2191 {
2192 .name = "vector_catch",
2193 .handler = handle_cortex_m_vector_catch_command,
2194 .mode = COMMAND_EXEC,
2195 .help = "configure hardware vectors to trigger debug entry",
2196 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2197 },
2198 {
2199 .name = "reset_config",
2200 .handler = handle_cortex_m_reset_config_command,
2201 .mode = COMMAND_ANY,
2202 .help = "configure software reset handling",
2203 .usage = "['srst'|'sysresetreq'|'vectreset']",
2204 },
2205 COMMAND_REGISTRATION_DONE
2206 };
2207 static const struct command_registration cortex_m_command_handlers[] = {
2208 {
2209 .chain = armv7m_command_handlers,
2210 },
2211 {
2212 .name = "cortex_m",
2213 .mode = COMMAND_EXEC,
2214 .help = "Cortex-M command group",
2215 .usage = "",
2216 .chain = cortex_m_exec_command_handlers,
2217 },
2218 COMMAND_REGISTRATION_DONE
2219 };
2220
2221 struct target_type cortexm_target = {
2222 .name = "cortex_m",
2223 .deprecated_name = "cortex_m3",
2224
2225 .poll = cortex_m_poll,
2226 .arch_state = armv7m_arch_state,
2227
2228 .target_request_data = cortex_m_target_request_data,
2229
2230 .halt = cortex_m_halt,
2231 .resume = cortex_m_resume,
2232 .step = cortex_m_step,
2233
2234 .assert_reset = cortex_m_assert_reset,
2235 .deassert_reset = cortex_m_deassert_reset,
2236 .soft_reset_halt = cortex_m_soft_reset_halt,
2237
2238 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2239
2240 .read_memory = cortex_m_read_memory,
2241 .write_memory = cortex_m_write_memory,
2242 .checksum_memory = armv7m_checksum_memory,
2243 .blank_check_memory = armv7m_blank_check_memory,
2244
2245 .run_algorithm = armv7m_run_algorithm,
2246 .start_algorithm = armv7m_start_algorithm,
2247 .wait_algorithm = armv7m_wait_algorithm,
2248
2249 .add_breakpoint = cortex_m_add_breakpoint,
2250 .remove_breakpoint = cortex_m_remove_breakpoint,
2251 .add_watchpoint = cortex_m_add_watchpoint,
2252 .remove_watchpoint = cortex_m_remove_watchpoint,
2253
2254 .commands = cortex_m_command_handlers,
2255 .target_create = cortex_m_target_create,
2256 .init_target = cortex_m_init_target,
2257 .examine = cortex_m_examine,
2258 };
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