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flash: stm32f1x: write option bytes using the loader
[openocd.git] / src / flash / nor / stm32f1x.c
blob58b7ba16acf7f24e3f288d50010bd9c0eaae65bb
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 /* timeout values */
106
107 #define FLASH_WRITE_TIMEOUT 10
108 #define FLASH_ERASE_TIMEOUT 100
109
110 struct stm32x_options {
111 uint16_t RDP;
112 uint16_t user_options;
113 uint16_t protection[4];
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 int probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 uint32_t register_base;
124 };
125
126 static int stm32x_mass_erase(struct flash_bank *bank);
127 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
128 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
129 uint32_t offset, uint32_t count);
130
131 /* flash bank stm32x <base> <size> 0 0 <target#>
132 */
133 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
134 {
135 struct stm32x_flash_bank *stm32x_info;
136
137 if (CMD_ARGC < 6)
138 return ERROR_COMMAND_SYNTAX_ERROR;
139
140 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
141
142 bank->driver_priv = stm32x_info;
143 stm32x_info->probed = 0;
144 stm32x_info->has_dual_banks = false;
145 stm32x_info->register_base = FLASH_REG_BASE_B0;
146
147 return ERROR_OK;
148 }
149
150 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
151 {
152 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
153 return reg + stm32x_info->register_base;
154 }
155
156 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
157 {
158 struct target *target = bank->target;
159 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
160 }
161
162 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
163 {
164 struct target *target = bank->target;
165 uint32_t status;
166 int retval = ERROR_OK;
167
168 /* wait for busy to clear */
169 for (;;) {
170 retval = stm32x_get_flash_status(bank, &status);
171 if (retval != ERROR_OK)
172 return retval;
173 LOG_DEBUG("status: 0x%" PRIx32 "", status);
174 if ((status & FLASH_BSY) == 0)
175 break;
176 if (timeout-- <= 0) {
177 LOG_ERROR("timed out waiting for flash");
178 return ERROR_FAIL;
179 }
180 alive_sleep(1);
181 }
182
183 if (status & FLASH_WRPRTERR) {
184 LOG_ERROR("stm32x device protected");
185 retval = ERROR_FAIL;
186 }
187
188 if (status & FLASH_PGERR) {
189 LOG_ERROR("stm32x device programming failed");
190 retval = ERROR_FAIL;
191 }
192
193 /* Clear but report errors */
194 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
195 /* If this operation fails, we ignore it and report the original
196 * retval
197 */
198 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
199 FLASH_WRPRTERR | FLASH_PGERR);
200 }
201 return retval;
202 }
203
204 int stm32x_check_operation_supported(struct flash_bank *bank)
205 {
206 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
207
208 /* if we have a dual flash bank device then
209 * we need to perform option byte stuff on bank0 only */
210 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
211 LOG_ERROR("Option Byte Operation's must use bank0");
212 return ERROR_FLASH_OPERATION_FAILED;
213 }
214
215 return ERROR_OK;
216 }
217
218 static int stm32x_read_options(struct flash_bank *bank)
219 {
220 uint32_t optiondata;
221 struct stm32x_flash_bank *stm32x_info = NULL;
222 struct target *target = bank->target;
223
224 stm32x_info = bank->driver_priv;
225
226 /* read current option bytes */
227 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
228 if (retval != ERROR_OK)
229 return retval;
230
231 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
232 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
233
234 if (optiondata & (1 << OPT_READOUT))
235 LOG_INFO("Device Security Bit Set");
236
237 /* each bit refers to a 4bank protection */
238 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
239 if (retval != ERROR_OK)
240 return retval;
241
242 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
243 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
244 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
245 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
246
247 return ERROR_OK;
248 }
249
250 static int stm32x_erase_options(struct flash_bank *bank)
251 {
252 struct stm32x_flash_bank *stm32x_info = NULL;
253 struct target *target = bank->target;
254
255 stm32x_info = bank->driver_priv;
256
257 /* read current options */
258 stm32x_read_options(bank);
259
260 /* unlock flash registers */
261 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
262 if (retval != ERROR_OK)
263 return retval;
264
265 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
266 if (retval != ERROR_OK)
267 return retval;
268
269 /* unlock option flash registers */
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
271 if (retval != ERROR_OK)
272 return retval;
273 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
274 if (retval != ERROR_OK)
275 return retval;
276
277 /* erase option bytes */
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
282 if (retval != ERROR_OK)
283 return retval;
284
285 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
286 if (retval != ERROR_OK)
287 return retval;
288
289 /* clear readout protection and complementary option bytes
290 * this will also force a device unlock if set */
291 stm32x_info->option_bytes.RDP = 0x5AA5;
292
293 return ERROR_OK;
294 }
295
296 static int stm32x_write_options(struct flash_bank *bank)
297 {
298 struct stm32x_flash_bank *stm32x_info = NULL;
299 struct target *target = bank->target;
300
301 stm32x_info = bank->driver_priv;
302
303 /* unlock flash registers */
304 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
305 if (retval != ERROR_OK)
306 return retval;
307 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
308 if (retval != ERROR_OK)
309 return retval;
310
311 /* unlock option flash registers */
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
313 if (retval != ERROR_OK)
314 return retval;
315 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
316 if (retval != ERROR_OK)
317 return retval;
318
319 /* program option bytes */
320 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
321 if (retval != ERROR_OK)
322 return retval;
323
324 uint8_t opt_bytes[16];
325
326 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
327 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
328 target_buffer_set_u16(target, opt_bytes + 4, 0x00FF);
329 target_buffer_set_u16(target, opt_bytes + 6, 0x00FF);
330 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
331 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
332 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
333 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
334
335 uint32_t offset = STM32_OB_RDP - bank->base;
336 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
337 if (retval != ERROR_OK) {
338 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
339 LOG_ERROR("working area required to erase options bytes");
340 return retval;
341 }
342
343 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
344 if (retval != ERROR_OK)
345 return retval;
346
347 return ERROR_OK;
348 }
349
350 static int stm32x_protect_check(struct flash_bank *bank)
351 {
352 struct target *target = bank->target;
353 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
354
355 uint32_t protection;
356 int i, s;
357 int num_bits;
358 int set;
359
360 if (target->state != TARGET_HALTED) {
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
363 }
364
365 int retval = stm32x_check_operation_supported(bank);
366 if (ERROR_OK != retval)
367 return retval;
368
369 /* medium density - each bit refers to a 4bank protection
370 * high density - each bit refers to a 2bank protection */
371 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
372 if (retval != ERROR_OK)
373 return retval;
374
375 /* medium density - each protection bit is for 4 * 1K pages
376 * high density - each protection bit is for 2 * 2K pages */
377 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
378
379 if (stm32x_info->ppage_size == 2) {
380 /* high density flash/connectivity line protection */
381
382 set = 1;
383
384 if (protection & (1 << 31))
385 set = 0;
386
387 /* bit 31 controls sector 62 - 255 protection for high density
388 * bit 31 controls sector 62 - 127 protection for connectivity line */
389 for (s = 62; s < bank->num_sectors; s++)
390 bank->sectors[s].is_protected = set;
391
392 if (bank->num_sectors > 61)
393 num_bits = 31;
394
395 for (i = 0; i < num_bits; i++) {
396 set = 1;
397
398 if (protection & (1 << i))
399 set = 0;
400
401 for (s = 0; s < stm32x_info->ppage_size; s++)
402 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
403 }
404 } else {
405 /* low/medium density flash protection */
406 for (i = 0; i < num_bits; i++) {
407 set = 1;
408
409 if (protection & (1 << i))
410 set = 0;
411
412 for (s = 0; s < stm32x_info->ppage_size; s++)
413 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
414 }
415 }
416
417 return ERROR_OK;
418 }
419
420 static int stm32x_erase(struct flash_bank *bank, int first, int last)
421 {
422 struct target *target = bank->target;
423 int i;
424
425 if (bank->target->state != TARGET_HALTED) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED;
428 }
429
430 if ((first == 0) && (last == (bank->num_sectors - 1)))
431 return stm32x_mass_erase(bank);
432
433 /* unlock flash registers */
434 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
435 if (retval != ERROR_OK)
436 return retval;
437 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
438 if (retval != ERROR_OK)
439 return retval;
440
441 for (i = first; i <= last; i++) {
442 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
443 if (retval != ERROR_OK)
444 return retval;
445 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
446 bank->base + bank->sectors[i].offset);
447 if (retval != ERROR_OK)
448 return retval;
449 retval = target_write_u32(target,
450 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
451 if (retval != ERROR_OK)
452 return retval;
453
454 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
455 if (retval != ERROR_OK)
456 return retval;
457
458 bank->sectors[i].is_erased = 1;
459 }
460
461 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
462 if (retval != ERROR_OK)
463 return retval;
464
465 return ERROR_OK;
466 }
467
468 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
469 {
470 struct stm32x_flash_bank *stm32x_info = NULL;
471 struct target *target = bank->target;
472 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
473 int i, reg, bit;
474 int status;
475 uint32_t protection;
476
477 stm32x_info = bank->driver_priv;
478
479 if (target->state != TARGET_HALTED) {
480 LOG_ERROR("Target not halted");
481 return ERROR_TARGET_NOT_HALTED;
482 }
483
484 int retval = stm32x_check_operation_supported(bank);
485 if (ERROR_OK != retval)
486 return retval;
487
488 if ((first % stm32x_info->ppage_size) != 0) {
489 LOG_WARNING("aligned start protect sector to a %d sector boundary",
490 stm32x_info->ppage_size);
491 first = first - (first % stm32x_info->ppage_size);
492 }
493 if (((last + 1) % stm32x_info->ppage_size) != 0) {
494 LOG_WARNING("aligned end protect sector to a %d sector boundary",
495 stm32x_info->ppage_size);
496 last++;
497 last = last - (last % stm32x_info->ppage_size);
498 last--;
499 }
500
501 /* medium density - each bit refers to a 4bank protection
502 * high density - each bit refers to a 2bank protection */
503 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
504 if (retval != ERROR_OK)
505 return retval;
506
507 prot_reg[0] = (uint16_t)protection;
508 prot_reg[1] = (uint16_t)(protection >> 8);
509 prot_reg[2] = (uint16_t)(protection >> 16);
510 prot_reg[3] = (uint16_t)(protection >> 24);
511
512 if (stm32x_info->ppage_size == 2) {
513 /* high density flash */
514
515 /* bit 7 controls sector 62 - 255 protection */
516 if (last > 61) {
517 if (set)
518 prot_reg[3] &= ~(1 << 7);
519 else
520 prot_reg[3] |= (1 << 7);
521 }
522
523 if (first > 61)
524 first = 62;
525 if (last > 61)
526 last = 61;
527
528 for (i = first; i <= last; i++) {
529 reg = (i / stm32x_info->ppage_size) / 8;
530 bit = (i / stm32x_info->ppage_size) - (reg * 8);
531
532 if (set)
533 prot_reg[reg] &= ~(1 << bit);
534 else
535 prot_reg[reg] |= (1 << bit);
536 }
537 } else {
538 /* medium density flash */
539 for (i = first; i <= last; i++) {
540 reg = (i / stm32x_info->ppage_size) / 8;
541 bit = (i / stm32x_info->ppage_size) - (reg * 8);
542
543 if (set)
544 prot_reg[reg] &= ~(1 << bit);
545 else
546 prot_reg[reg] |= (1 << bit);
547 }
548 }
549
550 status = stm32x_erase_options(bank);
551 if (status != ERROR_OK)
552 return status;
553
554 stm32x_info->option_bytes.protection[0] = prot_reg[0];
555 stm32x_info->option_bytes.protection[1] = prot_reg[1];
556 stm32x_info->option_bytes.protection[2] = prot_reg[2];
557 stm32x_info->option_bytes.protection[3] = prot_reg[3];
558
559 return stm32x_write_options(bank);
560 }
561
562 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
563 uint32_t offset, uint32_t count)
564 {
565 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
566 struct target *target = bank->target;
567 uint32_t buffer_size = 16384;
568 struct working_area *write_algorithm;
569 struct working_area *source;
570 uint32_t address = bank->base + offset;
571 struct reg_param reg_params[5];
572 struct armv7m_algorithm armv7m_info;
573 int retval = ERROR_OK;
574
575 /* see contrib/loaders/flash/stm32f1x.S for src */
576
577 static const uint8_t stm32x_flash_write_code[] = {
578 /* #define STM32_FLASH_SR_OFFSET 0x0C */
579 /* wait_fifo: */
580 0x16, 0x68, /* ldr r6, [r2, #0] */
581 0x00, 0x2e, /* cmp r6, #0 */
582 0x18, 0xd0, /* beq exit */
583 0x55, 0x68, /* ldr r5, [r2, #4] */
584 0xb5, 0x42, /* cmp r5, r6 */
585 0xf9, 0xd0, /* beq wait_fifo */
586 0x2e, 0x88, /* ldrh r6, [r5, #0] */
587 0x26, 0x80, /* strh r6, [r4, #0] */
588 0x02, 0x35, /* adds r5, #2 */
589 0x02, 0x34, /* adds r4, #2 */
590 /* busy: */
591 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
592 0x01, 0x27, /* movs r7, #1 */
593 0x3e, 0x42, /* tst r6, r7 */
594 0xfb, 0xd1, /* bne busy */
595 0x14, 0x27, /* movs r7, #0x14 */
596 0x3e, 0x42, /* tst r6, r7 */
597 0x08, 0xd1, /* bne error */
598 0x9d, 0x42, /* cmp r5, r3 */
599 0x01, 0xd3, /* bcc no_wrap */
600 0x15, 0x46, /* mov r5, r2 */
601 0x08, 0x35, /* adds r5, #8 */
602 /* no_wrap: */
603 0x55, 0x60, /* str r5, [r2, #4] */
604 0x01, 0x39, /* subs r1, r1, #1 */
605 0x00, 0x29, /* cmp r1, #0 */
606 0x02, 0xd0, /* beq exit */
607 0xe5, 0xe7, /* b wait_fifo */
608 /* error: */
609 0x00, 0x20, /* movs r0, #0 */
610 0x50, 0x60, /* str r0, [r2, #4] */
611 /* exit: */
612 0x30, 0x46, /* mov r0, r6 */
613 0x00, 0xbe, /* bkpt #0 */
614 };
615
616 /* flash write code */
617 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
618 &write_algorithm) != ERROR_OK) {
619 LOG_WARNING("no working area available, can't do block memory writes");
620 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
621 };
622
623 retval = target_write_buffer(target, write_algorithm->address,
624 sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
625 if (retval != ERROR_OK)
626 return retval;
627
628 /* memory buffer */
629 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
630 buffer_size /= 2;
631 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
632 if (buffer_size <= 256) {
633 /* we already allocated the writing code, but failed to get a
634 * buffer, free the algorithm */
635 target_free_working_area(target, write_algorithm);
636
637 LOG_WARNING("no large enough working area available, can't do block memory writes");
638 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
639 }
640 };
641
642 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
643 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
644 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
645 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
646 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
647
648 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
649 buf_set_u32(reg_params[1].value, 0, 32, count);
650 buf_set_u32(reg_params[2].value, 0, 32, source->address);
651 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
652 buf_set_u32(reg_params[4].value, 0, 32, address);
653
654 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
655 armv7m_info.core_mode = ARMV7M_MODE_ANY;
656
657 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
658 0, NULL,
659 5, reg_params,
660 source->address, source->size,
661 write_algorithm->address, 0,
662 &armv7m_info);
663
664 if (retval == ERROR_FLASH_OPERATION_FAILED) {
665 LOG_ERROR("flash write failed at address 0x%"PRIx32,
666 buf_get_u32(reg_params[4].value, 0, 32));
667
668 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
669 LOG_ERROR("flash memory not erased before writing");
670 /* Clear but report errors */
671 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
672 }
673
674 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
675 LOG_ERROR("flash memory write protected");
676 /* Clear but report errors */
677 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
678 }
679 }
680
681 target_free_working_area(target, source);
682 target_free_working_area(target, write_algorithm);
683
684 destroy_reg_param(&reg_params[0]);
685 destroy_reg_param(&reg_params[1]);
686 destroy_reg_param(&reg_params[2]);
687 destroy_reg_param(&reg_params[3]);
688 destroy_reg_param(&reg_params[4]);
689
690 return retval;
691 }
692
693 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
694 uint32_t offset, uint32_t count)
695 {
696 struct target *target = bank->target;
697 uint8_t *new_buffer = NULL;
698
699 if (bank->target->state != TARGET_HALTED) {
700 LOG_ERROR("Target not halted");
701 return ERROR_TARGET_NOT_HALTED;
702 }
703
704 if (offset & 0x1) {
705 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
706 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
707 }
708
709 /* If there's an odd number of bytes, the data has to be padded. Duplicate
710 * the buffer and use the normal code path with a single block write since
711 * it's probably cheaper than to special case the last odd write using
712 * discrete accesses. */
713 if (count & 1) {
714 new_buffer = malloc(count + 1);
715 if (new_buffer == NULL) {
716 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
717 return ERROR_FAIL;
718 }
719 LOG_INFO("odd number of bytes to write, padding with 0xff");
720 buffer = memcpy(new_buffer, buffer, count);
721 buffer[count++] = 0xff;
722 }
723
724 uint32_t words_remaining = count / 2;
725 int retval, retval2;
726
727 /* unlock flash registers */
728 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
729 if (retval != ERROR_OK)
730 goto cleanup;
731 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
732 if (retval != ERROR_OK)
733 goto cleanup;
734
735 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
736 if (retval != ERROR_OK)
737 goto cleanup;
738
739 /* try using a block write */
740 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
741
742 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
743 /* if block write failed (no sufficient working area),
744 * we use normal (slow) single halfword accesses */
745 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
746
747 while (words_remaining > 0) {
748 uint16_t value;
749 memcpy(&value, buffer, sizeof(uint16_t));
750
751 retval = target_write_u16(target, bank->base + offset, value);
752 if (retval != ERROR_OK)
753 goto reset_pg_and_lock;
754
755 retval = stm32x_wait_status_busy(bank, 5);
756 if (retval != ERROR_OK)
757 goto reset_pg_and_lock;
758
759 words_remaining--;
760 buffer += 2;
761 offset += 2;
762 }
763 }
764
765 reset_pg_and_lock:
766 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
767 if (retval == ERROR_OK)
768 retval = retval2;
769
770 cleanup:
771 if (new_buffer)
772 free(new_buffer);
773
774 return retval;
775 }
776
777 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
778 {
779 /* This check the device CPUID core register to detect
780 * the M0 from the M3 devices. */
781
782 struct target *target = bank->target;
783 uint32_t cpuid, device_id_register = 0;
784
785 /* Get the CPUID from the ARM Core
786 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
787 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
788 if (retval != ERROR_OK)
789 return retval;
790
791 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
792 /* 0xC20 is M0 devices */
793 device_id_register = 0x40015800;
794 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
795 /* 0xC23 is M3 devices */
796 device_id_register = 0xE0042000;
797 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
798 /* 0xC24 is M4 devices */
799 device_id_register = 0xE0042000;
800 } else {
801 LOG_ERROR("Cannot identify target as a stm32x");
802 return ERROR_FAIL;
803 }
804
805 /* read stm32 device id register */
806 retval = target_read_u32(target, device_id_register, device_id);
807 if (retval != ERROR_OK)
808 return retval;
809
810 return retval;
811 }
812
813 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
814 {
815 struct target *target = bank->target;
816 uint32_t cpuid, flash_size_reg;
817
818 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
819 if (retval != ERROR_OK)
820 return retval;
821
822 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
823 /* 0xC20 is M0 devices */
824 flash_size_reg = 0x1FFFF7CC;
825 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
826 /* 0xC23 is M3 devices */
827 flash_size_reg = 0x1FFFF7E0;
828 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
829 /* 0xC24 is M4 devices */
830 flash_size_reg = 0x1FFFF7CC;
831 } else {
832 LOG_ERROR("Cannot identify target as a stm32x");
833 return ERROR_FAIL;
834 }
835
836 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
837 if (retval != ERROR_OK)
838 return retval;
839
840 return retval;
841 }
842
843 static int stm32x_probe(struct flash_bank *bank)
844 {
845 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
846 int i;
847 uint16_t flash_size_in_kb;
848 uint16_t max_flash_size_in_kb;
849 uint32_t device_id;
850 int page_size;
851 uint32_t base_address = 0x08000000;
852
853 stm32x_info->probed = 0;
854 stm32x_info->register_base = FLASH_REG_BASE_B0;
855
856 /* read stm32 device id register */
857 int retval = stm32x_get_device_id(bank, &device_id);
858 if (retval != ERROR_OK)
859 return retval;
860
861 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
862
863 /* set page size, protection granularity and max flash size depending on family */
864 switch (device_id & 0xfff) {
865 case 0x410: /* medium density */
866 page_size = 1024;
867 stm32x_info->ppage_size = 4;
868 max_flash_size_in_kb = 128;
869 break;
870 case 0x412: /* low density */
871 page_size = 1024;
872 stm32x_info->ppage_size = 4;
873 max_flash_size_in_kb = 32;
874 break;
875 case 0x414: /* high density */
876 page_size = 2048;
877 stm32x_info->ppage_size = 2;
878 max_flash_size_in_kb = 512;
879 break;
880 case 0x418: /* connectivity line density */
881 page_size = 2048;
882 stm32x_info->ppage_size = 2;
883 max_flash_size_in_kb = 256;
884 break;
885 case 0x420: /* value line density */
886 page_size = 1024;
887 stm32x_info->ppage_size = 4;
888 max_flash_size_in_kb = 128;
889 break;
890 case 0x422: /* stm32f30x */
891 page_size = 2048;
892 stm32x_info->ppage_size = 2;
893 max_flash_size_in_kb = 256;
894 break;
895 case 0x428: /* value line High density */
896 page_size = 2048;
897 stm32x_info->ppage_size = 4;
898 max_flash_size_in_kb = 128;
899 break;
900 case 0x430: /* xl line density (dual flash banks) */
901 page_size = 2048;
902 stm32x_info->ppage_size = 2;
903 max_flash_size_in_kb = 1024;
904 stm32x_info->has_dual_banks = true;
905 break;
906 case 0x432: /* stm32f37x */
907 page_size = 2048;
908 stm32x_info->ppage_size = 2;
909 max_flash_size_in_kb = 256;
910 break;
911 case 0x440: /* stm32f0x */
912 page_size = 1024;
913 stm32x_info->ppage_size = 4;
914 max_flash_size_in_kb = 64;
915 break;
916 default:
917 LOG_WARNING("Cannot identify target as a STM32 family.");
918 return ERROR_FAIL;
919 }
920
921 /* get flash size from target. */
922 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
923
924 /* failed reading flash size or flash size invalid (early silicon),
925 * default to max target family */
926 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
927 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
928 max_flash_size_in_kb);
929 flash_size_in_kb = max_flash_size_in_kb;
930 }
931
932 if (stm32x_info->has_dual_banks) {
933 /* split reported size into matching bank */
934 if (bank->base != 0x08080000) {
935 /* bank 0 will be fixed 512k */
936 flash_size_in_kb = 512;
937 } else {
938 flash_size_in_kb -= 512;
939 /* bank1 also uses a register offset */
940 stm32x_info->register_base = FLASH_REG_BASE_B1;
941 base_address = 0x08080000;
942 }
943 }
944
945 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
946
947 /* did we assign flash size? */
948 assert(flash_size_in_kb != 0xffff);
949
950 /* calculate numbers of pages */
951 int num_pages = flash_size_in_kb * 1024 / page_size;
952
953 /* check that calculation result makes sense */
954 assert(num_pages > 0);
955
956 if (bank->sectors) {
957 free(bank->sectors);
958 bank->sectors = NULL;
959 }
960
961 bank->base = base_address;
962 bank->size = (num_pages * page_size);
963 bank->num_sectors = num_pages;
964 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
965
966 for (i = 0; i < num_pages; i++) {
967 bank->sectors[i].offset = i * page_size;
968 bank->sectors[i].size = page_size;
969 bank->sectors[i].is_erased = -1;
970 bank->sectors[i].is_protected = 1;
971 }
972
973 stm32x_info->probed = 1;
974
975 return ERROR_OK;
976 }
977
978 static int stm32x_auto_probe(struct flash_bank *bank)
979 {
980 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
981 if (stm32x_info->probed)
982 return ERROR_OK;
983 return stm32x_probe(bank);
984 }
985
986 #if 0
987 COMMAND_HANDLER(stm32x_handle_part_id_command)
988 {
989 return ERROR_OK;
990 }
991 #endif
992
993 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
994 {
995 uint32_t device_id;
996 int printed;
997
998 /* read stm32 device id register */
999 int retval = stm32x_get_device_id(bank, &device_id);
1000 if (retval != ERROR_OK)
1001 return retval;
1002
1003 if ((device_id & 0xfff) == 0x410) {
1004 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1005 buf += printed;
1006 buf_size -= printed;
1007
1008 switch (device_id >> 16) {
1009 case 0x0000:
1010 snprintf(buf, buf_size, "A");
1011 break;
1012
1013 case 0x2000:
1014 snprintf(buf, buf_size, "B");
1015 break;
1016
1017 case 0x2001:
1018 snprintf(buf, buf_size, "Z");
1019 break;
1020
1021 case 0x2003:
1022 snprintf(buf, buf_size, "Y");
1023 break;
1024
1025 default:
1026 snprintf(buf, buf_size, "unknown");
1027 break;
1028 }
1029 } else if ((device_id & 0xfff) == 0x412) {
1030 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1031 buf += printed;
1032 buf_size -= printed;
1033
1034 switch (device_id >> 16) {
1035 case 0x1000:
1036 snprintf(buf, buf_size, "A");
1037 break;
1038
1039 default:
1040 snprintf(buf, buf_size, "unknown");
1041 break;
1042 }
1043 } else if ((device_id & 0xfff) == 0x414) {
1044 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1045 buf += printed;
1046 buf_size -= printed;
1047
1048 switch (device_id >> 16) {
1049 case 0x1000:
1050 snprintf(buf, buf_size, "A");
1051 break;
1052
1053 case 0x1001:
1054 snprintf(buf, buf_size, "Z");
1055 break;
1056
1057 default:
1058 snprintf(buf, buf_size, "unknown");
1059 break;
1060 }
1061 } else if ((device_id & 0xfff) == 0x418) {
1062 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1063 buf += printed;
1064 buf_size -= printed;
1065
1066 switch (device_id >> 16) {
1067 case 0x1000:
1068 snprintf(buf, buf_size, "A");
1069 break;
1070
1071 case 0x1001:
1072 snprintf(buf, buf_size, "Z");
1073 break;
1074
1075 default:
1076 snprintf(buf, buf_size, "unknown");
1077 break;
1078 }
1079 } else if ((device_id & 0xfff) == 0x420) {
1080 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1081 buf += printed;
1082 buf_size -= printed;
1083
1084 switch (device_id >> 16) {
1085 case 0x1000:
1086 snprintf(buf, buf_size, "A");
1087 break;
1088
1089 case 0x1001:
1090 snprintf(buf, buf_size, "Z");
1091 break;
1092
1093 default:
1094 snprintf(buf, buf_size, "unknown");
1095 break;
1096 }
1097 } else if ((device_id & 0xfff) == 0x422) {
1098 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1099 buf += printed;
1100 buf_size -= printed;
1101
1102 switch (device_id >> 16) {
1103 case 0x1000:
1104 snprintf(buf, buf_size, "A");
1105 break;
1106
1107 case 0x1001:
1108 snprintf(buf, buf_size, "Z");
1109 break;
1110
1111 case 0x2000:
1112 snprintf(buf, buf_size, "B");
1113 break;
1114
1115 default:
1116 snprintf(buf, buf_size, "unknown");
1117 break;
1118 }
1119 } else if ((device_id & 0xfff) == 0x428) {
1120 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1121 buf += printed;
1122 buf_size -= printed;
1123
1124 switch (device_id >> 16) {
1125 case 0x1000:
1126 snprintf(buf, buf_size, "A");
1127 break;
1128
1129 case 0x1001:
1130 snprintf(buf, buf_size, "Z");
1131 break;
1132
1133 default:
1134 snprintf(buf, buf_size, "unknown");
1135 break;
1136 }
1137 } else if ((device_id & 0xfff) == 0x430) {
1138 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1139 buf += printed;
1140 buf_size -= printed;
1141
1142 switch (device_id >> 16) {
1143 case 0x1000:
1144 snprintf(buf, buf_size, "A");
1145 break;
1146
1147 default:
1148 snprintf(buf, buf_size, "unknown");
1149 break;
1150 }
1151 } else if ((device_id & 0xfff) == 0x432) {
1152 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1153 buf += printed;
1154 buf_size -= printed;
1155
1156 switch (device_id >> 16) {
1157 case 0x1000:
1158 snprintf(buf, buf_size, "A");
1159 break;
1160
1161 case 0x2000:
1162 snprintf(buf, buf_size, "B");
1163 break;
1164
1165 default:
1166 snprintf(buf, buf_size, "unknown");
1167 break;
1168 }
1169 } else if ((device_id & 0xfff) == 0x440) {
1170 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1171 buf += printed;
1172 buf_size -= printed;
1173
1174 switch (device_id >> 16) {
1175 case 0x1000:
1176 snprintf(buf, buf_size, "1.0");
1177 break;
1178
1179 case 0x2000:
1180 snprintf(buf, buf_size, "2.0");
1181 break;
1182
1183 default:
1184 snprintf(buf, buf_size, "unknown");
1185 break;
1186 }
1187 } else {
1188 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1189 return ERROR_FAIL;
1190 }
1191
1192 return ERROR_OK;
1193 }
1194
1195 COMMAND_HANDLER(stm32x_handle_lock_command)
1196 {
1197 struct target *target = NULL;
1198 struct stm32x_flash_bank *stm32x_info = NULL;
1199
1200 if (CMD_ARGC < 1)
1201 return ERROR_COMMAND_SYNTAX_ERROR;
1202
1203 struct flash_bank *bank;
1204 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1205 if (ERROR_OK != retval)
1206 return retval;
1207
1208 stm32x_info = bank->driver_priv;
1209
1210 target = bank->target;
1211
1212 if (target->state != TARGET_HALTED) {
1213 LOG_ERROR("Target not halted");
1214 return ERROR_TARGET_NOT_HALTED;
1215 }
1216
1217 retval = stm32x_check_operation_supported(bank);
1218 if (ERROR_OK != retval)
1219 return retval;
1220
1221 if (stm32x_erase_options(bank) != ERROR_OK) {
1222 command_print(CMD_CTX, "stm32x failed to erase options");
1223 return ERROR_OK;
1224 }
1225
1226 /* set readout protection */
1227 stm32x_info->option_bytes.RDP = 0;
1228
1229 if (stm32x_write_options(bank) != ERROR_OK) {
1230 command_print(CMD_CTX, "stm32x failed to lock device");
1231 return ERROR_OK;
1232 }
1233
1234 command_print(CMD_CTX, "stm32x locked");
1235
1236 return ERROR_OK;
1237 }
1238
1239 COMMAND_HANDLER(stm32x_handle_unlock_command)
1240 {
1241 struct target *target = NULL;
1242
1243 if (CMD_ARGC < 1)
1244 return ERROR_COMMAND_SYNTAX_ERROR;
1245
1246 struct flash_bank *bank;
1247 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1248 if (ERROR_OK != retval)
1249 return retval;
1250
1251 target = bank->target;
1252
1253 if (target->state != TARGET_HALTED) {
1254 LOG_ERROR("Target not halted");
1255 return ERROR_TARGET_NOT_HALTED;
1256 }
1257
1258 retval = stm32x_check_operation_supported(bank);
1259 if (ERROR_OK != retval)
1260 return retval;
1261
1262 if (stm32x_erase_options(bank) != ERROR_OK) {
1263 command_print(CMD_CTX, "stm32x failed to unlock device");
1264 return ERROR_OK;
1265 }
1266
1267 if (stm32x_write_options(bank) != ERROR_OK) {
1268 command_print(CMD_CTX, "stm32x failed to lock device");
1269 return ERROR_OK;
1270 }
1271
1272 command_print(CMD_CTX, "stm32x unlocked.\n"
1273 "INFO: a reset or power cycle is required "
1274 "for the new settings to take effect.");
1275
1276 return ERROR_OK;
1277 }
1278
1279 COMMAND_HANDLER(stm32x_handle_options_read_command)
1280 {
1281 uint32_t optionbyte;
1282 struct target *target = NULL;
1283 struct stm32x_flash_bank *stm32x_info = NULL;
1284
1285 if (CMD_ARGC < 1)
1286 return ERROR_COMMAND_SYNTAX_ERROR;
1287
1288 struct flash_bank *bank;
1289 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1290 if (ERROR_OK != retval)
1291 return retval;
1292
1293 stm32x_info = bank->driver_priv;
1294
1295 target = bank->target;
1296
1297 if (target->state != TARGET_HALTED) {
1298 LOG_ERROR("Target not halted");
1299 return ERROR_TARGET_NOT_HALTED;
1300 }
1301
1302 retval = stm32x_check_operation_supported(bank);
1303 if (ERROR_OK != retval)
1304 return retval;
1305
1306 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1307 if (retval != ERROR_OK)
1308 return retval;
1309 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1310
1311 if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1312 command_print(CMD_CTX, "Option Byte Complement Error");
1313
1314 if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1315 command_print(CMD_CTX, "Readout Protection On");
1316 else
1317 command_print(CMD_CTX, "Readout Protection Off");
1318
1319 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1320 command_print(CMD_CTX, "Software Watchdog");
1321 else
1322 command_print(CMD_CTX, "Hardware Watchdog");
1323
1324 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1325 command_print(CMD_CTX, "Stop: No reset generated");
1326 else
1327 command_print(CMD_CTX, "Stop: Reset generated");
1328
1329 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1330 command_print(CMD_CTX, "Standby: No reset generated");
1331 else
1332 command_print(CMD_CTX, "Standby: Reset generated");
1333
1334 if (stm32x_info->has_dual_banks) {
1335 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1336 command_print(CMD_CTX, "Boot: Bank 0");
1337 else
1338 command_print(CMD_CTX, "Boot: Bank 1");
1339 }
1340
1341 return ERROR_OK;
1342 }
1343
1344 COMMAND_HANDLER(stm32x_handle_options_write_command)
1345 {
1346 struct target *target = NULL;
1347 struct stm32x_flash_bank *stm32x_info = NULL;
1348 uint16_t optionbyte = 0xF8;
1349
1350 if (CMD_ARGC < 4)
1351 return ERROR_COMMAND_SYNTAX_ERROR;
1352
1353 struct flash_bank *bank;
1354 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1355 if (ERROR_OK != retval)
1356 return retval;
1357
1358 stm32x_info = bank->driver_priv;
1359
1360 target = bank->target;
1361
1362 if (target->state != TARGET_HALTED) {
1363 LOG_ERROR("Target not halted");
1364 return ERROR_TARGET_NOT_HALTED;
1365 }
1366
1367 retval = stm32x_check_operation_supported(bank);
1368 if (ERROR_OK != retval)
1369 return retval;
1370
1371 /* REVISIT: ignores some options which we will display...
1372 * and doesn't insist on the specified syntax.
1373 */
1374
1375 /* OPT_RDWDGSW */
1376 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1377 optionbyte |= (1 << 0);
1378 else /* REVISIT must be "HWWDG" then ... */
1379 optionbyte &= ~(1 << 0);
1380
1381 /* OPT_RDRSTSTOP */
1382 if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1383 optionbyte |= (1 << 1);
1384 else /* REVISIT must be "RSTSTNDBY" then ... */
1385 optionbyte &= ~(1 << 1);
1386
1387 /* OPT_RDRSTSTDBY */
1388 if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1389 optionbyte |= (1 << 2);
1390 else /* REVISIT must be "RSTSTOP" then ... */
1391 optionbyte &= ~(1 << 2);
1392
1393 if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
1394 /* OPT_BFB2 */
1395 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1396 optionbyte |= (1 << 3);
1397 else
1398 optionbyte &= ~(1 << 3);
1399 }
1400
1401 if (stm32x_erase_options(bank) != ERROR_OK) {
1402 command_print(CMD_CTX, "stm32x failed to erase options");
1403 return ERROR_OK;
1404 }
1405
1406 stm32x_info->option_bytes.user_options = optionbyte;
1407
1408 if (stm32x_write_options(bank) != ERROR_OK) {
1409 command_print(CMD_CTX, "stm32x failed to write options");
1410 return ERROR_OK;
1411 }
1412
1413 command_print(CMD_CTX, "stm32x write options complete.\n"
1414 "INFO: a reset or power cycle is required "
1415 "for the new settings to take effect.");
1416
1417 return ERROR_OK;
1418 }
1419
1420 static int stm32x_mass_erase(struct flash_bank *bank)
1421 {
1422 struct target *target = bank->target;
1423
1424 if (target->state != TARGET_HALTED) {
1425 LOG_ERROR("Target not halted");
1426 return ERROR_TARGET_NOT_HALTED;
1427 }
1428
1429 /* unlock option flash registers */
1430 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1431 if (retval != ERROR_OK)
1432 return retval;
1433 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1434 if (retval != ERROR_OK)
1435 return retval;
1436
1437 /* mass erase flash memory */
1438 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1439 if (retval != ERROR_OK)
1440 return retval;
1441 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1442 FLASH_MER | FLASH_STRT);
1443 if (retval != ERROR_OK)
1444 return retval;
1445
1446 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1447 if (retval != ERROR_OK)
1448 return retval;
1449
1450 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1451 if (retval != ERROR_OK)
1452 return retval;
1453
1454 return ERROR_OK;
1455 }
1456
1457 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1458 {
1459 int i;
1460
1461 if (CMD_ARGC < 1)
1462 return ERROR_COMMAND_SYNTAX_ERROR;
1463
1464 struct flash_bank *bank;
1465 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1466 if (ERROR_OK != retval)
1467 return retval;
1468
1469 retval = stm32x_mass_erase(bank);
1470 if (retval == ERROR_OK) {
1471 /* set all sectors as erased */
1472 for (i = 0; i < bank->num_sectors; i++)
1473 bank->sectors[i].is_erased = 1;
1474
1475 command_print(CMD_CTX, "stm32x mass erase complete");
1476 } else
1477 command_print(CMD_CTX, "stm32x mass erase failed");
1478
1479 return retval;
1480 }
1481
1482 static const struct command_registration stm32x_exec_command_handlers[] = {
1483 {
1484 .name = "lock",
1485 .handler = stm32x_handle_lock_command,
1486 .mode = COMMAND_EXEC,
1487 .usage = "bank_id",
1488 .help = "Lock entire flash device.",
1489 },
1490 {
1491 .name = "unlock",
1492 .handler = stm32x_handle_unlock_command,
1493 .mode = COMMAND_EXEC,
1494 .usage = "bank_id",
1495 .help = "Unlock entire protected flash device.",
1496 },
1497 {
1498 .name = "mass_erase",
1499 .handler = stm32x_handle_mass_erase_command,
1500 .mode = COMMAND_EXEC,
1501 .usage = "bank_id",
1502 .help = "Erase entire flash device.",
1503 },
1504 {
1505 .name = "options_read",
1506 .handler = stm32x_handle_options_read_command,
1507 .mode = COMMAND_EXEC,
1508 .usage = "bank_id",
1509 .help = "Read and display device option byte.",
1510 },
1511 {
1512 .name = "options_write",
1513 .handler = stm32x_handle_options_write_command,
1514 .mode = COMMAND_EXEC,
1515 .usage = "bank_id ('SWWDG'|'HWWDG') "
1516 "('RSTSTNDBY'|'NORSTSTNDBY') "
1517 "('RSTSTOP'|'NORSTSTOP')",
1518 .help = "Replace bits in device option byte.",
1519 },
1520 COMMAND_REGISTRATION_DONE
1521 };
1522
1523 static const struct command_registration stm32x_command_handlers[] = {
1524 {
1525 .name = "stm32f1x",
1526 .mode = COMMAND_ANY,
1527 .help = "stm32f1x flash command group",
1528 .usage = "",
1529 .chain = stm32x_exec_command_handlers,
1530 },
1531 COMMAND_REGISTRATION_DONE
1532 };
1533
1534 struct flash_driver stm32f1x_flash = {
1535 .name = "stm32f1x",
1536 .commands = stm32x_command_handlers,
1537 .flash_bank_command = stm32x_flash_bank_command,
1538 .erase = stm32x_erase,
1539 .protect = stm32x_protect,
1540 .write = stm32x_write,
1541 .read = default_flash_read,
1542 .probe = stm32x_probe,
1543 .auto_probe = stm32x_auto_probe,
1544 .erase_check = default_flash_blank_check,
1545 .protect_check = stm32x_protect_check,
1546 .info = get_stm32x_info,
1547 };
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