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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / openrisc / or1k.c
blob8c386108057e4292cde7a8e2bc5fef46a6049882
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2011 by Julius Baxter *
5 * julius@opencores.org *
6 * *
7 * Copyright (C) 2013 by Marek Czerski *
8 * ma.czerski@gmail.com *
9 * *
10 * Copyright (C) 2013 by Franck Jullien *
11 * elec4fun@gmail.com *
12 * *
13 ***************************************************************************/
14
15 #ifdef HAVE_CONFIG_H
16 #include "config.h"
17 #endif
18
19 #include <jtag/jtag.h>
20 #include <target/register.h>
21 #include <target/target.h>
22 #include <target/breakpoints.h>
23 #include <target/target_type.h>
24 #include <helper/time_support.h>
25 #include <helper/fileio.h>
26 #include "or1k_tap.h"
27 #include "or1k.h"
28 #include "or1k_du.h"
29
30 LIST_HEAD(tap_list);
31 LIST_HEAD(du_list);
32
33 static int or1k_remove_breakpoint(struct target *target,
34 struct breakpoint *breakpoint);
35
36 static int or1k_read_core_reg(struct target *target, int num);
37 static int or1k_write_core_reg(struct target *target, int num);
38
39 static struct or1k_core_reg *or1k_core_reg_list_arch_info;
40
41 static const struct or1k_core_reg_init or1k_init_reg_list[] = {
42 {"r0", GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
43 {"r1", GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
44 {"r2", GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
45 {"r3", GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
46 {"r4", GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
47 {"r5", GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
48 {"r6", GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
49 {"r7", GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
50 {"r8", GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
51 {"r9", GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
52 {"r10", GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
53 {"r11", GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
54 {"r12", GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
55 {"r13", GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
56 {"r14", GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
57 {"r15", GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
58 {"r16", GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
59 {"r17", GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
60 {"r18", GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
61 {"r19", GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
62 {"r20", GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
63 {"r21", GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
64 {"r22", GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
65 {"r23", GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
66 {"r24", GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
67 {"r25", GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
68 {"r26", GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
69 {"r27", GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
70 {"r28", GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
71 {"r29", GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
72 {"r30", GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
73 {"r31", GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
74 {"ppc", GROUP0 + 18, "org.gnu.gdb.or1k.group0", NULL},
75 {"npc", GROUP0 + 16, "org.gnu.gdb.or1k.group0", NULL},
76 {"sr", GROUP0 + 17, "org.gnu.gdb.or1k.group0", NULL},
77 {"vr", GROUP0 + 0, "org.gnu.gdb.or1k.group0", "system"},
78 {"upr", GROUP0 + 1, "org.gnu.gdb.or1k.group0", "system"},
79 {"cpucfgr", GROUP0 + 2, "org.gnu.gdb.or1k.group0", "system"},
80 {"dmmucfgr", GROUP0 + 3, "org.gnu.gdb.or1k.group0", "system"},
81 {"immucfgr", GROUP0 + 4, "org.gnu.gdb.or1k.group0", "system"},
82 {"dccfgr", GROUP0 + 5, "org.gnu.gdb.or1k.group0", "system"},
83 {"iccfgr", GROUP0 + 6, "org.gnu.gdb.or1k.group0", "system"},
84 {"dcfgr", GROUP0 + 7, "org.gnu.gdb.or1k.group0", "system"},
85 {"pccfgr", GROUP0 + 8, "org.gnu.gdb.or1k.group0", "system"},
86 {"fpcsr", GROUP0 + 20, "org.gnu.gdb.or1k.group0", "system"},
87 {"epcr0", GROUP0 + 32, "org.gnu.gdb.or1k.group0", "system"},
88 {"epcr1", GROUP0 + 33, "org.gnu.gdb.or1k.group0", "system"},
89 {"epcr2", GROUP0 + 34, "org.gnu.gdb.or1k.group0", "system"},
90 {"epcr3", GROUP0 + 35, "org.gnu.gdb.or1k.group0", "system"},
91 {"epcr4", GROUP0 + 36, "org.gnu.gdb.or1k.group0", "system"},
92 {"epcr5", GROUP0 + 37, "org.gnu.gdb.or1k.group0", "system"},
93 {"epcr6", GROUP0 + 38, "org.gnu.gdb.or1k.group0", "system"},
94 {"epcr7", GROUP0 + 39, "org.gnu.gdb.or1k.group0", "system"},
95 {"epcr8", GROUP0 + 40, "org.gnu.gdb.or1k.group0", "system"},
96 {"epcr9", GROUP0 + 41, "org.gnu.gdb.or1k.group0", "system"},
97 {"epcr10", GROUP0 + 42, "org.gnu.gdb.or1k.group0", "system"},
98 {"epcr11", GROUP0 + 43, "org.gnu.gdb.or1k.group0", "system"},
99 {"epcr12", GROUP0 + 44, "org.gnu.gdb.or1k.group0", "system"},
100 {"epcr13", GROUP0 + 45, "org.gnu.gdb.or1k.group0", "system"},
101 {"epcr14", GROUP0 + 46, "org.gnu.gdb.or1k.group0", "system"},
102 {"epcr15", GROUP0 + 47, "org.gnu.gdb.or1k.group0", "system"},
103 {"eear0", GROUP0 + 48, "org.gnu.gdb.or1k.group0", "system"},
104 {"eear1", GROUP0 + 49, "org.gnu.gdb.or1k.group0", "system"},
105 {"eear2", GROUP0 + 50, "org.gnu.gdb.or1k.group0", "system"},
106 {"eear3", GROUP0 + 51, "org.gnu.gdb.or1k.group0", "system"},
107 {"eear4", GROUP0 + 52, "org.gnu.gdb.or1k.group0", "system"},
108 {"eear5", GROUP0 + 53, "org.gnu.gdb.or1k.group0", "system"},
109 {"eear6", GROUP0 + 54, "org.gnu.gdb.or1k.group0", "system"},
110 {"eear7", GROUP0 + 55, "org.gnu.gdb.or1k.group0", "system"},
111 {"eear8", GROUP0 + 56, "org.gnu.gdb.or1k.group0", "system"},
112 {"eear9", GROUP0 + 57, "org.gnu.gdb.or1k.group0", "system"},
113 {"eear10", GROUP0 + 58, "org.gnu.gdb.or1k.group0", "system"},
114 {"eear11", GROUP0 + 59, "org.gnu.gdb.or1k.group0", "system"},
115 {"eear12", GROUP0 + 60, "org.gnu.gdb.or1k.group0", "system"},
116 {"eear13", GROUP0 + 61, "org.gnu.gdb.or1k.group0", "system"},
117 {"eear14", GROUP0 + 62, "org.gnu.gdb.or1k.group0", "system"},
118 {"eear15", GROUP0 + 63, "org.gnu.gdb.or1k.group0", "system"},
119 {"esr0", GROUP0 + 64, "org.gnu.gdb.or1k.group0", "system"},
120 {"esr1", GROUP0 + 65, "org.gnu.gdb.or1k.group0", "system"},
121 {"esr2", GROUP0 + 66, "org.gnu.gdb.or1k.group0", "system"},
122 {"esr3", GROUP0 + 67, "org.gnu.gdb.or1k.group0", "system"},
123 {"esr4", GROUP0 + 68, "org.gnu.gdb.or1k.group0", "system"},
124 {"esr5", GROUP0 + 69, "org.gnu.gdb.or1k.group0", "system"},
125 {"esr6", GROUP0 + 70, "org.gnu.gdb.or1k.group0", "system"},
126 {"esr7", GROUP0 + 71, "org.gnu.gdb.or1k.group0", "system"},
127 {"esr8", GROUP0 + 72, "org.gnu.gdb.or1k.group0", "system"},
128 {"esr9", GROUP0 + 73, "org.gnu.gdb.or1k.group0", "system"},
129 {"esr10", GROUP0 + 74, "org.gnu.gdb.or1k.group0", "system"},
130 {"esr11", GROUP0 + 75, "org.gnu.gdb.or1k.group0", "system"},
131 {"esr12", GROUP0 + 76, "org.gnu.gdb.or1k.group0", "system"},
132 {"esr13", GROUP0 + 77, "org.gnu.gdb.or1k.group0", "system"},
133 {"esr14", GROUP0 + 78, "org.gnu.gdb.or1k.group0", "system"},
134 {"esr15", GROUP0 + 79, "org.gnu.gdb.or1k.group0", "system"},
135
136 {"dmmuucr", GROUP1 + 0, "org.gnu.gdb.or1k.group1", "dmmu"},
137 {"dmmuupr", GROUP1 + 1, "org.gnu.gdb.or1k.group1", "dmmu"},
138 {"dtlbeir", GROUP1 + 2, "org.gnu.gdb.or1k.group1", "dmmu"},
139 {"datbmr0", GROUP1 + 4, "org.gnu.gdb.or1k.group1", "dmmu"},
140 {"datbmr1", GROUP1 + 5, "org.gnu.gdb.or1k.group1", "dmmu"},
141 {"datbmr2", GROUP1 + 6, "org.gnu.gdb.or1k.group1", "dmmu"},
142 {"datbmr3", GROUP1 + 7, "org.gnu.gdb.or1k.group1", "dmmu"},
143 {"datbtr0", GROUP1 + 8, "org.gnu.gdb.or1k.group1", "dmmu"},
144 {"datbtr1", GROUP1 + 9, "org.gnu.gdb.or1k.group1", "dmmu"},
145 {"datbtr2", GROUP1 + 10, "org.gnu.gdb.or1k.group1", "dmmu"},
146 {"datbtr3", GROUP1 + 11, "org.gnu.gdb.or1k.group1", "dmmu"},
147
148 {"immucr", GROUP2 + 0, "org.gnu.gdb.or1k.group2", "immu"},
149 {"immupr", GROUP2 + 1, "org.gnu.gdb.or1k.group2", "immu"},
150 {"itlbeir", GROUP2 + 2, "org.gnu.gdb.or1k.group2", "immu"},
151 {"iatbmr0", GROUP2 + 4, "org.gnu.gdb.or1k.group2", "immu"},
152 {"iatbmr1", GROUP2 + 5, "org.gnu.gdb.or1k.group2", "immu"},
153 {"iatbmr2", GROUP2 + 6, "org.gnu.gdb.or1k.group2", "immu"},
154 {"iatbmr3", GROUP2 + 7, "org.gnu.gdb.or1k.group2", "immu"},
155 {"iatbtr0", GROUP2 + 8, "org.gnu.gdb.or1k.group2", "immu"},
156 {"iatbtr1", GROUP2 + 9, "org.gnu.gdb.or1k.group2", "immu"},
157 {"iatbtr2", GROUP2 + 10, "org.gnu.gdb.or1k.group2", "immu"},
158 {"iatbtr3", GROUP2 + 11, "org.gnu.gdb.or1k.group2", "immu"},
159
160 {"dccr", GROUP3 + 0, "org.gnu.gdb.or1k.group3", "dcache"},
161 {"dcbpr", GROUP3 + 1, "org.gnu.gdb.or1k.group3", "dcache"},
162 {"dcbfr", GROUP3 + 2, "org.gnu.gdb.or1k.group3", "dcache"},
163 {"dcbir", GROUP3 + 3, "org.gnu.gdb.or1k.group3", "dcache"},
164 {"dcbwr", GROUP3 + 4, "org.gnu.gdb.or1k.group3", "dcache"},
165 {"dcblr", GROUP3 + 5, "org.gnu.gdb.or1k.group3", "dcache"},
166
167 {"iccr", GROUP4 + 0, "org.gnu.gdb.or1k.group4", "icache"},
168 {"icbpr", GROUP4 + 1, "org.gnu.gdb.or1k.group4", "icache"},
169 {"icbir", GROUP4 + 2, "org.gnu.gdb.or1k.group4", "icache"},
170 {"icblr", GROUP4 + 3, "org.gnu.gdb.or1k.group4", "icache"},
171
172 {"maclo", GROUP5 + 0, "org.gnu.gdb.or1k.group5", "mac"},
173 {"machi", GROUP5 + 1, "org.gnu.gdb.or1k.group5", "mac"},
174
175 {"dvr0", GROUP6 + 0, "org.gnu.gdb.or1k.group6", "debug"},
176 {"dvr1", GROUP6 + 1, "org.gnu.gdb.or1k.group6", "debug"},
177 {"dvr2", GROUP6 + 2, "org.gnu.gdb.or1k.group6", "debug"},
178 {"dvr3", GROUP6 + 3, "org.gnu.gdb.or1k.group6", "debug"},
179 {"dvr4", GROUP6 + 4, "org.gnu.gdb.or1k.group6", "debug"},
180 {"dvr5", GROUP6 + 5, "org.gnu.gdb.or1k.group6", "debug"},
181 {"dvr6", GROUP6 + 6, "org.gnu.gdb.or1k.group6", "debug"},
182 {"dvr7", GROUP6 + 7, "org.gnu.gdb.or1k.group6", "debug"},
183 {"dcr0", GROUP6 + 8, "org.gnu.gdb.or1k.group6", "debug"},
184 {"dcr1", GROUP6 + 9, "org.gnu.gdb.or1k.group6", "debug"},
185 {"dcr2", GROUP6 + 10, "org.gnu.gdb.or1k.group6", "debug"},
186 {"dcr3", GROUP6 + 11, "org.gnu.gdb.or1k.group6", "debug"},
187 {"dcr4", GROUP6 + 12, "org.gnu.gdb.or1k.group6", "debug"},
188 {"dcr5", GROUP6 + 13, "org.gnu.gdb.or1k.group6", "debug"},
189 {"dcr6", GROUP6 + 14, "org.gnu.gdb.or1k.group6", "debug"},
190 {"dcr7", GROUP6 + 15, "org.gnu.gdb.or1k.group6", "debug"},
191 {"dmr1", GROUP6 + 16, "org.gnu.gdb.or1k.group6", "debug"},
192 {"dmr2", GROUP6 + 17, "org.gnu.gdb.or1k.group6", "debug"},
193 {"dcwr0", GROUP6 + 18, "org.gnu.gdb.or1k.group6", "debug"},
194 {"dcwr1", GROUP6 + 19, "org.gnu.gdb.or1k.group6", "debug"},
195 {"dsr", GROUP6 + 20, "org.gnu.gdb.or1k.group6", "debug"},
196 {"drr", GROUP6 + 21, "org.gnu.gdb.or1k.group6", "debug"},
197
198 {"pccr0", GROUP7 + 0, "org.gnu.gdb.or1k.group7", "perf"},
199 {"pccr1", GROUP7 + 1, "org.gnu.gdb.or1k.group7", "perf"},
200 {"pccr2", GROUP7 + 2, "org.gnu.gdb.or1k.group7", "perf"},
201 {"pccr3", GROUP7 + 3, "org.gnu.gdb.or1k.group7", "perf"},
202 {"pccr4", GROUP7 + 4, "org.gnu.gdb.or1k.group7", "perf"},
203 {"pccr5", GROUP7 + 5, "org.gnu.gdb.or1k.group7", "perf"},
204 {"pccr6", GROUP7 + 6, "org.gnu.gdb.or1k.group7", "perf"},
205 {"pccr7", GROUP7 + 7, "org.gnu.gdb.or1k.group7", "perf"},
206 {"pcmr0", GROUP7 + 8, "org.gnu.gdb.or1k.group7", "perf"},
207 {"pcmr1", GROUP7 + 9, "org.gnu.gdb.or1k.group7", "perf"},
208 {"pcmr2", GROUP7 + 10, "org.gnu.gdb.or1k.group7", "perf"},
209 {"pcmr3", GROUP7 + 11, "org.gnu.gdb.or1k.group7", "perf"},
210 {"pcmr4", GROUP7 + 12, "org.gnu.gdb.or1k.group7", "perf"},
211 {"pcmr5", GROUP7 + 13, "org.gnu.gdb.or1k.group7", "perf"},
212 {"pcmr6", GROUP7 + 14, "org.gnu.gdb.or1k.group7", "perf"},
213 {"pcmr7", GROUP7 + 15, "org.gnu.gdb.or1k.group7", "perf"},
214
215 {"pmr", GROUP8 + 0, "org.gnu.gdb.or1k.group8", "power"},
216
217 {"picmr", GROUP9 + 0, "org.gnu.gdb.or1k.group9", "pic"},
218 {"picsr", GROUP9 + 2, "org.gnu.gdb.or1k.group9", "pic"},
219
220 {"ttmr", GROUP10 + 0, "org.gnu.gdb.or1k.group10", "timer"},
221 {"ttcr", GROUP10 + 1, "org.gnu.gdb.or1k.group10", "timer"},
222 };
223
224 static int or1k_add_reg(struct target *target, struct or1k_core_reg *new_reg)
225 {
226 struct or1k_common *or1k = target_to_or1k(target);
227 int reg_list_size = or1k->nb_regs * sizeof(struct or1k_core_reg);
228
229 or1k_core_reg_list_arch_info = realloc(or1k_core_reg_list_arch_info,
230 reg_list_size + sizeof(struct or1k_core_reg));
231
232 memcpy(&or1k_core_reg_list_arch_info[or1k->nb_regs], new_reg,
233 sizeof(struct or1k_core_reg));
234
235 or1k_core_reg_list_arch_info[or1k->nb_regs].list_num = or1k->nb_regs;
236
237 or1k->nb_regs++;
238
239 return ERROR_OK;
240 }
241
242 static int or1k_create_reg_list(struct target *target)
243 {
244 struct or1k_common *or1k = target_to_or1k(target);
245
246 LOG_DEBUG("-");
247
248 or1k_core_reg_list_arch_info = malloc(ARRAY_SIZE(or1k_init_reg_list) *
249 sizeof(struct or1k_core_reg));
250
251 for (int i = 0; i < (int)ARRAY_SIZE(or1k_init_reg_list); i++) {
252 or1k_core_reg_list_arch_info[i].name = or1k_init_reg_list[i].name;
253 or1k_core_reg_list_arch_info[i].spr_num = or1k_init_reg_list[i].spr_num;
254 or1k_core_reg_list_arch_info[i].group = or1k_init_reg_list[i].group;
255 or1k_core_reg_list_arch_info[i].feature = or1k_init_reg_list[i].feature;
256 or1k_core_reg_list_arch_info[i].list_num = i;
257 or1k_core_reg_list_arch_info[i].target = NULL;
258 or1k_core_reg_list_arch_info[i].or1k_common = NULL;
259 }
260
261 or1k->nb_regs = ARRAY_SIZE(or1k_init_reg_list);
262
263 struct or1k_core_reg new_reg;
264 new_reg.target = NULL;
265 new_reg.or1k_common = NULL;
266
267 char name[32];
268 for (int way = 0; way < 4; way++) {
269 for (int i = 0; i < 128; i++) {
270
271 sprintf(name, "dtlbw%dmr%d", way, i);
272 new_reg.name = strdup(name);
273 new_reg.spr_num = GROUP1 + 512 + i + (way * 256);
274 new_reg.feature = "org.gnu.gdb.or1k.group1";
275 new_reg.group = "dmmu";
276 or1k_add_reg(target, &new_reg);
277
278 sprintf(name, "dtlbw%dtr%d", way, i);
279 new_reg.name = strdup(name);
280 new_reg.spr_num = GROUP1 + 640 + i + (way * 256);
281 new_reg.feature = "org.gnu.gdb.or1k.group1";
282 new_reg.group = "dmmu";
283 or1k_add_reg(target, &new_reg);
284
285
286 sprintf(name, "itlbw%dmr%d", way, i);
287 new_reg.name = strdup(name);
288 new_reg.spr_num = GROUP2 + 512 + i + (way * 256);
289 new_reg.feature = "org.gnu.gdb.or1k.group2";
290 new_reg.group = "immu";
291 or1k_add_reg(target, &new_reg);
292
293
294 sprintf(name, "itlbw%dtr%d", way, i);
295 new_reg.name = strdup(name);
296 new_reg.spr_num = GROUP2 + 640 + i + (way * 256);
297 new_reg.feature = "org.gnu.gdb.or1k.group2";
298 new_reg.group = "immu";
299 or1k_add_reg(target, &new_reg);
300
301 }
302 }
303
304 return ERROR_OK;
305 }
306
307 static int or1k_jtag_read_regs(struct or1k_common *or1k, uint32_t *regs)
308 {
309 struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
310
311 LOG_DEBUG("-");
312
313 return du_core->or1k_jtag_read_cpu(&or1k->jtag,
314 or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
315 regs + OR1K_REG_R0);
316 }
317
318 static int or1k_jtag_write_regs(struct or1k_common *or1k, uint32_t *regs)
319 {
320 struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
321
322 LOG_DEBUG("-");
323
324 return du_core->or1k_jtag_write_cpu(&or1k->jtag,
325 or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
326 &regs[OR1K_REG_R0]);
327 }
328
329 static int or1k_save_context(struct target *target)
330 {
331 struct or1k_common *or1k = target_to_or1k(target);
332 struct or1k_du *du_core = or1k_to_du(or1k);
333 int regs_read = 0;
334 int retval;
335
336 LOG_DEBUG("-");
337
338 for (int i = 0; i < OR1KNUMCOREREGS; i++) {
339 if (!or1k->core_cache->reg_list[i].valid) {
340 if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
341 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
342 or1k->arch_info[i].spr_num, 1,
343 &or1k->core_regs[i]);
344 if (retval != ERROR_OK)
345 return retval;
346 } else if (!regs_read) {
347 /* read gpr registers at once (but only one time in this loop) */
348 retval = or1k_jtag_read_regs(or1k, or1k->core_regs);
349 if (retval != ERROR_OK)
350 return retval;
351 /* prevent next reads in this loop */
352 regs_read = 1;
353 }
354 /* We've just updated the core_reg[i], now update
355 the core cache */
356 or1k_read_core_reg(target, i);
357 }
358 }
359
360 return ERROR_OK;
361 }
362
363 static int or1k_restore_context(struct target *target)
364 {
365 struct or1k_common *or1k = target_to_or1k(target);
366 struct or1k_du *du_core = or1k_to_du(or1k);
367 int reg_write = 0;
368 int retval;
369
370 LOG_DEBUG("-");
371
372 for (int i = 0; i < OR1KNUMCOREREGS; i++) {
373 if (or1k->core_cache->reg_list[i].dirty) {
374 or1k_write_core_reg(target, i);
375
376 if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
377 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
378 or1k->arch_info[i].spr_num, 1,
379 &or1k->core_regs[i]);
380 if (retval != ERROR_OK) {
381 LOG_ERROR("Error while restoring context");
382 return retval;
383 }
384 } else
385 reg_write = 1;
386 }
387 }
388
389 if (reg_write) {
390 /* read gpr registers at once (but only one time in this loop) */
391 retval = or1k_jtag_write_regs(or1k, or1k->core_regs);
392 if (retval != ERROR_OK) {
393 LOG_ERROR("Error while restoring context");
394 return retval;
395 }
396 }
397
398 return ERROR_OK;
399 }
400
401 static int or1k_read_core_reg(struct target *target, int num)
402 {
403 struct or1k_common *or1k = target_to_or1k(target);
404 struct or1k_du *du_core = or1k_to_du(or1k);
405 uint32_t reg_value;
406
407 LOG_DEBUG("-");
408
409 if ((num < 0) || (num >= or1k->nb_regs))
410 return ERROR_COMMAND_SYNTAX_ERROR;
411
412 if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
413 reg_value = or1k->core_regs[num];
414 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
415 LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num, reg_value);
416 or1k->core_cache->reg_list[num].valid = true;
417 or1k->core_cache->reg_list[num].dirty = false;
418 } else {
419 /* This is an spr, always read value from HW */
420 int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
421 or1k->arch_info[num].spr_num, 1, &reg_value);
422 if (retval != ERROR_OK) {
423 LOG_ERROR("Error while reading spr 0x%08" PRIx32, or1k->arch_info[num].spr_num);
424 return retval;
425 }
426 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
427 LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num, reg_value);
428 }
429
430 return ERROR_OK;
431 }
432
433 static int or1k_write_core_reg(struct target *target, int num)
434 {
435 struct or1k_common *or1k = target_to_or1k(target);
436
437 LOG_DEBUG("-");
438
439 if ((num < 0) || (num >= OR1KNUMCOREREGS))
440 return ERROR_COMMAND_SYNTAX_ERROR;
441
442 uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
443 or1k->core_regs[num] = reg_value;
444 LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num, reg_value);
445 or1k->core_cache->reg_list[num].valid = true;
446 or1k->core_cache->reg_list[num].dirty = false;
447
448 return ERROR_OK;
449 }
450
451 static int or1k_get_core_reg(struct reg *reg)
452 {
453 struct or1k_core_reg *or1k_reg = reg->arch_info;
454 struct target *target = or1k_reg->target;
455
456 LOG_DEBUG("-");
457
458 if (target->state != TARGET_HALTED)
459 return ERROR_TARGET_NOT_HALTED;
460
461 return or1k_read_core_reg(target, or1k_reg->list_num);
462 }
463
464 static int or1k_set_core_reg(struct reg *reg, uint8_t *buf)
465 {
466 struct or1k_core_reg *or1k_reg = reg->arch_info;
467 struct target *target = or1k_reg->target;
468 struct or1k_common *or1k = target_to_or1k(target);
469 struct or1k_du *du_core = or1k_to_du(or1k);
470 uint32_t value = buf_get_u32(buf, 0, 32);
471
472 LOG_DEBUG("-");
473
474 if (target->state != TARGET_HALTED)
475 return ERROR_TARGET_NOT_HALTED;
476
477 if (or1k_reg->list_num < OR1KNUMCOREREGS) {
478 buf_set_u32(reg->value, 0, 32, value);
479 reg->dirty = true;
480 reg->valid = true;
481 } else {
482 /* This is an spr, write it to the HW */
483 int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
484 or1k_reg->spr_num, 1, &value);
485 if (retval != ERROR_OK) {
486 LOG_ERROR("Error while writing spr 0x%08" PRIx32, or1k_reg->spr_num);
487 return retval;
488 }
489 }
490
491 return ERROR_OK;
492 }
493
494 static const struct reg_arch_type or1k_reg_type = {
495 .get = or1k_get_core_reg,
496 .set = or1k_set_core_reg,
497 };
498
499 static struct reg_cache *or1k_build_reg_cache(struct target *target)
500 {
501 struct or1k_common *or1k = target_to_or1k(target);
502 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
503 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
504 struct reg *reg_list = calloc(or1k->nb_regs, sizeof(struct reg));
505 struct or1k_core_reg *arch_info =
506 malloc((or1k->nb_regs) * sizeof(struct or1k_core_reg));
507 struct reg_feature *feature;
508
509 LOG_DEBUG("-");
510
511 /* Build the process context cache */
512 cache->name = "OpenRISC 1000 registers";
513 cache->next = NULL;
514 cache->reg_list = reg_list;
515 cache->num_regs = or1k->nb_regs;
516 (*cache_p) = cache;
517 or1k->core_cache = cache;
518 or1k->arch_info = arch_info;
519
520 for (int i = 0; i < or1k->nb_regs; i++) {
521 arch_info[i] = or1k_core_reg_list_arch_info[i];
522 arch_info[i].target = target;
523 arch_info[i].or1k_common = or1k;
524 reg_list[i].name = or1k_core_reg_list_arch_info[i].name;
525
526 feature = malloc(sizeof(struct reg_feature));
527 feature->name = or1k_core_reg_list_arch_info[i].feature;
528 reg_list[i].feature = feature;
529
530 reg_list[i].group = or1k_core_reg_list_arch_info[i].group;
531 reg_list[i].size = 32;
532 reg_list[i].value = calloc(1, 4);
533 reg_list[i].dirty = false;
534 reg_list[i].valid = false;
535 reg_list[i].type = &or1k_reg_type;
536 reg_list[i].arch_info = &arch_info[i];
537 reg_list[i].number = i;
538 reg_list[i].exist = true;
539 }
540
541 return cache;
542 }
543
544 static int or1k_debug_entry(struct target *target)
545 {
546 LOG_DEBUG("-");
547
548 int retval = or1k_save_context(target);
549 if (retval != ERROR_OK) {
550 LOG_ERROR("Error while calling or1k_save_context");
551 return retval;
552 }
553
554 struct or1k_common *or1k = target_to_or1k(target);
555 uint32_t addr = or1k->core_regs[OR1K_REG_NPC];
556
557 if (breakpoint_find(target, addr))
558 /* Halted on a breakpoint, step back to permit executing the instruction there */
559 retval = or1k_set_core_reg(&or1k->core_cache->reg_list[OR1K_REG_NPC],
560 (uint8_t *)&addr);
561
562 return retval;
563 }
564
565 static int or1k_halt(struct target *target)
566 {
567 struct or1k_common *or1k = target_to_or1k(target);
568 struct or1k_du *du_core = or1k_to_du(or1k);
569
570 LOG_DEBUG("target->state: %s",
571 target_state_name(target));
572
573 if (target->state == TARGET_HALTED) {
574 LOG_DEBUG("Target was already halted");
575 return ERROR_OK;
576 }
577
578 if (target->state == TARGET_UNKNOWN)
579 LOG_WARNING("Target was in unknown state when halt was requested");
580
581 if (target->state == TARGET_RESET) {
582 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) &&
583 jtag_get_srst()) {
584 LOG_ERROR("Can't request a halt while in reset if nSRST pulls nTRST");
585 return ERROR_TARGET_FAILURE;
586 } else {
587 target->debug_reason = DBG_REASON_DBGRQ;
588 return ERROR_OK;
589 }
590 }
591
592 int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
593 if (retval != ERROR_OK) {
594 LOG_ERROR("Impossible to stall the CPU");
595 return retval;
596 }
597
598 target->debug_reason = DBG_REASON_DBGRQ;
599
600 return ERROR_OK;
601 }
602
603 static int or1k_is_cpu_running(struct target *target, int *running)
604 {
605 struct or1k_common *or1k = target_to_or1k(target);
606 struct or1k_du *du_core = or1k_to_du(or1k);
607 int retval;
608 int tries = 0;
609 const int RETRIES_MAX = 5;
610
611 /* Have a retry loop to determine of the CPU is running.
612 If target has been hard reset for any reason, it might take a couple
613 of goes before it's ready again.
614 */
615 while (tries < RETRIES_MAX) {
616
617 tries++;
618
619 retval = du_core->or1k_is_cpu_running(&or1k->jtag, running);
620 if (retval != ERROR_OK) {
621 LOG_WARNING("Debug IF CPU control reg read failure.");
622 /* Try once to restart the JTAG infrastructure -
623 quite possibly the board has just been reset. */
624 LOG_WARNING("Resetting JTAG TAP state and reconnecting to debug IF.");
625 du_core->or1k_jtag_init(&or1k->jtag);
626
627 LOG_WARNING("...attempt %d of %d", tries, RETRIES_MAX);
628
629 alive_sleep(2);
630
631 continue;
632 } else
633 return ERROR_OK;
634 }
635
636 LOG_ERROR("Could not re-establish communication with target");
637 return retval;
638 }
639
640 static int or1k_poll(struct target *target)
641 {
642 int retval;
643 int running;
644
645 retval = or1k_is_cpu_running(target, &running);
646 if (retval != ERROR_OK) {
647 LOG_ERROR("Error while calling or1k_is_cpu_running");
648 return retval;
649 }
650
651 /* check for processor halted */
652 if (!running) {
653 /* It's actually stalled, so update our software's state */
654 if ((target->state == TARGET_RUNNING) ||
655 (target->state == TARGET_RESET)) {
656
657 target->state = TARGET_HALTED;
658
659 retval = or1k_debug_entry(target);
660 if (retval != ERROR_OK) {
661 LOG_ERROR("Error while calling or1k_debug_entry");
662 return retval;
663 }
664
665 target_call_event_callbacks(target,
666 TARGET_EVENT_HALTED);
667 } else if (target->state == TARGET_DEBUG_RUNNING) {
668 target->state = TARGET_HALTED;
669
670 retval = or1k_debug_entry(target);
671 if (retval != ERROR_OK) {
672 LOG_ERROR("Error while calling or1k_debug_entry");
673 return retval;
674 }
675
676 target_call_event_callbacks(target,
677 TARGET_EVENT_DEBUG_HALTED);
678 }
679 } else { /* ... target is running */
680
681 /* If target was supposed to be stalled, stall it again */
682 if (target->state == TARGET_HALTED) {
683
684 target->state = TARGET_RUNNING;
685
686 retval = or1k_halt(target);
687 if (retval != ERROR_OK) {
688 LOG_ERROR("Error while calling or1k_halt");
689 return retval;
690 }
691
692 retval = or1k_debug_entry(target);
693 if (retval != ERROR_OK) {
694 LOG_ERROR("Error while calling or1k_debug_entry");
695 return retval;
696 }
697
698 target_call_event_callbacks(target,
699 TARGET_EVENT_DEBUG_HALTED);
700 }
701
702 target->state = TARGET_RUNNING;
703
704 }
705
706 return ERROR_OK;
707 }
708
709 static int or1k_assert_reset(struct target *target)
710 {
711 struct or1k_common *or1k = target_to_or1k(target);
712 struct or1k_du *du_core = or1k_to_du(or1k);
713
714 LOG_DEBUG("-");
715
716 int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_RESET);
717 if (retval != ERROR_OK) {
718 LOG_ERROR("Error while asserting RESET");
719 return retval;
720 }
721
722 return ERROR_OK;
723 }
724
725 static int or1k_deassert_reset(struct target *target)
726 {
727 struct or1k_common *or1k = target_to_or1k(target);
728 struct or1k_du *du_core = or1k_to_du(or1k);
729
730 LOG_DEBUG("-");
731
732 int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_NOT_RESET);
733 if (retval != ERROR_OK) {
734 LOG_ERROR("Error while deasserting RESET");
735 return retval;
736 }
737
738 return ERROR_OK;
739 }
740
741 static int or1k_soft_reset_halt(struct target *target)
742 {
743 struct or1k_common *or1k = target_to_or1k(target);
744 struct or1k_du *du_core = or1k_to_du(or1k);
745
746 LOG_DEBUG("-");
747
748 int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
749 if (retval != ERROR_OK) {
750 LOG_ERROR("Error while stalling the CPU");
751 return retval;
752 }
753
754 retval = or1k_assert_reset(target);
755 if (retval != ERROR_OK)
756 return retval;
757
758 retval = or1k_deassert_reset(target);
759 if (retval != ERROR_OK)
760 return retval;
761
762 return ERROR_OK;
763 }
764
765 static bool is_any_soft_breakpoint(struct target *target)
766 {
767 struct breakpoint *breakpoint = target->breakpoints;
768
769 LOG_DEBUG("-");
770
771 while (breakpoint)
772 if (breakpoint->type == BKPT_SOFT)
773 return true;
774
775 return false;
776 }
777
778 static int or1k_resume_or_step(struct target *target, int current,
779 uint32_t address, int handle_breakpoints,
780 int debug_execution, int step)
781 {
782 struct or1k_common *or1k = target_to_or1k(target);
783 struct or1k_du *du_core = or1k_to_du(or1k);
784 struct breakpoint *breakpoint = NULL;
785 uint32_t resume_pc;
786 uint32_t debug_reg_list[OR1K_DEBUG_REG_NUM];
787
788 LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
789 address, step ? "yes" : "no", handle_breakpoints ? "yes" : "no");
790
791 if (target->state != TARGET_HALTED) {
792 LOG_TARGET_ERROR(target, "not halted");
793 return ERROR_TARGET_NOT_HALTED;
794 }
795
796 if (!debug_execution)
797 target_free_all_working_areas(target);
798
799 /* current ? continue on current pc : continue at <address> */
800 if (!current)
801 buf_set_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value, 0,
802 32, address);
803
804 int retval = or1k_restore_context(target);
805 if (retval != ERROR_OK) {
806 LOG_ERROR("Error while calling or1k_restore_context");
807 return retval;
808 }
809
810 /* read debug registers (starting from DMR1 register) */
811 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
812 OR1K_DEBUG_REG_NUM, debug_reg_list);
813 if (retval != ERROR_OK) {
814 LOG_ERROR("Error while reading debug registers");
815 return retval;
816 }
817
818 /* Clear Debug Reason Register (DRR) */
819 debug_reg_list[OR1K_DEBUG_REG_DRR] = 0;
820
821 /* Clear watchpoint break generation in Debug Mode Register 2 (DMR2) */
822 debug_reg_list[OR1K_DEBUG_REG_DMR2] &= ~OR1K_DMR2_WGB;
823 if (step)
824 /* Set the single step trigger in Debug Mode Register 1 (DMR1) */
825 debug_reg_list[OR1K_DEBUG_REG_DMR1] |= OR1K_DMR1_ST | OR1K_DMR1_BT;
826 else
827 /* Clear the single step trigger in Debug Mode Register 1 (DMR1) */
828 debug_reg_list[OR1K_DEBUG_REG_DMR1] &= ~(OR1K_DMR1_ST | OR1K_DMR1_BT);
829
830 /* Set traps to be handled by the debug unit in the Debug Stop
831 Register (DSR). Check if we have any software breakpoints in
832 place before setting this value - the kernel, for instance,
833 relies on l.trap instructions not stalling the processor ! */
834 if (is_any_soft_breakpoint(target) == true)
835 debug_reg_list[OR1K_DEBUG_REG_DSR] |= OR1K_DSR_TE;
836
837 /* Write debug registers (starting from DMR1 register) */
838 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
839 OR1K_DEBUG_REG_NUM, debug_reg_list);
840 if (retval != ERROR_OK) {
841 LOG_ERROR("Error while writing back debug registers");
842 return retval;
843 }
844
845 resume_pc = buf_get_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value,
846 0, 32);
847
848 /* The front-end may request us not to handle breakpoints */
849 if (handle_breakpoints) {
850 /* Single step past breakpoint at current address */
851 breakpoint = breakpoint_find(target, resume_pc);
852 if (breakpoint) {
853 LOG_DEBUG("Unset breakpoint at 0x%08" TARGET_PRIxADDR, breakpoint->address);
854 retval = or1k_remove_breakpoint(target, breakpoint);
855 if (retval != ERROR_OK)
856 return retval;
857 }
858 }
859
860 /* Unstall time */
861 retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_UNSTALL);
862 if (retval != ERROR_OK) {
863 LOG_ERROR("Error while unstalling the CPU");
864 return retval;
865 }
866
867 if (step)
868 target->debug_reason = DBG_REASON_SINGLESTEP;
869 else
870 target->debug_reason = DBG_REASON_NOTHALTED;
871
872 /* Registers are now invalid */
873 register_cache_invalidate(or1k->core_cache);
874
875 if (!debug_execution) {
876 target->state = TARGET_RUNNING;
877 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
878 LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
879 } else {
880 target->state = TARGET_DEBUG_RUNNING;
881 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
882 LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
883 }
884
885 return ERROR_OK;
886 }
887
888 static int or1k_resume(struct target *target, int current,
889 target_addr_t address, int handle_breakpoints,
890 int debug_execution)
891 {
892 return or1k_resume_or_step(target, current, address,
893 handle_breakpoints,
894 debug_execution,
895 NO_SINGLE_STEP);
896 }
897
898 static int or1k_step(struct target *target, int current,
899 target_addr_t address, int handle_breakpoints)
900 {
901 return or1k_resume_or_step(target, current, address,
902 handle_breakpoints,
903 0,
904 SINGLE_STEP);
905
906 }
907
908 static int or1k_add_breakpoint(struct target *target,
909 struct breakpoint *breakpoint)
910 {
911 struct or1k_common *or1k = target_to_or1k(target);
912 struct or1k_du *du_core = or1k_to_du(or1k);
913 uint8_t data;
914
915 LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, id: %" PRIu32,
916 breakpoint->address, breakpoint->length, breakpoint->type,
917 breakpoint->unique_id);
918
919 /* Only support SW breakpoints for now. */
920 if (breakpoint->type == BKPT_HARD)
921 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
922
923 /* Read and save the instruction */
924 int retval = du_core->or1k_jtag_read_memory(&or1k->jtag,
925 breakpoint->address,
926 4,
927 1,
928 &data);
929 if (retval != ERROR_OK) {
930 LOG_ERROR("Error while reading the instruction at 0x%08" TARGET_PRIxADDR,
931 breakpoint->address);
932 return retval;
933 }
934
935 free(breakpoint->orig_instr);
936
937 breakpoint->orig_instr = malloc(breakpoint->length);
938 memcpy(breakpoint->orig_instr, &data, breakpoint->length);
939
940 /* Sub in the OR1K trap instruction */
941 uint8_t or1k_trap_insn[4];
942 target_buffer_set_u32(target, or1k_trap_insn, OR1K_TRAP_INSTR);
943 retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
944 breakpoint->address,
945 4,
946 1,
947 or1k_trap_insn);
948
949 if (retval != ERROR_OK) {
950 LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08" TARGET_PRIxADDR,
951 breakpoint->address);
952 return retval;
953 }
954
955 /* invalidate instruction cache */
956 uint32_t addr = breakpoint->address;
957 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
958 OR1K_ICBIR_CPU_REG_ADD, 1, &addr);
959 if (retval != ERROR_OK) {
960 LOG_ERROR("Error while invalidating the ICACHE");
961 return retval;
962 }
963
964 return ERROR_OK;
965 }
966
967 static int or1k_remove_breakpoint(struct target *target,
968 struct breakpoint *breakpoint)
969 {
970 struct or1k_common *or1k = target_to_or1k(target);
971 struct or1k_du *du_core = or1k_to_du(or1k);
972
973 LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, id: %" PRIu32,
974 breakpoint->address, breakpoint->length, breakpoint->type,
975 breakpoint->unique_id);
976
977 /* Only support SW breakpoints for now. */
978 if (breakpoint->type == BKPT_HARD)
979 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
980
981 /* Replace the removed instruction */
982 int retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
983 breakpoint->address,
984 4,
985 1,
986 breakpoint->orig_instr);
987
988 if (retval != ERROR_OK) {
989 LOG_ERROR("Error while writing back the instruction at 0x%08" TARGET_PRIxADDR,
990 breakpoint->address);
991 return retval;
992 }
993
994 /* invalidate instruction cache */
995 uint32_t addr = breakpoint->address;
996 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
997 OR1K_ICBIR_CPU_REG_ADD, 1, &addr);
998 if (retval != ERROR_OK) {
999 LOG_ERROR("Error while invalidating the ICACHE");
1000 return retval;
1001 }
1002
1003 return ERROR_OK;
1004 }
1005
1006 static int or1k_add_watchpoint(struct target *target,
1007 struct watchpoint *watchpoint)
1008 {
1009 LOG_ERROR("%s: implement me", __func__);
1010 return ERROR_OK;
1011 }
1012
1013 static int or1k_remove_watchpoint(struct target *target,
1014 struct watchpoint *watchpoint)
1015 {
1016 LOG_ERROR("%s: implement me", __func__);
1017 return ERROR_OK;
1018 }
1019
1020 static int or1k_read_memory(struct target *target, target_addr_t address,
1021 uint32_t size, uint32_t count, uint8_t *buffer)
1022 {
1023 struct or1k_common *or1k = target_to_or1k(target);
1024 struct or1k_du *du_core = or1k_to_du(or1k);
1025
1026 LOG_DEBUG("Read memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1027
1028 if (target->state != TARGET_HALTED) {
1029 LOG_TARGET_ERROR(target, "not halted");
1030 return ERROR_TARGET_NOT_HALTED;
1031 }
1032
1033 /* Sanitize arguments */
1034 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1035 LOG_ERROR("Bad arguments");
1036 return ERROR_COMMAND_SYNTAX_ERROR;
1037 }
1038
1039 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1040 LOG_ERROR("Can't handle unaligned memory access");
1041 return ERROR_TARGET_UNALIGNED_ACCESS;
1042 }
1043
1044 return du_core->or1k_jtag_read_memory(&or1k->jtag, address, size, count, buffer);
1045 }
1046
1047 static int or1k_write_memory(struct target *target, target_addr_t address,
1048 uint32_t size, uint32_t count, const uint8_t *buffer)
1049 {
1050 struct or1k_common *or1k = target_to_or1k(target);
1051 struct or1k_du *du_core = or1k_to_du(or1k);
1052
1053 LOG_DEBUG("Write memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1054
1055 if (target->state != TARGET_HALTED) {
1056 LOG_TARGET_ERROR(target, "not halted");
1057 return ERROR_TARGET_NOT_HALTED;
1058 }
1059
1060 /* Sanitize arguments */
1061 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1062 LOG_ERROR("Bad arguments");
1063 return ERROR_COMMAND_SYNTAX_ERROR;
1064 }
1065
1066 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1067 LOG_ERROR("Can't handle unaligned memory access");
1068 return ERROR_TARGET_UNALIGNED_ACCESS;
1069 }
1070
1071 return du_core->or1k_jtag_write_memory(&or1k->jtag, address, size, count, buffer);
1072 }
1073
1074 static int or1k_init_target(struct command_context *cmd_ctx,
1075 struct target *target)
1076 {
1077 struct or1k_common *or1k = target_to_or1k(target);
1078 struct or1k_du *du_core = or1k_to_du(or1k);
1079 struct or1k_jtag *jtag = &or1k->jtag;
1080
1081 if (!du_core) {
1082 LOG_ERROR("No debug unit selected");
1083 return ERROR_FAIL;
1084 }
1085
1086 if (!jtag->tap_ip) {
1087 LOG_ERROR("No tap selected");
1088 return ERROR_FAIL;
1089 }
1090
1091 or1k->jtag.tap = target->tap;
1092 or1k->jtag.or1k_jtag_inited = 0;
1093 or1k->jtag.or1k_jtag_module_selected = -1;
1094 or1k->jtag.target = target;
1095
1096 or1k_build_reg_cache(target);
1097
1098 return ERROR_OK;
1099 }
1100
1101 static int or1k_target_create(struct target *target, Jim_Interp *interp)
1102 {
1103 if (!target->tap)
1104 return ERROR_FAIL;
1105
1106 struct or1k_common *or1k = calloc(1, sizeof(struct or1k_common));
1107
1108 target->arch_info = or1k;
1109
1110 or1k_create_reg_list(target);
1111
1112 or1k_tap_vjtag_register();
1113 or1k_tap_xilinx_bscan_register();
1114 or1k_tap_mohor_register();
1115
1116 or1k_du_adv_register();
1117
1118 return ERROR_OK;
1119 }
1120
1121 static int or1k_examine(struct target *target)
1122 {
1123 struct or1k_common *or1k = target_to_or1k(target);
1124 struct or1k_du *du_core = or1k_to_du(or1k);
1125
1126 if (!target_was_examined(target)) {
1127
1128 target_set_examined(target);
1129
1130 int running;
1131
1132 int retval = du_core->or1k_is_cpu_running(&or1k->jtag, &running);
1133 if (retval != ERROR_OK) {
1134 LOG_ERROR("Couldn't read the CPU state");
1135 return retval;
1136 } else {
1137 if (running)
1138 target->state = TARGET_RUNNING;
1139 else {
1140 LOG_DEBUG("Target is halted");
1141
1142 /* This is the first time we examine the target,
1143 * it is stalled and we don't know why. Let's
1144 * assume this is because of a debug reason.
1145 */
1146 if (target->state == TARGET_UNKNOWN)
1147 target->debug_reason = DBG_REASON_DBGRQ;
1148
1149 target->state = TARGET_HALTED;
1150 }
1151 }
1152 }
1153
1154 return ERROR_OK;
1155 }
1156
1157 static int or1k_arch_state(struct target *target)
1158 {
1159 return ERROR_OK;
1160 }
1161
1162 static int or1k_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
1163 int *reg_list_size, enum target_register_class reg_class)
1164 {
1165 struct or1k_common *or1k = target_to_or1k(target);
1166
1167 if (reg_class == REG_CLASS_GENERAL) {
1168 /* We will have this called whenever GDB connects. */
1169 int retval = or1k_save_context(target);
1170 if (retval != ERROR_OK) {
1171 LOG_ERROR("Error while calling or1k_save_context");
1172 return retval;
1173 }
1174 *reg_list_size = OR1KNUMCOREREGS;
1175 /* this is free()'d back in gdb_server.c's gdb_get_register_packet() */
1176 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1177
1178 for (int i = 0; i < OR1KNUMCOREREGS; i++)
1179 (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1180 } else {
1181 *reg_list_size = or1k->nb_regs;
1182 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1183
1184 for (int i = 0; i < or1k->nb_regs; i++)
1185 (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1186 }
1187
1188 return ERROR_OK;
1189
1190 }
1191
1192 static int or1k_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info)
1193 {
1194 return ERROR_FAIL;
1195 }
1196
1197 static int or1k_checksum_memory(struct target *target, target_addr_t address,
1198 uint32_t count, uint32_t *checksum)
1199 {
1200 return ERROR_FAIL;
1201 }
1202
1203 static int or1k_profiling(struct target *target, uint32_t *samples,
1204 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1205 {
1206 struct timeval timeout, now;
1207 struct or1k_common *or1k = target_to_or1k(target);
1208 struct or1k_du *du_core = or1k_to_du(or1k);
1209 int retval = ERROR_OK;
1210
1211 gettimeofday(&timeout, NULL);
1212 timeval_add_time(&timeout, seconds, 0);
1213
1214 LOG_INFO("Starting or1k profiling. Sampling npc as fast as we can...");
1215
1216 /* Make sure the target is running */
1217 target_poll(target);
1218 if (target->state == TARGET_HALTED)
1219 retval = target_resume(target, 1, 0, 0, 0);
1220
1221 if (retval != ERROR_OK) {
1222 LOG_ERROR("Error while resuming target");
1223 return retval;
1224 }
1225
1226 uint32_t sample_count = 0;
1227
1228 for (;;) {
1229 uint32_t reg_value;
1230 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, GROUP0 + 16 /* NPC */, 1, &reg_value);
1231 if (retval != ERROR_OK) {
1232 LOG_ERROR("Error while reading NPC");
1233 return retval;
1234 }
1235
1236 samples[sample_count++] = reg_value;
1237
1238 gettimeofday(&now, NULL);
1239 if ((sample_count >= max_num_samples) || timeval_compare(&now, &timeout) > 0) {
1240 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1241 break;
1242 }
1243 }
1244
1245 *num_samples = sample_count;
1246 return retval;
1247 }
1248
1249 COMMAND_HANDLER(or1k_tap_select_command_handler)
1250 {
1251 struct target *target = get_current_target(CMD_CTX);
1252 struct or1k_common *or1k = target_to_or1k(target);
1253 struct or1k_jtag *jtag = &or1k->jtag;
1254 struct or1k_tap_ip *or1k_tap;
1255
1256 if (CMD_ARGC != 1)
1257 return ERROR_COMMAND_SYNTAX_ERROR;
1258
1259 list_for_each_entry(or1k_tap, &tap_list, list) {
1260 if (or1k_tap->name) {
1261 if (!strcmp(CMD_ARGV[0], or1k_tap->name)) {
1262 jtag->tap_ip = or1k_tap;
1263 LOG_INFO("%s tap selected", or1k_tap->name);
1264 return ERROR_OK;
1265 }
1266 }
1267 }
1268
1269 LOG_ERROR("%s unknown, no tap selected", CMD_ARGV[0]);
1270 return ERROR_COMMAND_SYNTAX_ERROR;
1271 }
1272
1273 COMMAND_HANDLER(or1k_tap_list_command_handler)
1274 {
1275 struct or1k_tap_ip *or1k_tap;
1276
1277 if (CMD_ARGC != 0)
1278 return ERROR_COMMAND_SYNTAX_ERROR;
1279
1280 list_for_each_entry(or1k_tap, &tap_list, list) {
1281 if (or1k_tap->name)
1282 command_print(CMD, "%s", or1k_tap->name);
1283 }
1284
1285 return ERROR_OK;
1286 }
1287
1288 COMMAND_HANDLER(or1k_du_select_command_handler)
1289 {
1290 struct target *target = get_current_target(CMD_CTX);
1291 struct or1k_common *or1k = target_to_or1k(target);
1292 struct or1k_jtag *jtag = &or1k->jtag;
1293 struct or1k_du *or1k_du;
1294
1295 if (CMD_ARGC > 2)
1296 return ERROR_COMMAND_SYNTAX_ERROR;
1297
1298 list_for_each_entry(or1k_du, &du_list, list) {
1299 if (or1k_du->name) {
1300 if (!strcmp(CMD_ARGV[0], or1k_du->name)) {
1301 jtag->du_core = or1k_du;
1302 LOG_INFO("%s debug unit selected", or1k_du->name);
1303
1304 if (CMD_ARGC == 2) {
1305 int options;
1306 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], options);
1307 or1k_du->options = options;
1308 LOG_INFO("Option %x is passed to %s debug unit"
1309 , options, or1k_du->name);
1310 }
1311
1312 return ERROR_OK;
1313 }
1314 }
1315 }
1316
1317 LOG_ERROR("%s unknown, no debug unit selected", CMD_ARGV[0]);
1318 return ERROR_COMMAND_SYNTAX_ERROR;
1319 }
1320
1321 COMMAND_HANDLER(or1k_du_list_command_handler)
1322 {
1323 struct or1k_du *or1k_du;
1324
1325 if (CMD_ARGC != 0)
1326 return ERROR_COMMAND_SYNTAX_ERROR;
1327
1328 list_for_each_entry(or1k_du, &du_list, list) {
1329 if (or1k_du->name)
1330 command_print(CMD, "%s", or1k_du->name);
1331 }
1332
1333 return ERROR_OK;
1334 }
1335
1336 COMMAND_HANDLER(or1k_addreg_command_handler)
1337 {
1338 struct target *target = get_current_target(CMD_CTX);
1339 struct or1k_core_reg new_reg;
1340
1341 if (CMD_ARGC != 4)
1342 return ERROR_COMMAND_SYNTAX_ERROR;
1343
1344 new_reg.target = NULL;
1345 new_reg.or1k_common = NULL;
1346
1347 uint32_t addr;
1348 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], addr);
1349
1350 new_reg.name = strdup(CMD_ARGV[0]);
1351 new_reg.spr_num = addr;
1352 new_reg.feature = strdup(CMD_ARGV[2]);
1353 new_reg.group = strdup(CMD_ARGV[3]);
1354
1355 or1k_add_reg(target, &new_reg);
1356
1357 LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
1358 new_reg.name, addr, new_reg.group, new_reg.feature);
1359
1360 return ERROR_OK;
1361 }
1362
1363 static const struct command_registration or1k_hw_ip_command_handlers[] = {
1364 {
1365 .name = "tap_select",
1366 .handler = or1k_tap_select_command_handler,
1367 .mode = COMMAND_ANY,
1368 .usage = "name",
1369 .help = "Select the TAP core to use",
1370 },
1371 {
1372 .name = "tap_list",
1373 .handler = or1k_tap_list_command_handler,
1374 .mode = COMMAND_ANY,
1375 .usage = "",
1376 .help = "Display available TAP core",
1377 },
1378 {
1379 .name = "du_select",
1380 .handler = or1k_du_select_command_handler,
1381 .mode = COMMAND_ANY,
1382 .usage = "name",
1383 .help = "Select the Debug Unit core to use",
1384 },
1385 {
1386 .name = "du_list",
1387 .handler = or1k_du_list_command_handler,
1388 .mode = COMMAND_ANY,
1389 .usage = "select_tap name",
1390 .help = "Display available Debug Unit core",
1391 },
1392 COMMAND_REGISTRATION_DONE
1393 };
1394
1395 static const struct command_registration or1k_reg_command_handlers[] = {
1396 {
1397 .name = "addreg",
1398 .handler = or1k_addreg_command_handler,
1399 .mode = COMMAND_ANY,
1400 .usage = "name addr feature group",
1401 .help = "Add a register to the register list",
1402 },
1403 COMMAND_REGISTRATION_DONE
1404 };
1405
1406 static const struct command_registration or1k_command_handlers[] = {
1407 {
1408 .chain = or1k_reg_command_handlers,
1409 },
1410 {
1411 .chain = or1k_hw_ip_command_handlers,
1412 },
1413 COMMAND_REGISTRATION_DONE
1414 };
1415
1416
1417 struct target_type or1k_target = {
1418 .name = "or1k",
1419
1420 .poll = or1k_poll,
1421 .arch_state = or1k_arch_state,
1422
1423 .target_request_data = NULL,
1424
1425 .halt = or1k_halt,
1426 .resume = or1k_resume,
1427 .step = or1k_step,
1428
1429 .assert_reset = or1k_assert_reset,
1430 .deassert_reset = or1k_deassert_reset,
1431 .soft_reset_halt = or1k_soft_reset_halt,
1432
1433 .get_gdb_reg_list = or1k_get_gdb_reg_list,
1434
1435 .read_memory = or1k_read_memory,
1436 .write_memory = or1k_write_memory,
1437 .checksum_memory = or1k_checksum_memory,
1438
1439 .commands = or1k_command_handlers,
1440 .add_breakpoint = or1k_add_breakpoint,
1441 .remove_breakpoint = or1k_remove_breakpoint,
1442 .add_watchpoint = or1k_add_watchpoint,
1443 .remove_watchpoint = or1k_remove_watchpoint,
1444
1445 .target_create = or1k_target_create,
1446 .init_target = or1k_init_target,
1447 .examine = or1k_examine,
1448
1449 .get_gdb_fileio_info = or1k_get_gdb_fileio_info,
1450
1451 .profiling = or1k_profiling,
1452 };
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