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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / nrf5.c
blobbf8c9da5fed0fa93450f833f58e8865789d9bc66
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013 Synapse Product Development *
5 * Andrey Smirnov <andrew.smironv@gmail.com> *
6 * Angus Gratton <gus@projectgus.com> *
7 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
8 ***************************************************************************/
9
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13
14 #include "imp.h"
15 #include <helper/binarybuffer.h>
16 #include <target/algorithm.h>
17 #include <target/armv7m.h>
18 #include <helper/types.h>
19 #include <helper/time_support.h>
20 #include <helper/bits.h>
21
22 /* Both those values are constant across the current spectrum ofr nRF5 devices */
23 #define WATCHDOG_REFRESH_REGISTER 0x40010600
24 #define WATCHDOG_REFRESH_VALUE 0x6e524635
25
26 enum {
27 NRF5_FLASH_BASE = 0x00000000,
28 };
29
30 enum nrf5_ficr_registers {
31 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
32
33 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
34
35 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
36 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
37
38 NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
39 NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
40 NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
41 NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
42 NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
43 NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
44 NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
45
46 /* CONFIGID is documented on nRF51 series only.
47 * On nRF52 is present but not documented */
48 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
49
50 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
51 NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
52 NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
53 NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
54 NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
55 NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
56 };
57
58 enum nrf5_uicr_registers {
59 NRF5_UICR_BASE = 0x10001000, /* User Information
60 * Configuration Registers */
61
62 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
63
64 NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
65 };
66
67 enum nrf5_nvmc_registers {
68 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
69 * Controller Registers */
70
71 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
72
73 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
74 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
75 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
76 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
77 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
78
79 NRF5_BPROT_BASE = 0x40000000,
80 };
81
82 enum nrf5_nvmc_config_bits {
83 NRF5_NVMC_CONFIG_REN = 0x00,
84 NRF5_NVMC_CONFIG_WEN = 0x01,
85 NRF5_NVMC_CONFIG_EEN = 0x02,
86
87 };
88
89 struct nrf52_ficr_info {
90 uint32_t part;
91 uint32_t variant;
92 uint32_t package;
93 uint32_t ram;
94 uint32_t flash;
95 };
96
97 enum nrf5_features {
98 NRF5_FEATURE_SERIES_51 = BIT(0),
99 NRF5_FEATURE_SERIES_52 = BIT(1),
100 NRF5_FEATURE_BPROT = BIT(2),
101 NRF5_FEATURE_ACL_PROT = BIT(3),
102 };
103
104 struct nrf5_device_spec {
105 uint16_t hwid;
106 const char *part;
107 const char *variant;
108 const char *build_code;
109 unsigned int flash_size_kb;
110 enum nrf5_features features;
111 };
112
113 struct nrf5_info {
114 unsigned int refcount;
115
116 struct nrf5_bank {
117 struct nrf5_info *chip;
118 bool probed;
119 } bank[2];
120 struct target *target;
121
122 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
123 bool ficr_info_valid;
124 struct nrf52_ficr_info ficr_info;
125 const struct nrf5_device_spec *spec;
126 uint16_t hwid;
127 enum nrf5_features features;
128 unsigned int flash_size_kb;
129 unsigned int ram_size_kb;
130 };
131
132 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
133 { \
134 .hwid = (id), \
135 .part = pt, \
136 .variant = var, \
137 .build_code = bcode, \
138 .flash_size_kb = (fsize), \
139 .features = NRF5_FEATURE_SERIES_51, \
140 }
141
142 /*
143 * The table maps known HWIDs to the part numbers, variant
144 * build code and some other info. For nRF51 rev 1 and 2 devices
145 * this is the only way how to get the part number and variant.
146 *
147 * All tested nRF51 rev 3 devices have FICR INFO fields
148 * but the fields are not documented in RM so we keep HWIDs in
149 * this table.
150 *
151 * nRF52 and newer devices have FICR INFO documented, the autodetection
152 * can rely on it and HWIDs table is not used.
153 *
154 * The known devices table below is derived from the "nRF5x series
155 * compatibility matrix" documents.
156 *
157 * Up to date with Matrix v2.0, plus some additional HWIDs.
158 *
159 * The additional HWIDs apply where the build code in the matrix is
160 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
161 * for x==0, x!=0 means different (unspecified) HWIDs.
162 */
163 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
164 /* nRF51822 Devices (IC rev 1). */
165 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
166 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
167 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
168 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
169 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
170
171 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
172 with built-in jlink seem to use engineering samples not listed
173 in the nRF51 Series Compatibility Matrix V1.0. */
174 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
175
176 /* nRF51822 Devices (IC rev 2). */
177 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
178 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
179 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
180 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
181 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
182 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
183 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
184 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
185 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
186
187 /* nRF51822 Devices (IC rev 3). */
188 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
189 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
190 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
191 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
192 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
193 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
194 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
195 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
196 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
197
198 /* nRF51422 Devices (IC rev 1). */
199 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
200 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
201 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
202
203 /* nRF51422 Devices (IC rev 2). */
204 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
205 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
206 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
207 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
208
209 /* nRF51422 Devices (IC rev 3). */
210 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
211 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
212 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
213 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
214 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
215 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
216 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
217
218 /* The driver fully autodetects nRF52 series devices by FICR INFO,
219 * no need for nRF52xxx HWIDs in this table */
220 };
221
222 struct nrf5_device_package {
223 uint32_t package;
224 const char *code;
225 };
226
227 /* Newer devices have FICR INFO.PACKAGE.
228 * This table converts its value to two character code */
229 static const struct nrf5_device_package nrf52_packages_table[] = {
230 { 0x2000, "QF" },
231 { 0x2001, "CH" },
232 { 0x2002, "CI" },
233 { 0x2003, "QC" },
234 { 0x2004, "QI/CA" }, /* differs nRF52805, 810, 811: CA, nRF52833, 840: QI */
235 { 0x2005, "CK" },
236 { 0x2007, "QD" },
237 { 0x2008, "CJ" },
238 { 0x2009, "CF" },
239 };
240
241 const struct flash_driver nrf5_flash, nrf51_flash;
242
243 static bool nrf5_bank_is_probed(const struct flash_bank *bank)
244 {
245 struct nrf5_bank *nbank = bank->driver_priv;
246 assert(nbank);
247
248 return nbank->probed;
249 }
250
251 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
252 {
253 uint32_t ready;
254 int res;
255 int timeout_ms = 340;
256 int64_t ts_start = timeval_ms();
257
258 do {
259 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
260 if (res != ERROR_OK) {
261 LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
262 return res;
263 }
264
265 if (ready == 0x00000001)
266 return ERROR_OK;
267
268 keep_alive();
269
270 } while ((timeval_ms()-ts_start) < timeout_ms);
271
272 LOG_DEBUG("Timed out waiting for NVMC_READY");
273 return ERROR_FLASH_BUSY;
274 }
275
276 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
277 {
278 int res;
279 res = target_write_u32(chip->target,
280 NRF5_NVMC_CONFIG,
281 NRF5_NVMC_CONFIG_EEN);
282
283 if (res != ERROR_OK) {
284 LOG_ERROR("Failed to enable erase operation");
285 return res;
286 }
287
288 /*
289 According to NVMC examples in Nordic SDK busy status must be
290 checked after writing to NVMC_CONFIG
291 */
292 res = nrf5_wait_for_nvmc(chip);
293 if (res != ERROR_OK)
294 LOG_ERROR("Erase enable did not complete");
295
296 return res;
297 }
298
299 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
300 {
301 int res;
302 res = target_write_u32(chip->target,
303 NRF5_NVMC_CONFIG,
304 NRF5_NVMC_CONFIG_WEN);
305
306 if (res != ERROR_OK) {
307 LOG_ERROR("Failed to enable write operation");
308 return res;
309 }
310
311 /*
312 According to NVMC examples in Nordic SDK busy status must be
313 checked after writing to NVMC_CONFIG
314 */
315 res = nrf5_wait_for_nvmc(chip);
316 if (res != ERROR_OK)
317 LOG_ERROR("Write enable did not complete");
318
319 return res;
320 }
321
322 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
323 {
324 int res;
325 res = target_write_u32(chip->target,
326 NRF5_NVMC_CONFIG,
327 NRF5_NVMC_CONFIG_REN);
328
329 if (res != ERROR_OK) {
330 LOG_ERROR("Failed to enable read-only operation");
331 return res;
332 }
333 /*
334 According to NVMC examples in Nordic SDK busy status must be
335 checked after writing to NVMC_CONFIG
336 */
337 res = nrf5_wait_for_nvmc(chip);
338 if (res != ERROR_OK)
339 LOG_ERROR("Read only enable did not complete");
340
341 return res;
342 }
343
344 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
345 uint32_t erase_register, uint32_t erase_value)
346 {
347 int res;
348
349 res = nrf5_nvmc_erase_enable(chip);
350 if (res != ERROR_OK)
351 goto error;
352
353 res = target_write_u32(chip->target,
354 erase_register,
355 erase_value);
356 if (res != ERROR_OK)
357 goto set_read_only;
358
359 res = nrf5_wait_for_nvmc(chip);
360 if (res != ERROR_OK)
361 goto set_read_only;
362
363 return nrf5_nvmc_read_only(chip);
364
365 set_read_only:
366 nrf5_nvmc_read_only(chip);
367 error:
368 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
369 erase_register, erase_value);
370 return ERROR_FAIL;
371 }
372
373 static int nrf5_protect_check_clenr0(struct flash_bank *bank)
374 {
375 int res;
376 uint32_t clenr0;
377
378 struct nrf5_bank *nbank = bank->driver_priv;
379 assert(nbank);
380 struct nrf5_info *chip = nbank->chip;
381 assert(chip);
382
383 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
384 &clenr0);
385 if (res != ERROR_OK) {
386 LOG_ERROR("Couldn't read code region 0 size[FICR]");
387 return res;
388 }
389
390 if (clenr0 == 0xFFFFFFFF) {
391 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
392 &clenr0);
393 if (res != ERROR_OK) {
394 LOG_ERROR("Couldn't read code region 0 size[UICR]");
395 return res;
396 }
397 }
398
399 for (unsigned int i = 0; i < bank->num_sectors; i++)
400 bank->sectors[i].is_protected =
401 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
402
403 return ERROR_OK;
404 }
405
406 static int nrf5_protect_check_bprot(struct flash_bank *bank)
407 {
408 struct nrf5_bank *nbank = bank->driver_priv;
409 assert(nbank);
410 struct nrf5_info *chip = nbank->chip;
411 assert(chip);
412
413 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
414 uint32_t bprot_reg = 0;
415 int res;
416
417 for (unsigned int i = 0; i < bank->num_sectors; i++) {
418 unsigned int bit = i % 32;
419 if (bit == 0) {
420 unsigned int n_reg = i / 32;
421 if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
422 break;
423
424 res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
425 if (res != ERROR_OK)
426 return res;
427 }
428 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
429 }
430 return ERROR_OK;
431 }
432
433 static int nrf5_protect_check(struct flash_bank *bank)
434 {
435 /* UICR cannot be write protected so just return early */
436 if (bank->base == NRF5_UICR_BASE)
437 return ERROR_OK;
438
439 struct nrf5_bank *nbank = bank->driver_priv;
440 assert(nbank);
441 struct nrf5_info *chip = nbank->chip;
442 assert(chip);
443
444 if (chip->features & NRF5_FEATURE_BPROT)
445 return nrf5_protect_check_bprot(bank);
446
447 if (chip->features & NRF5_FEATURE_SERIES_51)
448 return nrf5_protect_check_clenr0(bank);
449
450 LOG_WARNING("Flash protection of this nRF device is not supported");
451 return ERROR_FLASH_OPER_UNSUPPORTED;
452 }
453
454 static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
455 unsigned int last)
456 {
457 int res;
458 uint32_t clenr0, ppfc;
459
460 struct nrf5_bank *nbank = bank->driver_priv;
461 assert(nbank);
462 struct nrf5_info *chip = nbank->chip;
463 assert(chip);
464
465 if (first != 0) {
466 LOG_ERROR("Code region 0 must start at the beginning of the bank");
467 return ERROR_FAIL;
468 }
469
470 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
471 &ppfc);
472 if (res != ERROR_OK) {
473 LOG_ERROR("Couldn't read PPFC register");
474 return res;
475 }
476
477 if ((ppfc & 0xFF) == 0x00) {
478 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
479 return ERROR_FAIL;
480 }
481
482 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
483 &clenr0);
484 if (res != ERROR_OK) {
485 LOG_ERROR("Couldn't read code region 0 size from UICR");
486 return res;
487 }
488
489 if (!set || clenr0 != 0xFFFFFFFF) {
490 LOG_ERROR("You need to perform chip erase before changing the protection settings");
491 return ERROR_FAIL;
492 }
493
494 res = nrf5_nvmc_write_enable(chip);
495 if (res != ERROR_OK)
496 goto error;
497
498 clenr0 = bank->sectors[last].offset + bank->sectors[last].size;
499 res = target_write_u32(chip->target, NRF51_UICR_CLENR0, clenr0);
500
501 int res2 = nrf5_wait_for_nvmc(chip);
502
503 if (res == ERROR_OK)
504 res = res2;
505
506 if (res == ERROR_OK)
507 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
508 else
509 LOG_ERROR("Couldn't write code region 0 size to UICR");
510
511 error:
512 nrf5_nvmc_read_only(chip);
513
514 return res;
515 }
516
517 static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
518 unsigned int last)
519 {
520 /* UICR cannot be write protected so just bail out early */
521 if (bank->base == NRF5_UICR_BASE) {
522 LOG_ERROR("UICR page does not support protection");
523 return ERROR_FLASH_OPER_UNSUPPORTED;
524 }
525
526 if (bank->target->state != TARGET_HALTED) {
527 LOG_ERROR("Target not halted");
528 return ERROR_TARGET_NOT_HALTED;
529 }
530
531 struct nrf5_bank *nbank = bank->driver_priv;
532 assert(nbank);
533 struct nrf5_info *chip = nbank->chip;
534 assert(chip);
535
536 if (chip->features & NRF5_FEATURE_SERIES_51)
537 return nrf5_protect_clenr0(bank, set, first, last);
538
539 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
540 return ERROR_FLASH_OPER_UNSUPPORTED;
541 }
542
543 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
544 {
545 uint8_t b[4];
546
547 h_u32_to_be(b, variant);
548 if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
549 memcpy(bf, b, 4);
550 bf[4] = 0;
551 return true;
552 }
553
554 strcpy(bf, "xxxx");
555 return false;
556 }
557
558 static const char *nrf5_decode_info_package(uint32_t package)
559 {
560 for (size_t i = 0; i < ARRAY_SIZE(nrf52_packages_table); i++) {
561 if (nrf52_packages_table[i].package == package)
562 return nrf52_packages_table[i].code;
563 }
564 return "xx";
565 }
566
567 static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
568 {
569 int res;
570 if (chip->spec) {
571 res = snprintf(buf, buf_size, "nRF%s-%s(build code: %s)",
572 chip->spec->part, chip->spec->variant, chip->spec->build_code);
573 } else if (chip->ficr_info_valid) {
574 char variant[5];
575 nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
576 res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
577 chip->ficr_info.part,
578 nrf5_decode_info_package(chip->ficr_info.package),
579 variant, &variant[2]);
580 } else {
581 res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid);
582 }
583
584 /* safety: */
585 if (res <= 0 || (unsigned int)res >= buf_size) {
586 LOG_ERROR("BUG: buffer problem in %s", __func__);
587 return ERROR_FAIL;
588 }
589 return ERROR_OK;
590 }
591
592 static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
593 {
594 struct nrf5_bank *nbank = bank->driver_priv;
595 assert(nbank);
596 struct nrf5_info *chip = nbank->chip;
597 assert(chip);
598
599 char chip_type_str[256];
600 if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
601 return ERROR_FAIL;
602
603 command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
604 chip_type_str, chip->flash_size_kb, chip->ram_size_kb);
605 return ERROR_OK;
606 }
607
608 static int nrf5_read_ficr_info(struct nrf5_info *chip)
609 {
610 int res;
611 struct target *target = chip->target;
612
613 chip->ficr_info_valid = false;
614
615 res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
616 if (res != ERROR_OK) {
617 LOG_DEBUG("Couldn't read FICR INFO.PART register");
618 return res;
619 }
620
621 uint32_t series = chip->ficr_info.part & 0xfffff000;
622 switch (series) {
623 case 0x51000:
624 chip->features = NRF5_FEATURE_SERIES_51;
625 break;
626
627 case 0x52000:
628 chip->features = NRF5_FEATURE_SERIES_52;
629
630 switch (chip->ficr_info.part) {
631 case 0x52805:
632 case 0x52810:
633 case 0x52811:
634 case 0x52832:
635 chip->features |= NRF5_FEATURE_BPROT;
636 break;
637
638 case 0x52820:
639 case 0x52833:
640 case 0x52840:
641 chip->features |= NRF5_FEATURE_ACL_PROT;
642 break;
643 }
644 break;
645
646 default:
647 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
648 PRIx32, chip->ficr_info.part);
649 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
650 }
651
652 /* Now we know the device has FICR INFO filled by something relevant:
653 * Although it is not documented, the tested nRF51 rev 3 devices
654 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
655 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
656 * nRF52 devices have FICR INFO documented and always filled. */
657
658 res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
659 if (res != ERROR_OK)
660 return res;
661
662 res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
663 if (res != ERROR_OK)
664 return res;
665
666 res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
667 if (res != ERROR_OK)
668 return res;
669
670 res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
671 if (res != ERROR_OK)
672 return res;
673
674 chip->ficr_info_valid = true;
675 return ERROR_OK;
676 }
677
678 static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
679 {
680 int res;
681
682 *ram_size = 0;
683
684 uint32_t numramblock;
685 res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
686 if (res != ERROR_OK) {
687 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
688 return res;
689 }
690
691 if (numramblock < 1 || numramblock > 4) {
692 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
693 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
694 }
695
696 for (unsigned int i = 0; i < numramblock; i++) {
697 uint32_t sizeramblock;
698 res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
699 if (res != ERROR_OK) {
700 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
701 return res;
702 }
703 if (sizeramblock < 1024 || sizeramblock > 65536)
704 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
705 else
706 *ram_size += sizeramblock;
707 }
708 return res;
709 }
710
711 static int nrf5_probe(struct flash_bank *bank)
712 {
713 int res;
714
715 struct nrf5_bank *nbank = bank->driver_priv;
716 assert(nbank);
717 struct nrf5_info *chip = nbank->chip;
718 assert(chip);
719 struct target *target = chip->target;
720
721 uint32_t configid;
722 res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid);
723 if (res != ERROR_OK) {
724 LOG_ERROR("Couldn't read CONFIGID register");
725 return res;
726 }
727
728 /* HWID is stored in the lower two bytes of the CONFIGID register */
729 chip->hwid = configid & 0xFFFF;
730
731 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
732 chip->features = NRF5_FEATURE_SERIES_51;
733
734 /* Don't bail out on error for the case that some old engineering
735 * sample has FICR INFO registers unreadable. We can proceed anyway. */
736 (void)nrf5_read_ficr_info(chip);
737
738 chip->spec = NULL;
739 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
740 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
741 chip->spec = &nrf5_known_devices_table[i];
742 chip->features = chip->spec->features;
743 break;
744 }
745 }
746
747 if (chip->spec && chip->ficr_info_valid) {
748 /* check if HWID table gives the same part as FICR INFO */
749 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
750 LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
751 PRIx32, chip->hwid, chip->ficr_info.part);
752 }
753
754 if (chip->ficr_info_valid) {
755 chip->ram_size_kb = chip->ficr_info.ram;
756 } else {
757 uint32_t ram_size;
758 nrf5_get_ram_size(target, &ram_size);
759 chip->ram_size_kb = ram_size / 1024;
760 }
761
762 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
763 uint32_t flash_page_size;
764 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
765 &flash_page_size);
766 if (res != ERROR_OK) {
767 LOG_ERROR("Couldn't read code page size");
768 return res;
769 }
770
771 /* Note the register name is misleading,
772 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
773 uint32_t num_sectors;
774 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
775 if (res != ERROR_OK) {
776 LOG_ERROR("Couldn't read code memory size");
777 return res;
778 }
779
780 chip->flash_size_kb = num_sectors * flash_page_size / 1024;
781
782 if (!chip->bank[0].probed && !chip->bank[1].probed) {
783 char chip_type_str[256];
784 if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
785 return ERROR_FAIL;
786 const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
787 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
788 device_is_unknown ? "Unknown device: " : "",
789 chip_type_str,
790 chip->flash_size_kb,
791 chip->ram_size_kb);
792 }
793
794 free(bank->sectors);
795
796 if (bank->base == NRF5_FLASH_BASE) {
797 /* Sanity check */
798 if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
799 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
800 if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
801 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
802
803 bank->num_sectors = num_sectors;
804 bank->size = num_sectors * flash_page_size;
805
806 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
807 if (!bank->sectors)
808 return ERROR_FAIL;
809
810 chip->bank[0].probed = true;
811
812 } else {
813 bank->num_sectors = 1;
814 bank->size = flash_page_size;
815
816 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
817 if (!bank->sectors)
818 return ERROR_FAIL;
819
820 bank->sectors[0].is_protected = 0;
821
822 chip->bank[1].probed = true;
823 }
824
825 return ERROR_OK;
826 }
827
828 static int nrf5_auto_probe(struct flash_bank *bank)
829 {
830 if (nrf5_bank_is_probed(bank))
831 return ERROR_OK;
832
833 return nrf5_probe(bank);
834 }
835
836 static int nrf5_erase_all(struct nrf5_info *chip)
837 {
838 LOG_DEBUG("Erasing all non-volatile memory");
839 return nrf5_nvmc_generic_erase(chip,
840 NRF5_NVMC_ERASEALL,
841 0x00000001);
842 }
843
844 static int nrf5_erase_page(struct flash_bank *bank,
845 struct nrf5_info *chip,
846 struct flash_sector *sector)
847 {
848 int res;
849
850 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
851
852 if (bank->base == NRF5_UICR_BASE) {
853 if (chip->features & NRF5_FEATURE_SERIES_51) {
854 uint32_t ppfc;
855 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
856 &ppfc);
857 if (res != ERROR_OK) {
858 LOG_ERROR("Couldn't read PPFC register");
859 return res;
860 }
861
862 if ((ppfc & 0xFF) == 0xFF) {
863 /* We can't erase the UICR. Double-check to
864 see if it's already erased before complaining. */
865 default_flash_blank_check(bank);
866 if (sector->is_erased == 1)
867 return ERROR_OK;
868
869 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
870 return ERROR_FAIL;
871 }
872 }
873
874 res = nrf5_nvmc_generic_erase(chip,
875 NRF5_NVMC_ERASEUICR,
876 0x00000001);
877
878
879 } else {
880 res = nrf5_nvmc_generic_erase(chip,
881 NRF5_NVMC_ERASEPAGE,
882 sector->offset);
883 }
884
885 return res;
886 }
887
888 /* Start a low level flash write for the specified region */
889 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
890 {
891 struct target *target = chip->target;
892 uint32_t buffer_size = 8192;
893 struct working_area *write_algorithm;
894 struct working_area *source;
895 struct reg_param reg_params[6];
896 struct armv7m_algorithm armv7m_info;
897 int retval = ERROR_OK;
898
899 static const uint8_t nrf5_flash_write_code[] = {
900 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
901 };
902
903 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
904 assert(bytes % 4 == 0);
905
906 /* allocate working area with flash programming code */
907 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
908 &write_algorithm) != ERROR_OK) {
909 LOG_WARNING("no working area available, falling back to slow memory writes");
910
911 for (; bytes > 0; bytes -= 4) {
912 retval = target_write_memory(target, address, 4, 1, buffer);
913 if (retval != ERROR_OK)
914 return retval;
915
916 retval = nrf5_wait_for_nvmc(chip);
917 if (retval != ERROR_OK)
918 return retval;
919
920 address += 4;
921 buffer += 4;
922 }
923
924 return ERROR_OK;
925 }
926
927 retval = target_write_buffer(target, write_algorithm->address,
928 sizeof(nrf5_flash_write_code),
929 nrf5_flash_write_code);
930 if (retval != ERROR_OK)
931 return retval;
932
933 /* memory buffer */
934 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
935 buffer_size /= 2;
936 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
937 if (buffer_size <= 256) {
938 /* free working area, write algorithm already allocated */
939 target_free_working_area(target, write_algorithm);
940
941 LOG_WARNING("No large enough working area available, can't do block memory writes");
942 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
943 }
944 }
945
946 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
947 armv7m_info.core_mode = ARM_MODE_THREAD;
948
949 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
950 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
951 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
952 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
953 init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT); /* watchdog refresh value */
954 init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT); /* watchdog refresh register address */
955
956 buf_set_u32(reg_params[0].value, 0, 32, bytes);
957 buf_set_u32(reg_params[1].value, 0, 32, source->address);
958 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
959 buf_set_u32(reg_params[3].value, 0, 32, address);
960 buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
961 buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
962
963 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
964 0, NULL,
965 ARRAY_SIZE(reg_params), reg_params,
966 source->address, source->size,
967 write_algorithm->address, write_algorithm->address + sizeof(nrf5_flash_write_code) - 2,
968 &armv7m_info);
969
970 target_free_working_area(target, source);
971 target_free_working_area(target, write_algorithm);
972
973 destroy_reg_param(&reg_params[0]);
974 destroy_reg_param(&reg_params[1]);
975 destroy_reg_param(&reg_params[2]);
976 destroy_reg_param(&reg_params[3]);
977 destroy_reg_param(&reg_params[4]);
978 destroy_reg_param(&reg_params[5]);
979
980 return retval;
981 }
982
983 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
984 uint32_t offset, uint32_t count)
985 {
986 int res;
987
988 if (bank->target->state != TARGET_HALTED) {
989 LOG_ERROR("Target not halted");
990 return ERROR_TARGET_NOT_HALTED;
991 }
992
993 struct nrf5_bank *nbank = bank->driver_priv;
994 assert(nbank);
995 struct nrf5_info *chip = nbank->chip;
996 assert(chip);
997
998 assert(offset % 4 == 0);
999 assert(count % 4 == 0);
1000
1001 /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1002 * RM reads: Code running from code region 1 will not be able to write
1003 * to code region 0.
1004 * Unfortunately the flash loader running from RAM can write to both
1005 * code regions without any hint the protection is violated.
1006 *
1007 * Update protection state and check if any flash sector to be written
1008 * is protected. */
1009 if (chip->features & NRF5_FEATURE_SERIES_51) {
1010
1011 res = nrf5_protect_check_clenr0(bank);
1012 if (res != ERROR_OK)
1013 return res;
1014
1015 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1016 struct flash_sector *bs = &bank->sectors[sector];
1017
1018 /* Start offset in or before this sector? */
1019 /* End offset in or behind this sector? */
1020 if ((offset < (bs->offset + bs->size))
1021 && ((offset + count - 1) >= bs->offset)
1022 && bs->is_protected == 1) {
1023 LOG_ERROR("Write refused, sector %d is protected", sector);
1024 return ERROR_FLASH_PROTECTED;
1025 }
1026 }
1027 }
1028
1029 res = nrf5_nvmc_write_enable(chip);
1030 if (res != ERROR_OK)
1031 goto error;
1032
1033 res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
1034 if (res != ERROR_OK)
1035 goto error;
1036
1037 return nrf5_nvmc_read_only(chip);
1038
1039 error:
1040 nrf5_nvmc_read_only(chip);
1041 LOG_ERROR("Failed to write to nrf5 flash");
1042 return res;
1043 }
1044
1045 static int nrf5_erase(struct flash_bank *bank, unsigned int first,
1046 unsigned int last)
1047 {
1048 int res;
1049
1050 if (bank->target->state != TARGET_HALTED) {
1051 LOG_ERROR("Target not halted");
1052 return ERROR_TARGET_NOT_HALTED;
1053 }
1054
1055 struct nrf5_bank *nbank = bank->driver_priv;
1056 assert(nbank);
1057 struct nrf5_info *chip = nbank->chip;
1058 assert(chip);
1059
1060 /* UICR CLENR0 based protection used on nRF51 prevents erase
1061 * absolutely silently. NVMC has no flag to indicate the protection
1062 * was violated.
1063 *
1064 * Update protection state and check if any flash sector to be erased
1065 * is protected. */
1066 if (chip->features & NRF5_FEATURE_SERIES_51) {
1067
1068 res = nrf5_protect_check_clenr0(bank);
1069 if (res != ERROR_OK)
1070 return res;
1071 }
1072
1073 /* For each sector to be erased */
1074 for (unsigned int s = first; s <= last; s++) {
1075
1076 if (chip->features & NRF5_FEATURE_SERIES_51
1077 && bank->sectors[s].is_protected == 1) {
1078 LOG_ERROR("Flash sector %d is protected", s);
1079 return ERROR_FLASH_PROTECTED;
1080 }
1081
1082 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
1083 if (res != ERROR_OK) {
1084 LOG_ERROR("Error erasing sector %d", s);
1085 return res;
1086 }
1087 }
1088
1089 return ERROR_OK;
1090 }
1091
1092 static void nrf5_free_driver_priv(struct flash_bank *bank)
1093 {
1094 struct nrf5_bank *nbank = bank->driver_priv;
1095 assert(nbank);
1096 struct nrf5_info *chip = nbank->chip;
1097 if (!chip)
1098 return;
1099
1100 chip->refcount--;
1101 if (chip->refcount == 0) {
1102 free(chip);
1103 bank->driver_priv = NULL;
1104 }
1105 }
1106
1107 static struct nrf5_info *nrf5_get_chip(struct target *target)
1108 {
1109 struct flash_bank *bank_iter;
1110
1111 /* iterate over nrf5 banks of same target */
1112 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
1113 if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
1114 continue;
1115
1116 if (bank_iter->target != target)
1117 continue;
1118
1119 struct nrf5_bank *nbank = bank_iter->driver_priv;
1120 if (!nbank)
1121 continue;
1122
1123 if (nbank->chip)
1124 return nbank->chip;
1125 }
1126 return NULL;
1127 }
1128
1129 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1130 {
1131 struct nrf5_info *chip;
1132 struct nrf5_bank *nbank = NULL;
1133
1134 if (bank->driver == &nrf51_flash)
1135 LOG_WARNING("Flash driver 'nrf51' is deprecated! Use 'nrf5' instead.");
1136
1137 switch (bank->base) {
1138 case NRF5_FLASH_BASE:
1139 case NRF5_UICR_BASE:
1140 break;
1141 default:
1142 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
1143 return ERROR_FAIL;
1144 }
1145
1146 chip = nrf5_get_chip(bank->target);
1147 if (!chip) {
1148 /* Create a new chip */
1149 chip = calloc(1, sizeof(*chip));
1150 if (!chip)
1151 return ERROR_FAIL;
1152
1153 chip->target = bank->target;
1154 }
1155
1156 switch (bank->base) {
1157 case NRF5_FLASH_BASE:
1158 nbank = &chip->bank[0];
1159 break;
1160 case NRF5_UICR_BASE:
1161 nbank = &chip->bank[1];
1162 break;
1163 }
1164 assert(nbank);
1165
1166 chip->refcount++;
1167 nbank->chip = chip;
1168 nbank->probed = false;
1169 bank->driver_priv = nbank;
1170 bank->write_start_alignment = bank->write_end_alignment = 4;
1171
1172 return ERROR_OK;
1173 }
1174
1175 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1176 {
1177 int res;
1178 struct flash_bank *bank = NULL;
1179 struct target *target = get_current_target(CMD_CTX);
1180
1181 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1182 if (res != ERROR_OK)
1183 return res;
1184
1185 assert(bank);
1186
1187 if (target->state != TARGET_HALTED) {
1188 LOG_ERROR("Target not halted");
1189 return ERROR_TARGET_NOT_HALTED;
1190 }
1191
1192 struct nrf5_bank *nbank = bank->driver_priv;
1193 assert(nbank);
1194 struct nrf5_info *chip = nbank->chip;
1195 assert(chip);
1196
1197 if (chip->features & NRF5_FEATURE_SERIES_51) {
1198 uint32_t ppfc;
1199 res = target_read_u32(target, NRF51_FICR_PPFC,
1200 &ppfc);
1201 if (res != ERROR_OK) {
1202 LOG_ERROR("Couldn't read PPFC register");
1203 return res;
1204 }
1205
1206 if ((ppfc & 0xFF) == 0x00) {
1207 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1208 "mass erase command won't work.");
1209 return ERROR_FAIL;
1210 }
1211 }
1212
1213 res = nrf5_erase_all(chip);
1214 if (res == ERROR_OK) {
1215 LOG_INFO("Mass erase completed.");
1216 if (chip->features & NRF5_FEATURE_SERIES_51)
1217 LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1218
1219 } else {
1220 LOG_ERROR("Failed to erase the chip");
1221 }
1222
1223 return res;
1224 }
1225
1226
1227 static const struct command_registration nrf5_exec_command_handlers[] = {
1228 {
1229 .name = "mass_erase",
1230 .handler = nrf5_handle_mass_erase_command,
1231 .mode = COMMAND_EXEC,
1232 .help = "Erase all flash contents of the chip.",
1233 .usage = "",
1234 },
1235 COMMAND_REGISTRATION_DONE
1236 };
1237
1238 static const struct command_registration nrf5_command_handlers[] = {
1239 {
1240 .name = "nrf5",
1241 .mode = COMMAND_ANY,
1242 .help = "nrf5 flash command group",
1243 .usage = "",
1244 .chain = nrf5_exec_command_handlers,
1245 },
1246 {
1247 .name = "nrf51",
1248 .mode = COMMAND_ANY,
1249 .help = "nrf51 flash command group",
1250 .usage = "",
1251 .chain = nrf5_exec_command_handlers,
1252 },
1253 COMMAND_REGISTRATION_DONE
1254 };
1255
1256 const struct flash_driver nrf5_flash = {
1257 .name = "nrf5",
1258 .commands = nrf5_command_handlers,
1259 .flash_bank_command = nrf5_flash_bank_command,
1260 .info = nrf5_info,
1261 .erase = nrf5_erase,
1262 .protect = nrf5_protect,
1263 .write = nrf5_write,
1264 .read = default_flash_read,
1265 .probe = nrf5_probe,
1266 .auto_probe = nrf5_auto_probe,
1267 .erase_check = default_flash_blank_check,
1268 .protect_check = nrf5_protect_check,
1269 .free_driver_priv = nrf5_free_driver_priv,
1270 };
1271
1272 /* We need to retain the flash-driver name as well as the commands
1273 * for backwards compatibility */
1274 const struct flash_driver nrf51_flash = {
1275 .name = "nrf51",
1276 .commands = nrf5_command_handlers,
1277 .flash_bank_command = nrf5_flash_bank_command,
1278 .info = nrf5_info,
1279 .erase = nrf5_erase,
1280 .protect = nrf5_protect,
1281 .write = nrf5_write,
1282 .read = default_flash_read,
1283 .probe = nrf5_probe,
1284 .auto_probe = nrf5_auto_probe,
1285 .erase_check = default_flash_blank_check,
1286 .protect_check = nrf5_protect_check,
1287 .free_driver_priv = nrf5_free_driver_priv,
1288 };
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