1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
26 * Freescale iMX2* OpenOCD NAND Flash controller support.
27 * based on Freescale iMX3* OpenOCD NAND Flash controller support.
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; imx27_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
46 #include <target/target.h>
48 /* This permits to print (in LOG_INFO) how much bytes
49 * has been written after a page read or write.
50 * This is useful when OpenOCD is used with a graphical
51 * front-end to estimate progression of the global read/write
53 #undef _MX2_PRINT_STAT
54 //#define _MX2_PRINT_STAT
56 static const char target_not_halted_err_msg
[] =
57 "target must be halted to use mx2 NAND flash controller";
58 static const char data_block_size_err_msg
[] =
59 "minimal granularity is one half-word, %" PRId32
" is incorrect";
60 static const char sram_buffer_bounds_err_msg
[] =
61 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
62 static const char get_status_register_err_msg
[] = "can't get NAND status";
63 static uint32_t in_sram_address
;
64 static unsigned char sign_of_sequental_byte_read
;
66 static int initialize_nf_controller(struct nand_device
*nand
);
67 static int get_next_byte_from_sram_buffer(struct target
* target
, uint8_t * value
);
68 static int get_next_halfword_from_sram_buffer(struct target
* target
,
70 static int poll_for_complete_op(struct target
* target
, const char *text
);
71 static int validate_target_state(struct nand_device
*nand
);
72 static int do_data_output(struct nand_device
*nand
);
74 static int imx27_command(struct nand_device
*nand
, uint8_t command
);
75 static int imx27_address(struct nand_device
*nand
, uint8_t address
);
77 NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command
)
79 struct mx2_nf_controller
*mx2_nf_info
;
82 mx2_nf_info
= malloc(sizeof(struct mx2_nf_controller
));
83 if (mx2_nf_info
== NULL
) {
84 LOG_ERROR("no memory for nand controller");
88 nand
->controller_priv
= mx2_nf_info
;
90 LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
94 * check hwecc requirements
97 hwecc_needed
= strcmp(CMD_ARGV
[2], "hwecc");
98 if (hwecc_needed
== 0)
99 mx2_nf_info
->flags
.hw_ecc_enabled
= 1;
101 mx2_nf_info
->flags
.hw_ecc_enabled
= 0;
103 mx2_nf_info
->optype
= MX2_NF_DATAOUT_PAGE
;
104 mx2_nf_info
->fin
= MX2_NF_FIN_NONE
;
105 mx2_nf_info
->flags
.target_little_endian
=
106 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
108 * testing host endianness
111 if (*(char *) &x
== 1)
112 mx2_nf_info
->flags
.host_little_endian
= 1;
114 mx2_nf_info
->flags
.host_little_endian
= 0;
118 static int imx27_init(struct nand_device
*nand
)
120 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
121 struct target
*target
= nand
->target
;
123 int validate_target_result
;
124 uint16_t buffsize_register_content
;
125 uint32_t pcsr_register_content
;
127 uint16_t nand_status_content
;
129 * validate target state
131 validate_target_result
= validate_target_state(nand
);
132 if (validate_target_result
!= ERROR_OK
)
133 return validate_target_result
;
135 target_read_u16(target
, MX2_NF_BUFSIZ
, &buffsize_register_content
);
136 mx2_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
138 target_read_u32(target
, MX2_FMCR
, &pcsr_register_content
);
139 if (!nand
->bus_width
) {
140 /* bus_width not yet defined. Read it from MX2_FMCR */
142 (pcsr_register_content
& MX2_FMCR_NF_16BIT_SEL
) ? 16 : 8;
144 /* bus_width forced in soft. Sync it to MX2_FMCR */
145 pcsr_register_content
|=
146 ((nand
->bus_width
== 16) ? MX2_FMCR_NF_16BIT_SEL
: 0x00000000);
147 target_write_u32(target
, MX2_FMCR
, pcsr_register_content
);
149 if (nand
->bus_width
== 16)
150 LOG_DEBUG("MX2_NF : bus is 16-bit width");
152 LOG_DEBUG("MX2_NF : bus is 8-bit width");
154 if (!nand
->page_size
) {
156 (pcsr_register_content
& MX2_FMCR_NF_FMS
) ? 2048 : 512;
158 pcsr_register_content
|=
159 ((nand
->page_size
== 2048) ? MX2_FMCR_NF_FMS
: 0x00000000);
160 target_write_u32(target
, MX2_FMCR
, pcsr_register_content
);
162 if (mx2_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048)) {
163 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
164 "pagesize 2048 is incompatible with it");
166 LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
169 initialize_nf_controller(nand
);
172 retval
|= imx27_command(nand
, NAND_CMD_STATUS
);
173 retval
|= imx27_address(nand
, 0x00);
174 retval
|= do_data_output(nand
);
175 if (retval
!= ERROR_OK
) {
176 LOG_ERROR(get_status_register_err_msg
);
179 target_read_u16(target
, MX2_NF_MAIN_BUFFER0
, &nand_status_content
);
180 if (!(nand_status_content
& 0x0080)) {
181 LOG_INFO("NAND read-only");
182 mx2_nf_info
->flags
.nand_readonly
= 1;
184 mx2_nf_info
->flags
.nand_readonly
= 0;
189 static int imx27_read_data(struct nand_device
*nand
, void *data
)
191 struct target
*target
= nand
->target
;
192 int validate_target_result
;
193 int try_data_output_from_nand_chip
;
195 * validate target state
197 validate_target_result
= validate_target_state(nand
);
198 if (validate_target_result
!= ERROR_OK
)
199 return validate_target_result
;
202 * get data from nand chip
204 try_data_output_from_nand_chip
= do_data_output(nand
);
205 if (try_data_output_from_nand_chip
!= ERROR_OK
) {
206 LOG_ERROR("imx27_read_data : read data failed : '%x'",
207 try_data_output_from_nand_chip
);
208 return try_data_output_from_nand_chip
;
211 if (nand
->bus_width
== 16)
212 get_next_halfword_from_sram_buffer(target
, data
);
214 get_next_byte_from_sram_buffer(target
, data
);
219 static int imx27_write_data(struct nand_device
*nand
, uint16_t data
)
221 LOG_ERROR("write_data() not implemented");
222 return ERROR_NAND_OPERATION_FAILED
;
225 static int imx27_reset(struct nand_device
*nand
)
228 * validate target state
230 int validate_target_result
;
231 validate_target_result
= validate_target_state(nand
);
232 if (validate_target_result
!= ERROR_OK
)
233 return validate_target_result
;
234 initialize_nf_controller(nand
);
238 static int imx27_command(struct nand_device
*nand
, uint8_t command
)
240 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
241 struct target
*target
= nand
->target
;
242 int validate_target_result
;
245 * validate target state
247 validate_target_result
= validate_target_state(nand
);
248 if (validate_target_result
!= ERROR_OK
)
249 return validate_target_result
;
252 case NAND_CMD_READOOB
:
253 command
= NAND_CMD_READ0
;
254 /* set read point for data_read() and read_block_data() to
255 * spare area in SRAM buffer
257 in_sram_address
= MX2_NF_SPARE_BUFFER0
;
260 command
= NAND_CMD_READ0
;
262 * offset == one half of page size
265 MX2_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
268 in_sram_address
= MX2_NF_MAIN_BUFFER0
;
272 target_write_u16(target
, MX2_NF_FCMD
, command
);
274 * start command input operation (set MX2_NF_BIT_OP_DONE==0)
276 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FCI
);
277 poll_result
= poll_for_complete_op(target
, "command");
278 if (poll_result
!= ERROR_OK
)
281 * reset cursor to begin of the buffer
283 sign_of_sequental_byte_read
= 0;
284 /* Handle special read command and adjust NF_CFG2(FDO) */
286 case NAND_CMD_READID
:
287 mx2_nf_info
->optype
= MX2_NF_DATAOUT_NANDID
;
288 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
290 case NAND_CMD_STATUS
:
291 mx2_nf_info
->optype
= MX2_NF_DATAOUT_NANDSTATUS
;
292 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
293 target_write_u16 (target
, MX2_NF_BUFADDR
, 0);
297 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
298 mx2_nf_info
->optype
= MX2_NF_DATAOUT_PAGE
;
301 /* Ohter command use the default 'One page data out' FDO */
302 mx2_nf_info
->optype
= MX2_NF_DATAOUT_PAGE
;
308 static int imx27_address(struct nand_device
*nand
, uint8_t address
)
310 struct target
*target
= nand
->target
;
311 int validate_target_result
;
314 * validate target state
316 validate_target_result
= validate_target_state(nand
);
317 if (validate_target_result
!= ERROR_OK
)
318 return validate_target_result
;
320 target_write_u16(target
, MX2_NF_FADDR
, address
);
322 * start address input operation (set MX2_NF_BIT_OP_DONE==0)
324 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FAI
);
325 poll_result
= poll_for_complete_op(target
, "address");
326 if (poll_result
!= ERROR_OK
)
332 static int imx27_nand_ready(struct nand_device
*nand
, int tout
)
334 uint16_t poll_complete_status
;
335 struct target
*target
= nand
->target
;
336 int validate_target_result
;
339 * validate target state
341 validate_target_result
= validate_target_state(nand
);
342 if (validate_target_result
!= ERROR_OK
)
343 return validate_target_result
;
346 target_read_u16(target
, MX2_NF_CFG2
, &poll_complete_status
);
347 if (poll_complete_status
& MX2_NF_BIT_OP_DONE
)
356 static int imx27_write_page(struct nand_device
*nand
, uint32_t page
,
357 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
360 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
361 struct target
*target
= nand
->target
;
363 uint16_t nand_status_content
;
364 uint16_t swap1
, swap2
, new_swap1
;
367 LOG_ERROR(data_block_size_err_msg
, data_size
);
368 return ERROR_NAND_OPERATION_FAILED
;
371 LOG_ERROR(data_block_size_err_msg
, oob_size
);
372 return ERROR_NAND_OPERATION_FAILED
;
375 LOG_ERROR("nothing to program");
376 return ERROR_NAND_OPERATION_FAILED
;
379 * validate target state
381 retval
= validate_target_state(nand
);
382 if (retval
!= ERROR_OK
)
385 in_sram_address
= MX2_NF_MAIN_BUFFER0
;
386 sign_of_sequental_byte_read
= 0;
388 retval
|= imx27_command(nand
, NAND_CMD_SEQIN
);
389 retval
|= imx27_address(nand
, 0); //col
390 retval
|= imx27_address(nand
, 0); //col
391 retval
|= imx27_address(nand
, page
& 0xff); //page address
392 retval
|= imx27_address(nand
, (page
>> 8) & 0xff); //page address
393 retval
|= imx27_address(nand
, (page
>> 16) & 0xff); //page address
395 target_write_buffer(target
, MX2_NF_MAIN_BUFFER0
, data_size
, data
);
397 if (mx2_nf_info
->flags
.hw_ecc_enabled
) {
399 * part of spare block will be overrided by hardware
402 LOG_DEBUG("part of spare block will be overrided "
403 "by hardware ECC generator");
405 target_write_buffer(target
, MX2_NF_SPARE_BUFFER0
, oob_size
,
408 //BI-swap - work-around of imx27 NFC for NAND device with page == 2kb
409 target_read_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, &swap1
);
411 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented "
413 return ERROR_NAND_OPERATION_FAILED
;
415 //target_read_u16 (target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
416 swap2
= 0xffff; //Spare buffer unused forced to 0xffff
417 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
418 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
420 target_write_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, new_swap1
);
421 target_write_u16(target
, MX2_NF_SPARE_BUFFER3
+ 4, swap2
);
423 * start data input operation (set MX2_NF_BIT_OP_DONE==0)
425 target_write_u16(target
, MX2_NF_BUFADDR
, 0);
426 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
427 poll_result
= poll_for_complete_op(target
, "data input");
428 if (poll_result
!= ERROR_OK
)
431 target_write_u16(target
, MX2_NF_BUFADDR
, 1);
432 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
433 poll_result
= poll_for_complete_op(target
, "data input");
434 if (poll_result
!= ERROR_OK
)
437 target_write_u16(target
, MX2_NF_BUFADDR
, 2);
438 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
439 poll_result
= poll_for_complete_op(target
, "data input");
440 if (poll_result
!= ERROR_OK
)
443 target_write_u16(target
, MX2_NF_BUFADDR
, 3);
444 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
445 poll_result
= poll_for_complete_op(target
, "data input");
446 if (poll_result
!= ERROR_OK
)
449 retval
|= imx27_command(nand
, NAND_CMD_PAGEPROG
);
450 if (retval
!= ERROR_OK
)
454 * check status register
457 retval
|= imx27_command(nand
, NAND_CMD_STATUS
);
458 target_write_u16 (target
, MX2_NF_BUFADDR
, 0);
459 mx2_nf_info
->optype
= MX2_NF_DATAOUT_NANDSTATUS
;
460 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
461 retval
|= do_data_output(nand
);
462 if (retval
!= ERROR_OK
) {
463 LOG_ERROR (get_status_register_err_msg
);
466 target_read_u16 (target
, MX2_NF_MAIN_BUFFER0
, &nand_status_content
);
467 if (nand_status_content
& 0x0001) {
469 * page not correctly written
471 return ERROR_NAND_OPERATION_FAILED
;
473 #ifdef _MX2_PRINT_STAT
474 LOG_INFO("%d bytes newly written", data_size
);
479 static int imx27_read_page(struct nand_device
*nand
, uint32_t page
,
480 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
483 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
484 struct target
*target
= nand
->target
;
486 uint16_t swap1
, swap2
, new_swap1
;
488 LOG_ERROR(data_block_size_err_msg
, data_size
);
489 return ERROR_NAND_OPERATION_FAILED
;
492 LOG_ERROR(data_block_size_err_msg
, oob_size
);
493 return ERROR_NAND_OPERATION_FAILED
;
497 * validate target state
499 retval
= validate_target_state(nand
);
500 if (retval
!= ERROR_OK
) {
503 /* Reset address_cycles before imx27_command ?? */
504 retval
= imx27_command(nand
, NAND_CMD_READ0
);
505 if (retval
!= ERROR_OK
) return retval
;
506 retval
= imx27_address(nand
, 0); //col
507 if (retval
!= ERROR_OK
) return retval
;
508 retval
= imx27_address(nand
, 0); //col
509 if (retval
!= ERROR_OK
) return retval
;
510 retval
= imx27_address(nand
, page
& 0xff); //page address
511 if (retval
!= ERROR_OK
) return retval
;
512 retval
= imx27_address(nand
, (page
>> 8) & 0xff); //page address
513 if (retval
!= ERROR_OK
) return retval
;
514 retval
= imx27_address(nand
, (page
>> 16) & 0xff); //page address
515 if (retval
!= ERROR_OK
) return retval
;
516 retval
= imx27_command(nand
, NAND_CMD_READSTART
);
517 if (retval
!= ERROR_OK
) return retval
;
519 target_write_u16(target
, MX2_NF_BUFADDR
, 0);
520 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
521 retval
= do_data_output(nand
);
522 if (retval
!= ERROR_OK
) {
523 LOG_ERROR("MX2_NF : Error reading page 0");
526 //Test nand page size to know how much MAIN_BUFFER must be written
527 target_write_u16(target
, MX2_NF_BUFADDR
, 1);
528 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
529 retval
= do_data_output(nand
);
530 if (retval
!= ERROR_OK
) {
531 LOG_ERROR("MX2_NF : Error reading page 1");
534 target_write_u16(target
, MX2_NF_BUFADDR
, 2);
535 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
536 retval
= do_data_output(nand
);
537 if (retval
!= ERROR_OK
) {
538 LOG_ERROR("MX2_NF : Error reading page 2");
541 target_write_u16(target
, MX2_NF_BUFADDR
, 3);
542 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
543 retval
= do_data_output(nand
);
544 if (retval
!= ERROR_OK
) {
545 LOG_ERROR("MX2_NF : Error reading page 3");
548 //BI-swap - work-around of imx27 NFC for NAND device with page == 2k
549 target_read_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, &swap1
);
550 target_read_u16(target
, MX2_NF_SPARE_BUFFER3
+ 4, &swap2
);
551 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
552 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
553 target_write_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, new_swap1
);
554 target_write_u16(target
, MX2_NF_SPARE_BUFFER3
+ 4, swap2
);
557 target_read_buffer(target
, MX2_NF_MAIN_BUFFER0
, data_size
, data
);
559 target_read_buffer(target
, MX2_NF_SPARE_BUFFER0
, oob_size
,
561 #ifdef _MX2_PRINT_STAT
563 /* When Operation Status is read (when page is erased),
564 * this function is used but data_size is null.
566 LOG_INFO("%d bytes newly read", data_size
);
572 static int initialize_nf_controller(struct nand_device
*nand
)
574 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
575 struct target
*target
= nand
->target
;
579 * resets NAND flash controller in zero time ? I dont know.
581 target_write_u16(target
, MX2_NF_CFG1
, MX2_NF_BIT_RESET_EN
);
582 work_mode
= MX2_NF_BIT_INT_DIS
; /* disable interrupt */
583 if (target
->endianness
== TARGET_BIG_ENDIAN
) {
584 LOG_DEBUG("MX2_NF : work in Big Endian mode");
585 work_mode
|= MX2_NF_BIT_BE_EN
;
587 LOG_DEBUG("MX2_NF : work in Little Endian mode");
589 if (mx2_nf_info
->flags
.hw_ecc_enabled
) {
590 LOG_DEBUG("MX2_NF : work with ECC mode");
591 work_mode
|= MX2_NF_BIT_ECC_EN
;
593 LOG_DEBUG("MX2_NF : work without ECC mode");
595 target_write_u16(target
, MX2_NF_CFG1
, work_mode
);
597 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
599 target_write_u16(target
, MX2_NF_BUFCFG
, 2);
600 target_read_u16(target
, MX2_NF_FWP
, &temp
);
601 if ((temp
& 0x0007) == 1) {
602 LOG_ERROR("NAND flash is tight-locked, reset needed");
607 * unlock NAND flash for write
609 target_write_u16(target
, MX2_NF_FWP
, 4);
610 target_write_u16(target
, MX2_NF_LOCKSTART
, 0x0000);
611 target_write_u16(target
, MX2_NF_LOCKEND
, 0xFFFF);
613 * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
615 target_write_u16(target
, MX2_NF_BUFADDR
, 0x0000);
617 * address of SRAM buffer
619 in_sram_address
= MX2_NF_MAIN_BUFFER0
;
620 sign_of_sequental_byte_read
= 0;
624 static int get_next_byte_from_sram_buffer(struct target
* target
, uint8_t * value
)
626 static uint8_t even_byte
= 0;
631 if (sign_of_sequental_byte_read
== 0)
634 if (in_sram_address
> MX2_NF_LAST_BUFFER_ADDR
) {
635 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
637 sign_of_sequental_byte_read
= 0;
639 return ERROR_NAND_OPERATION_FAILED
;
641 target_read_u16(target
, in_sram_address
, &temp
);
645 in_sram_address
+= 2;
647 *value
= temp
& 0xff;
651 sign_of_sequental_byte_read
= 1;
655 static int get_next_halfword_from_sram_buffer(struct target
* target
,
658 if (in_sram_address
> MX2_NF_LAST_BUFFER_ADDR
) {
659 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
661 return ERROR_NAND_OPERATION_FAILED
;
663 target_read_u16(target
, in_sram_address
, value
);
664 in_sram_address
+= 2;
669 static int poll_for_complete_op(struct target
* target
, const char *text
)
671 uint16_t poll_complete_status
;
672 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++) {
673 target_read_u16(target
, MX2_NF_CFG2
, &poll_complete_status
);
674 if (poll_complete_status
& MX2_NF_BIT_OP_DONE
)
679 if (!(poll_complete_status
& MX2_NF_BIT_OP_DONE
)) {
680 LOG_ERROR("%s sending timeout", text
);
681 return ERROR_NAND_OPERATION_FAILED
;
686 static int validate_target_state(struct nand_device
*nand
)
688 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
689 struct target
*target
= nand
->target
;
691 if (target
->state
!= TARGET_HALTED
) {
692 LOG_ERROR(target_not_halted_err_msg
);
693 return ERROR_NAND_OPERATION_FAILED
;
696 if (mx2_nf_info
->flags
.target_little_endian
!=
697 (target
->endianness
== TARGET_LITTLE_ENDIAN
)) {
699 * endianness changed after NAND controller probed
701 return ERROR_NAND_OPERATION_FAILED
;
706 static int do_data_output(struct nand_device
*nand
)
708 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
709 struct target
*target
= nand
->target
;
712 switch(mx2_nf_info
->fin
) {
713 case MX2_NF_FIN_DATAOUT
:
715 * start data output operation (set MX2_NF_BIT_OP_DONE==0)
717 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info
->optype
));
718 poll_result
= poll_for_complete_op(target
, "data output");
719 if (poll_result
!= ERROR_OK
)
722 mx2_nf_info
->fin
= MX2_NF_FIN_NONE
;
726 if ((mx2_nf_info
->optype
== MX2_NF_DATAOUT_PAGE
) && mx2_nf_info
->flags
.hw_ecc_enabled
) {
727 target_read_u16(target
, MX2_NF_ECCSTATUS
, &ecc_status
);
728 switch(ecc_status
& 0x000c) {
730 LOG_INFO("main area readed with 1 (correctable) error");
733 LOG_INFO("main area readed with more than 1 (incorrectable) error");
734 return ERROR_NAND_OPERATION_FAILED
;
737 switch(ecc_status
& 0x0003) {
739 LOG_INFO("spare area readed with 1 (correctable) error");
742 LOG_INFO("main area readed with more than 1 (incorrectable) error");
743 return ERROR_NAND_OPERATION_FAILED
;
748 case MX2_NF_FIN_NONE
:
754 struct nand_flash_controller imx27_nand_flash_controller
= {
756 .nand_device_command
= &imx27_nand_device_command
,
758 .reset
= &imx27_reset
,
759 .command
= &imx27_command
,
760 .address
= &imx27_address
,
761 .write_data
= &imx27_write_data
,
762 .read_data
= &imx27_read_data
,
763 .write_page
= &imx27_write_page
,
764 .read_page
= &imx27_read_page
,
765 .nand_ready
= &imx27_nand_ready
,