src/jtag/drivers/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <jtag/interface.h>
  25 #include "bitbang.h"
  26
  27 #define TDO_BIT         1
  28 #define TDI_BIT         2
  29 #define TCK_BIT         4
  30 #define TMS_BIT         8
  31 #define TRST_BIT        16
  32 #define SRST_BIT        32
  33 #define VCC_BIT         64
  34
  35 #include <sys/mman.h>
  36
  37 static uint8_t output_value = 0x0;
  38 static int dev_mem_fd;
  39 static void *gpio_controller;
  40 static volatile uint8_t *gpio_data_register;
  41 static volatile uint8_t *gpio_data_direction_register;
  42
  43 /* low level command set
  44  */
  45 static int ep93xx_read(void);
  46 static void ep93xx_write(int tck, int tms, int tdi);
  47 static void ep93xx_reset(int trst, int srst);
  48
  49 static int ep93xx_speed(int speed);
  50 static int ep93xx_init(void);
  51 static int ep93xx_quit(void);
  52
  53 struct timespec ep93xx_zzzz;
  54
  55 struct jtag_interface ep93xx_interface =
  56 {
  57         .name = "ep93xx",
  58
  59         .supported = DEBUG_CAP_TMS_SEQ,
  60         .execute_queue = bitbang_execute_queue,
  61
  62         .speed = ep93xx_speed,
  63         .init = ep93xx_init,
  64         .quit = ep93xx_quit,
  65 };
  66
  67 static struct bitbang_interface ep93xx_bitbang =
  68 {
  69         .read = ep93xx_read,
  70         .write = ep93xx_write,
  71         .reset = ep93xx_reset,
  72         .blink = 0,
  73 };
  74
  75 static int ep93xx_read(void)
  76 {
  77         return !!(*gpio_data_register & TDO_BIT);
  78 }
  79
  80 static void ep93xx_write(int tck, int tms, int tdi)
  81 {
  82         if (tck)
  83                 output_value |= TCK_BIT;
  84         else
  85                 output_value &= ~TCK_BIT;
  86
  87         if (tms)
  88                 output_value |= TMS_BIT;
  89         else
  90                 output_value &= ~TMS_BIT;
  91
  92         if (tdi)
  93                 output_value |= TDI_BIT;
  94         else
  95                 output_value &= ~TDI_BIT;
  96
  97         *gpio_data_register = output_value;
  98         nanosleep(&ep93xx_zzzz, NULL);
  99 }
 100
 101 /* (1) assert or (0) deassert reset lines */
 102 static void ep93xx_reset(int trst, int srst)
 103 {
 104         if (trst == 0)
 105                 output_value |= TRST_BIT;
 106         else if (trst == 1)
 107                 output_value &= ~TRST_BIT;
 108
 109         if (srst == 0)
 110                 output_value |= SRST_BIT;
 111         else if (srst == 1)
 112                 output_value &= ~SRST_BIT;
 113
 114         *gpio_data_register = output_value;
 115         nanosleep(&ep93xx_zzzz, NULL);
 116 }
 117
 118 static int ep93xx_speed(int speed)
 119 {
 120
 121         return ERROR_OK;
 122 }
 123
 124 static int set_gonk_mode(void)
 125 {
 126         void *syscon;
 127         uint32_t devicecfg;
 128
 129         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 130                         MAP_SHARED, dev_mem_fd, 0x80930000);
 131         if (syscon == MAP_FAILED) {
 132                 perror("mmap");
 133                 return ERROR_JTAG_INIT_FAILED;
 134         }
 135
 136         devicecfg = *((volatile int *)(syscon + 0x80));
 137         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 138         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 139
 140         munmap(syscon, 4096);
 141
 142         return ERROR_OK;
 143 }
 144
 145 static int ep93xx_init(void)
 146 {
 147         int ret;
 148
 149         bitbang_interface = &ep93xx_bitbang;
 150
 151         ep93xx_zzzz.tv_sec = 0;
 152         ep93xx_zzzz.tv_nsec = 10000000;
 153
 154         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 155         if (dev_mem_fd < 0) {
 156                 perror("open");
 157                 return ERROR_JTAG_INIT_FAILED;
 158         }
 159
 160         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 161                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 162         if (gpio_controller == MAP_FAILED) {
 163                 perror("mmap");
 164                 close(dev_mem_fd);
 165                 return ERROR_JTAG_INIT_FAILED;
 166         }
 167
 168         ret = set_gonk_mode();
 169         if (ret != ERROR_OK) {
 170                 munmap(gpio_controller, 4096);
 171                 close(dev_mem_fd);
 172                 return ret;
 173         }
 174
 175 #if 0
 176         /* Use GPIO port A.  */
 177         gpio_data_register = gpio_controller + 0x00;
 178         gpio_data_direction_register = gpio_controller + 0x10;
 179
 180
 181         /* Use GPIO port B.  */
 182         gpio_data_register = gpio_controller + 0x04;
 183         gpio_data_direction_register = gpio_controller + 0x14;
 184
 185         /* Use GPIO port C.  */
 186         gpio_data_register = gpio_controller + 0x08;
 187         gpio_data_direction_register = gpio_controller + 0x18;
 188
 189         /* Use GPIO port D.  */
 190         gpio_data_register = gpio_controller + 0x0c;
 191         gpio_data_direction_register = gpio_controller + 0x1c;
 192 #endif
 193
 194         /* Use GPIO port C.  */
 195         gpio_data_register = gpio_controller + 0x08;
 196         gpio_data_direction_register = gpio_controller + 0x18;
 197
 198         LOG_INFO("gpio_data_register      = %p", gpio_data_register);
 199         LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register);
 200         /*
 201          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 202          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 203          * TMS/TRST/SRST high.
 204          */
 205         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 206         *gpio_data_register = output_value;
 207         nanosleep(&ep93xx_zzzz, NULL);
 208
 209         /*
 210          * Configure the direction register.  1 = output, 0 = input.
 211          */
 212         *gpio_data_direction_register =
 213                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 214
 215         nanosleep(&ep93xx_zzzz, NULL);
 216         return ERROR_OK;
 217 }
 218
 219 static int ep93xx_quit(void)
 220 {
 221
 222         return ERROR_OK;
 223 }