?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
stm32: add new stm32f0 device id
[openocd.git] / src / flash / nor / stm32f1x.c
blob5ad0b62279d37d0f5578b55ef0c93b87cb627722
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 /* timeout values */
106
107 #define FLASH_WRITE_TIMEOUT 10
108 #define FLASH_ERASE_TIMEOUT 100
109
110 struct stm32x_options {
111 uint16_t RDP;
112 uint16_t user_options;
113 uint16_t user_data;
114 uint16_t protection[4];
115 };
116
117 struct stm32x_flash_bank {
118 struct stm32x_options option_bytes;
119 int ppage_size;
120 int probed;
121
122 bool has_dual_banks;
123 /* used to access dual flash bank stm32xl */
124 uint32_t register_base;
125 uint16_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
134 uint32_t offset, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = 0;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->register_base = FLASH_REG_BASE_B0;
151 stm32x_info->user_bank_size = bank->size;
152
153 return ERROR_OK;
154 }
155
156 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
157 {
158 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
159 return reg + stm32x_info->register_base;
160 }
161
162 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
163 {
164 struct target *target = bank->target;
165 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
166 }
167
168 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
169 {
170 struct target *target = bank->target;
171 uint32_t status;
172 int retval = ERROR_OK;
173
174 /* wait for busy to clear */
175 for (;;) {
176 retval = stm32x_get_flash_status(bank, &status);
177 if (retval != ERROR_OK)
178 return retval;
179 LOG_DEBUG("status: 0x%" PRIx32 "", status);
180 if ((status & FLASH_BSY) == 0)
181 break;
182 if (timeout-- <= 0) {
183 LOG_ERROR("timed out waiting for flash");
184 return ERROR_FAIL;
185 }
186 alive_sleep(1);
187 }
188
189 if (status & FLASH_WRPRTERR) {
190 LOG_ERROR("stm32x device protected");
191 retval = ERROR_FAIL;
192 }
193
194 if (status & FLASH_PGERR) {
195 LOG_ERROR("stm32x device programming failed");
196 retval = ERROR_FAIL;
197 }
198
199 /* Clear but report errors */
200 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
201 /* If this operation fails, we ignore it and report the original
202 * retval
203 */
204 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
205 FLASH_WRPRTERR | FLASH_PGERR);
206 }
207 return retval;
208 }
209
210 static int stm32x_check_operation_supported(struct flash_bank *bank)
211 {
212 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
213
214 /* if we have a dual flash bank device then
215 * we need to perform option byte stuff on bank0 only */
216 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
217 LOG_ERROR("Option Byte Operation's must use bank0");
218 return ERROR_FLASH_OPERATION_FAILED;
219 }
220
221 return ERROR_OK;
222 }
223
224 static int stm32x_read_options(struct flash_bank *bank)
225 {
226 uint32_t optiondata;
227 struct stm32x_flash_bank *stm32x_info = NULL;
228 struct target *target = bank->target;
229
230 stm32x_info = bank->driver_priv;
231
232 /* read current option bytes */
233 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
238 stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
239 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
240
241 if (optiondata & (1 << OPT_READOUT))
242 LOG_INFO("Device Security Bit Set");
243
244 /* each bit refers to a 4bank protection */
245 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
246 if (retval != ERROR_OK)
247 return retval;
248
249 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
250 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
251 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
252 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
253
254 return ERROR_OK;
255 }
256
257 static int stm32x_erase_options(struct flash_bank *bank)
258 {
259 struct stm32x_flash_bank *stm32x_info = NULL;
260 struct target *target = bank->target;
261
262 stm32x_info = bank->driver_priv;
263
264 /* read current options */
265 stm32x_read_options(bank);
266
267 /* unlock flash registers */
268 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
269 if (retval != ERROR_OK)
270 return retval;
271
272 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
273 if (retval != ERROR_OK)
274 return retval;
275
276 /* unlock option flash registers */
277 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
278 if (retval != ERROR_OK)
279 return retval;
280 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
281 if (retval != ERROR_OK)
282 return retval;
283
284 /* erase option bytes */
285 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
286 if (retval != ERROR_OK)
287 return retval;
288 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
289 if (retval != ERROR_OK)
290 return retval;
291
292 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
293 if (retval != ERROR_OK)
294 return retval;
295
296 /* clear readout protection and complementary option bytes
297 * this will also force a device unlock if set */
298 stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
299
300 return ERROR_OK;
301 }
302
303 static int stm32x_write_options(struct flash_bank *bank)
304 {
305 struct stm32x_flash_bank *stm32x_info = NULL;
306 struct target *target = bank->target;
307
308 stm32x_info = bank->driver_priv;
309
310 /* unlock flash registers */
311 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
312 if (retval != ERROR_OK)
313 return retval;
314 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
315 if (retval != ERROR_OK)
316 return retval;
317
318 /* unlock option flash registers */
319 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
320 if (retval != ERROR_OK)
321 return retval;
322 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
323 if (retval != ERROR_OK)
324 return retval;
325
326 /* program option bytes */
327 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
328 if (retval != ERROR_OK)
329 return retval;
330
331 uint8_t opt_bytes[16];
332
333 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
334 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
335 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
336 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
337 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
338 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
339 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
340 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
341
342 uint32_t offset = STM32_OB_RDP - bank->base;
343 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
344 if (retval != ERROR_OK) {
345 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
346 LOG_ERROR("working area required to erase options bytes");
347 return retval;
348 }
349
350 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
351 if (retval != ERROR_OK)
352 return retval;
353
354 return ERROR_OK;
355 }
356
357 static int stm32x_protect_check(struct flash_bank *bank)
358 {
359 struct target *target = bank->target;
360 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
361
362 uint32_t protection;
363 int i, s;
364 int num_bits;
365 int set;
366
367 if (target->state != TARGET_HALTED) {
368 LOG_ERROR("Target not halted");
369 return ERROR_TARGET_NOT_HALTED;
370 }
371
372 int retval = stm32x_check_operation_supported(bank);
373 if (ERROR_OK != retval)
374 return retval;
375
376 /* medium density - each bit refers to a 4bank protection
377 * high density - each bit refers to a 2bank protection */
378 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
379 if (retval != ERROR_OK)
380 return retval;
381
382 /* medium density - each protection bit is for 4 * 1K pages
383 * high density - each protection bit is for 2 * 2K pages */
384 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
385
386 if (stm32x_info->ppage_size == 2) {
387 /* high density flash/connectivity line protection */
388
389 set = 1;
390
391 if (protection & (1 << 31))
392 set = 0;
393
394 /* bit 31 controls sector 62 - 255 protection for high density
395 * bit 31 controls sector 62 - 127 protection for connectivity line */
396 for (s = 62; s < bank->num_sectors; s++)
397 bank->sectors[s].is_protected = set;
398
399 if (bank->num_sectors > 61)
400 num_bits = 31;
401
402 for (i = 0; i < num_bits; i++) {
403 set = 1;
404
405 if (protection & (1 << i))
406 set = 0;
407
408 for (s = 0; s < stm32x_info->ppage_size; s++)
409 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
410 }
411 } else {
412 /* low/medium density flash protection */
413 for (i = 0; i < num_bits; i++) {
414 set = 1;
415
416 if (protection & (1 << i))
417 set = 0;
418
419 for (s = 0; s < stm32x_info->ppage_size; s++)
420 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
421 }
422 }
423
424 return ERROR_OK;
425 }
426
427 static int stm32x_erase(struct flash_bank *bank, int first, int last)
428 {
429 struct target *target = bank->target;
430 int i;
431
432 if (bank->target->state != TARGET_HALTED) {
433 LOG_ERROR("Target not halted");
434 return ERROR_TARGET_NOT_HALTED;
435 }
436
437 if ((first == 0) && (last == (bank->num_sectors - 1)))
438 return stm32x_mass_erase(bank);
439
440 /* unlock flash registers */
441 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
442 if (retval != ERROR_OK)
443 return retval;
444 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
445 if (retval != ERROR_OK)
446 return retval;
447
448 for (i = first; i <= last; i++) {
449 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
453 bank->base + bank->sectors[i].offset);
454 if (retval != ERROR_OK)
455 return retval;
456 retval = target_write_u32(target,
457 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
458 if (retval != ERROR_OK)
459 return retval;
460
461 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
462 if (retval != ERROR_OK)
463 return retval;
464
465 bank->sectors[i].is_erased = 1;
466 }
467
468 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
469 if (retval != ERROR_OK)
470 return retval;
471
472 return ERROR_OK;
473 }
474
475 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
476 {
477 struct stm32x_flash_bank *stm32x_info = NULL;
478 struct target *target = bank->target;
479 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
480 int i, reg, bit;
481 int status;
482 uint32_t protection;
483
484 stm32x_info = bank->driver_priv;
485
486 if (target->state != TARGET_HALTED) {
487 LOG_ERROR("Target not halted");
488 return ERROR_TARGET_NOT_HALTED;
489 }
490
491 int retval = stm32x_check_operation_supported(bank);
492 if (ERROR_OK != retval)
493 return retval;
494
495 if ((first % stm32x_info->ppage_size) != 0) {
496 LOG_WARNING("aligned start protect sector to a %d sector boundary",
497 stm32x_info->ppage_size);
498 first = first - (first % stm32x_info->ppage_size);
499 }
500 if (((last + 1) % stm32x_info->ppage_size) != 0) {
501 LOG_WARNING("aligned end protect sector to a %d sector boundary",
502 stm32x_info->ppage_size);
503 last++;
504 last = last - (last % stm32x_info->ppage_size);
505 last--;
506 }
507
508 /* medium density - each bit refers to a 4bank protection
509 * high density - each bit refers to a 2bank protection */
510 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
511 if (retval != ERROR_OK)
512 return retval;
513
514 prot_reg[0] = (uint16_t)protection;
515 prot_reg[1] = (uint16_t)(protection >> 8);
516 prot_reg[2] = (uint16_t)(protection >> 16);
517 prot_reg[3] = (uint16_t)(protection >> 24);
518
519 if (stm32x_info->ppage_size == 2) {
520 /* high density flash */
521
522 /* bit 7 controls sector 62 - 255 protection */
523 if (last > 61) {
524 if (set)
525 prot_reg[3] &= ~(1 << 7);
526 else
527 prot_reg[3] |= (1 << 7);
528 }
529
530 if (first > 61)
531 first = 62;
532 if (last > 61)
533 last = 61;
534
535 for (i = first; i <= last; i++) {
536 reg = (i / stm32x_info->ppage_size) / 8;
537 bit = (i / stm32x_info->ppage_size) - (reg * 8);
538
539 if (set)
540 prot_reg[reg] &= ~(1 << bit);
541 else
542 prot_reg[reg] |= (1 << bit);
543 }
544 } else {
545 /* medium density flash */
546 for (i = first; i <= last; i++) {
547 reg = (i / stm32x_info->ppage_size) / 8;
548 bit = (i / stm32x_info->ppage_size) - (reg * 8);
549
550 if (set)
551 prot_reg[reg] &= ~(1 << bit);
552 else
553 prot_reg[reg] |= (1 << bit);
554 }
555 }
556
557 status = stm32x_erase_options(bank);
558 if (status != ERROR_OK)
559 return status;
560
561 stm32x_info->option_bytes.protection[0] = prot_reg[0];
562 stm32x_info->option_bytes.protection[1] = prot_reg[1];
563 stm32x_info->option_bytes.protection[2] = prot_reg[2];
564 stm32x_info->option_bytes.protection[3] = prot_reg[3];
565
566 return stm32x_write_options(bank);
567 }
568
569 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
570 uint32_t offset, uint32_t count)
571 {
572 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
573 struct target *target = bank->target;
574 uint32_t buffer_size = 16384;
575 struct working_area *write_algorithm;
576 struct working_area *source;
577 uint32_t address = bank->base + offset;
578 struct reg_param reg_params[5];
579 struct armv7m_algorithm armv7m_info;
580 int retval = ERROR_OK;
581
582 /* see contrib/loaders/flash/stm32f1x.S for src */
583
584 static const uint8_t stm32x_flash_write_code[] = {
585 /* #define STM32_FLASH_SR_OFFSET 0x0C */
586 /* wait_fifo: */
587 0x16, 0x68, /* ldr r6, [r2, #0] */
588 0x00, 0x2e, /* cmp r6, #0 */
589 0x18, 0xd0, /* beq exit */
590 0x55, 0x68, /* ldr r5, [r2, #4] */
591 0xb5, 0x42, /* cmp r5, r6 */
592 0xf9, 0xd0, /* beq wait_fifo */
593 0x2e, 0x88, /* ldrh r6, [r5, #0] */
594 0x26, 0x80, /* strh r6, [r4, #0] */
595 0x02, 0x35, /* adds r5, #2 */
596 0x02, 0x34, /* adds r4, #2 */
597 /* busy: */
598 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
599 0x01, 0x27, /* movs r7, #1 */
600 0x3e, 0x42, /* tst r6, r7 */
601 0xfb, 0xd1, /* bne busy */
602 0x14, 0x27, /* movs r7, #0x14 */
603 0x3e, 0x42, /* tst r6, r7 */
604 0x08, 0xd1, /* bne error */
605 0x9d, 0x42, /* cmp r5, r3 */
606 0x01, 0xd3, /* bcc no_wrap */
607 0x15, 0x46, /* mov r5, r2 */
608 0x08, 0x35, /* adds r5, #8 */
609 /* no_wrap: */
610 0x55, 0x60, /* str r5, [r2, #4] */
611 0x01, 0x39, /* subs r1, r1, #1 */
612 0x00, 0x29, /* cmp r1, #0 */
613 0x02, 0xd0, /* beq exit */
614 0xe5, 0xe7, /* b wait_fifo */
615 /* error: */
616 0x00, 0x20, /* movs r0, #0 */
617 0x50, 0x60, /* str r0, [r2, #4] */
618 /* exit: */
619 0x30, 0x46, /* mov r0, r6 */
620 0x00, 0xbe, /* bkpt #0 */
621 };
622
623 /* flash write code */
624 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
625 &write_algorithm) != ERROR_OK) {
626 LOG_WARNING("no working area available, can't do block memory writes");
627 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
628 };
629
630 retval = target_write_buffer(target, write_algorithm->address,
631 sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
632 if (retval != ERROR_OK)
633 return retval;
634
635 /* memory buffer */
636 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
637 buffer_size /= 2;
638 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
639 if (buffer_size <= 256) {
640 /* we already allocated the writing code, but failed to get a
641 * buffer, free the algorithm */
642 target_free_working_area(target, write_algorithm);
643
644 LOG_WARNING("no large enough working area available, can't do block memory writes");
645 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
646 }
647 };
648
649 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
650 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
651 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
652 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
653 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
654
655 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
656 buf_set_u32(reg_params[1].value, 0, 32, count);
657 buf_set_u32(reg_params[2].value, 0, 32, source->address);
658 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
659 buf_set_u32(reg_params[4].value, 0, 32, address);
660
661 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
662 armv7m_info.core_mode = ARM_MODE_THREAD;
663
664 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
665 0, NULL,
666 5, reg_params,
667 source->address, source->size,
668 write_algorithm->address, 0,
669 &armv7m_info);
670
671 if (retval == ERROR_FLASH_OPERATION_FAILED) {
672 LOG_ERROR("flash write failed at address 0x%"PRIx32,
673 buf_get_u32(reg_params[4].value, 0, 32));
674
675 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
676 LOG_ERROR("flash memory not erased before writing");
677 /* Clear but report errors */
678 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
679 }
680
681 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
682 LOG_ERROR("flash memory write protected");
683 /* Clear but report errors */
684 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
685 }
686 }
687
688 target_free_working_area(target, source);
689 target_free_working_area(target, write_algorithm);
690
691 destroy_reg_param(&reg_params[0]);
692 destroy_reg_param(&reg_params[1]);
693 destroy_reg_param(&reg_params[2]);
694 destroy_reg_param(&reg_params[3]);
695 destroy_reg_param(&reg_params[4]);
696
697 return retval;
698 }
699
700 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
701 uint32_t offset, uint32_t count)
702 {
703 struct target *target = bank->target;
704 uint8_t *new_buffer = NULL;
705
706 if (bank->target->state != TARGET_HALTED) {
707 LOG_ERROR("Target not halted");
708 return ERROR_TARGET_NOT_HALTED;
709 }
710
711 if (offset & 0x1) {
712 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
713 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
714 }
715
716 /* If there's an odd number of bytes, the data has to be padded. Duplicate
717 * the buffer and use the normal code path with a single block write since
718 * it's probably cheaper than to special case the last odd write using
719 * discrete accesses. */
720 if (count & 1) {
721 new_buffer = malloc(count + 1);
722 if (new_buffer == NULL) {
723 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
724 return ERROR_FAIL;
725 }
726 LOG_INFO("odd number of bytes to write, padding with 0xff");
727 buffer = memcpy(new_buffer, buffer, count);
728 buffer[count++] = 0xff;
729 }
730
731 uint32_t words_remaining = count / 2;
732 int retval, retval2;
733
734 /* unlock flash registers */
735 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
736 if (retval != ERROR_OK)
737 goto cleanup;
738 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
739 if (retval != ERROR_OK)
740 goto cleanup;
741
742 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
743 if (retval != ERROR_OK)
744 goto cleanup;
745
746 /* try using a block write */
747 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
748
749 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
750 /* if block write failed (no sufficient working area),
751 * we use normal (slow) single halfword accesses */
752 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
753
754 while (words_remaining > 0) {
755 uint16_t value;
756 memcpy(&value, buffer, sizeof(uint16_t));
757
758 retval = target_write_u16(target, bank->base + offset, value);
759 if (retval != ERROR_OK)
760 goto reset_pg_and_lock;
761
762 retval = stm32x_wait_status_busy(bank, 5);
763 if (retval != ERROR_OK)
764 goto reset_pg_and_lock;
765
766 words_remaining--;
767 buffer += 2;
768 offset += 2;
769 }
770 }
771
772 reset_pg_and_lock:
773 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
774 if (retval == ERROR_OK)
775 retval = retval2;
776
777 cleanup:
778 if (new_buffer)
779 free(new_buffer);
780
781 return retval;
782 }
783
784 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
785 {
786 /* This check the device CPUID core register to detect
787 * the M0 from the M3 devices. */
788
789 struct target *target = bank->target;
790 uint32_t cpuid, device_id_register = 0;
791
792 /* Get the CPUID from the ARM Core
793 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
794 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
795 if (retval != ERROR_OK)
796 return retval;
797
798 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
799 /* 0xC20 is M0 devices */
800 device_id_register = 0x40015800;
801 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
802 /* 0xC23 is M3 devices */
803 device_id_register = 0xE0042000;
804 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
805 /* 0xC24 is M4 devices */
806 device_id_register = 0xE0042000;
807 } else {
808 LOG_ERROR("Cannot identify target as a stm32x");
809 return ERROR_FAIL;
810 }
811
812 /* read stm32 device id register */
813 retval = target_read_u32(target, device_id_register, device_id);
814 if (retval != ERROR_OK)
815 return retval;
816
817 return retval;
818 }
819
820 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
821 {
822 struct target *target = bank->target;
823 uint32_t cpuid, flash_size_reg;
824
825 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
826 if (retval != ERROR_OK)
827 return retval;
828
829 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
830 /* 0xC20 is M0 devices */
831 flash_size_reg = 0x1FFFF7CC;
832 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
833 /* 0xC23 is M3 devices */
834 flash_size_reg = 0x1FFFF7E0;
835 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
836 /* 0xC24 is M4 devices */
837 flash_size_reg = 0x1FFFF7CC;
838 } else {
839 LOG_ERROR("Cannot identify target as a stm32x");
840 return ERROR_FAIL;
841 }
842
843 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
844 if (retval != ERROR_OK)
845 return retval;
846
847 return retval;
848 }
849
850 static int stm32x_probe(struct flash_bank *bank)
851 {
852 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
853 int i;
854 uint16_t flash_size_in_kb;
855 uint16_t max_flash_size_in_kb;
856 uint32_t device_id;
857 int page_size;
858 uint32_t base_address = 0x08000000;
859
860 stm32x_info->probed = 0;
861 stm32x_info->register_base = FLASH_REG_BASE_B0;
862 stm32x_info->user_data_offset = 10;
863 stm32x_info->option_offset = 0;
864
865 /* default factory protection level */
866 stm32x_info->default_rdp = 0x5AA5;
867
868 /* read stm32 device id register */
869 int retval = stm32x_get_device_id(bank, &device_id);
870 if (retval != ERROR_OK)
871 return retval;
872
873 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
874
875 /* set page size, protection granularity and max flash size depending on family */
876 switch (device_id & 0xfff) {
877 case 0x410: /* medium density */
878 page_size = 1024;
879 stm32x_info->ppage_size = 4;
880 max_flash_size_in_kb = 128;
881 break;
882 case 0x412: /* low density */
883 page_size = 1024;
884 stm32x_info->ppage_size = 4;
885 max_flash_size_in_kb = 32;
886 break;
887 case 0x414: /* high density */
888 page_size = 2048;
889 stm32x_info->ppage_size = 2;
890 max_flash_size_in_kb = 512;
891 break;
892 case 0x418: /* connectivity line density */
893 page_size = 2048;
894 stm32x_info->ppage_size = 2;
895 max_flash_size_in_kb = 256;
896 break;
897 case 0x420: /* value line density */
898 page_size = 1024;
899 stm32x_info->ppage_size = 4;
900 max_flash_size_in_kb = 128;
901 break;
902 case 0x422: /* stm32f30x */
903 page_size = 2048;
904 stm32x_info->ppage_size = 2;
905 max_flash_size_in_kb = 256;
906 stm32x_info->user_data_offset = 16;
907 stm32x_info->option_offset = 6;
908 stm32x_info->default_rdp = 0x55AA;
909 break;
910 case 0x428: /* value line High density */
911 page_size = 2048;
912 stm32x_info->ppage_size = 4;
913 max_flash_size_in_kb = 128;
914 break;
915 case 0x430: /* xl line density (dual flash banks) */
916 page_size = 2048;
917 stm32x_info->ppage_size = 2;
918 max_flash_size_in_kb = 1024;
919 stm32x_info->has_dual_banks = true;
920 break;
921 case 0x432: /* stm32f37x */
922 page_size = 2048;
923 stm32x_info->ppage_size = 2;
924 max_flash_size_in_kb = 256;
925 stm32x_info->user_data_offset = 16;
926 stm32x_info->option_offset = 6;
927 stm32x_info->default_rdp = 0x55AA;
928 break;
929 case 0x440: /* stm32f0x */
930 case 0x444:
931 page_size = 1024;
932 stm32x_info->ppage_size = 4;
933 max_flash_size_in_kb = 64;
934 stm32x_info->user_data_offset = 16;
935 stm32x_info->option_offset = 6;
936 stm32x_info->default_rdp = 0x55AA;
937 break;
938 default:
939 LOG_WARNING("Cannot identify target as a STM32 family.");
940 return ERROR_FAIL;
941 }
942
943 /* get flash size from target. */
944 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
945
946 /* failed reading flash size or flash size invalid (early silicon),
947 * default to max target family */
948 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
949 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
950 max_flash_size_in_kb);
951 flash_size_in_kb = max_flash_size_in_kb;
952 }
953
954 if (stm32x_info->has_dual_banks) {
955 /* split reported size into matching bank */
956 if (bank->base != 0x08080000) {
957 /* bank 0 will be fixed 512k */
958 flash_size_in_kb = 512;
959 } else {
960 flash_size_in_kb -= 512;
961 /* bank1 also uses a register offset */
962 stm32x_info->register_base = FLASH_REG_BASE_B1;
963 base_address = 0x08080000;
964 }
965 }
966
967 /* if the user sets the size manually then ignore the probed value
968 * this allows us to work around devices that have a invalid flash size register value */
969 if (stm32x_info->user_bank_size) {
970 LOG_INFO("ignoring flash probed value, using configured bank size");
971 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
972 }
973
974 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
975
976 /* did we assign flash size? */
977 assert(flash_size_in_kb != 0xffff);
978
979 /* calculate numbers of pages */
980 int num_pages = flash_size_in_kb * 1024 / page_size;
981
982 /* check that calculation result makes sense */
983 assert(num_pages > 0);
984
985 if (bank->sectors) {
986 free(bank->sectors);
987 bank->sectors = NULL;
988 }
989
990 bank->base = base_address;
991 bank->size = (num_pages * page_size);
992 bank->num_sectors = num_pages;
993 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
994
995 for (i = 0; i < num_pages; i++) {
996 bank->sectors[i].offset = i * page_size;
997 bank->sectors[i].size = page_size;
998 bank->sectors[i].is_erased = -1;
999 bank->sectors[i].is_protected = 1;
1000 }
1001
1002 stm32x_info->probed = 1;
1003
1004 return ERROR_OK;
1005 }
1006
1007 static int stm32x_auto_probe(struct flash_bank *bank)
1008 {
1009 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1010 if (stm32x_info->probed)
1011 return ERROR_OK;
1012 return stm32x_probe(bank);
1013 }
1014
1015 #if 0
1016 COMMAND_HANDLER(stm32x_handle_part_id_command)
1017 {
1018 return ERROR_OK;
1019 }
1020 #endif
1021
1022 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1023 {
1024 uint32_t device_id;
1025 int printed;
1026
1027 /* read stm32 device id register */
1028 int retval = stm32x_get_device_id(bank, &device_id);
1029 if (retval != ERROR_OK)
1030 return retval;
1031
1032 if ((device_id & 0xfff) == 0x410) {
1033 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1034 buf += printed;
1035 buf_size -= printed;
1036
1037 switch (device_id >> 16) {
1038 case 0x0000:
1039 snprintf(buf, buf_size, "A");
1040 break;
1041
1042 case 0x2000:
1043 snprintf(buf, buf_size, "B");
1044 break;
1045
1046 case 0x2001:
1047 snprintf(buf, buf_size, "Z");
1048 break;
1049
1050 case 0x2003:
1051 snprintf(buf, buf_size, "Y");
1052 break;
1053
1054 default:
1055 snprintf(buf, buf_size, "unknown");
1056 break;
1057 }
1058 } else if ((device_id & 0xfff) == 0x412) {
1059 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1060 buf += printed;
1061 buf_size -= printed;
1062
1063 switch (device_id >> 16) {
1064 case 0x1000:
1065 snprintf(buf, buf_size, "A");
1066 break;
1067
1068 default:
1069 snprintf(buf, buf_size, "unknown");
1070 break;
1071 }
1072 } else if ((device_id & 0xfff) == 0x414) {
1073 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1074 buf += printed;
1075 buf_size -= printed;
1076
1077 switch (device_id >> 16) {
1078 case 0x1000:
1079 snprintf(buf, buf_size, "A");
1080 break;
1081
1082 case 0x1001:
1083 snprintf(buf, buf_size, "Z");
1084 break;
1085
1086 default:
1087 snprintf(buf, buf_size, "unknown");
1088 break;
1089 }
1090 } else if ((device_id & 0xfff) == 0x418) {
1091 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1092 buf += printed;
1093 buf_size -= printed;
1094
1095 switch (device_id >> 16) {
1096 case 0x1000:
1097 snprintf(buf, buf_size, "A");
1098 break;
1099
1100 case 0x1001:
1101 snprintf(buf, buf_size, "Z");
1102 break;
1103
1104 default:
1105 snprintf(buf, buf_size, "unknown");
1106 break;
1107 }
1108 } else if ((device_id & 0xfff) == 0x420) {
1109 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1110 buf += printed;
1111 buf_size -= printed;
1112
1113 switch (device_id >> 16) {
1114 case 0x1000:
1115 snprintf(buf, buf_size, "A");
1116 break;
1117
1118 case 0x1001:
1119 snprintf(buf, buf_size, "Z");
1120 break;
1121
1122 default:
1123 snprintf(buf, buf_size, "unknown");
1124 break;
1125 }
1126 } else if ((device_id & 0xfff) == 0x422) {
1127 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1128 buf += printed;
1129 buf_size -= printed;
1130
1131 switch (device_id >> 16) {
1132 case 0x1000:
1133 snprintf(buf, buf_size, "A");
1134 break;
1135
1136 case 0x1001:
1137 snprintf(buf, buf_size, "Z");
1138 break;
1139
1140 case 0x2000:
1141 snprintf(buf, buf_size, "B");
1142 break;
1143
1144 default:
1145 snprintf(buf, buf_size, "unknown");
1146 break;
1147 }
1148 } else if ((device_id & 0xfff) == 0x428) {
1149 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1150 buf += printed;
1151 buf_size -= printed;
1152
1153 switch (device_id >> 16) {
1154 case 0x1000:
1155 snprintf(buf, buf_size, "A");
1156 break;
1157
1158 case 0x1001:
1159 snprintf(buf, buf_size, "Z");
1160 break;
1161
1162 default:
1163 snprintf(buf, buf_size, "unknown");
1164 break;
1165 }
1166 } else if ((device_id & 0xfff) == 0x430) {
1167 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1168 buf += printed;
1169 buf_size -= printed;
1170
1171 switch (device_id >> 16) {
1172 case 0x1000:
1173 snprintf(buf, buf_size, "A");
1174 break;
1175
1176 default:
1177 snprintf(buf, buf_size, "unknown");
1178 break;
1179 }
1180 } else if ((device_id & 0xfff) == 0x432) {
1181 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1182 buf += printed;
1183 buf_size -= printed;
1184
1185 switch (device_id >> 16) {
1186 case 0x1000:
1187 snprintf(buf, buf_size, "A");
1188 break;
1189
1190 case 0x2000:
1191 snprintf(buf, buf_size, "B");
1192 break;
1193
1194 default:
1195 snprintf(buf, buf_size, "unknown");
1196 break;
1197 }
1198 } else if (((device_id & 0xfff) == 0x440) ||
1199 ((device_id & 0xfff) == 0x444)) {
1200 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1201 buf += printed;
1202 buf_size -= printed;
1203
1204 switch (device_id >> 16) {
1205 case 0x1000:
1206 snprintf(buf, buf_size, "1.0");
1207 break;
1208
1209 case 0x2000:
1210 snprintf(buf, buf_size, "2.0");
1211 break;
1212
1213 default:
1214 snprintf(buf, buf_size, "unknown");
1215 break;
1216 }
1217 } else {
1218 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1219 return ERROR_FAIL;
1220 }
1221
1222 return ERROR_OK;
1223 }
1224
1225 COMMAND_HANDLER(stm32x_handle_lock_command)
1226 {
1227 struct target *target = NULL;
1228 struct stm32x_flash_bank *stm32x_info = NULL;
1229
1230 if (CMD_ARGC < 1)
1231 return ERROR_COMMAND_SYNTAX_ERROR;
1232
1233 struct flash_bank *bank;
1234 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1235 if (ERROR_OK != retval)
1236 return retval;
1237
1238 stm32x_info = bank->driver_priv;
1239
1240 target = bank->target;
1241
1242 if (target->state != TARGET_HALTED) {
1243 LOG_ERROR("Target not halted");
1244 return ERROR_TARGET_NOT_HALTED;
1245 }
1246
1247 retval = stm32x_check_operation_supported(bank);
1248 if (ERROR_OK != retval)
1249 return retval;
1250
1251 if (stm32x_erase_options(bank) != ERROR_OK) {
1252 command_print(CMD_CTX, "stm32x failed to erase options");
1253 return ERROR_OK;
1254 }
1255
1256 /* set readout protection */
1257 stm32x_info->option_bytes.RDP = 0;
1258
1259 if (stm32x_write_options(bank) != ERROR_OK) {
1260 command_print(CMD_CTX, "stm32x failed to lock device");
1261 return ERROR_OK;
1262 }
1263
1264 command_print(CMD_CTX, "stm32x locked");
1265
1266 return ERROR_OK;
1267 }
1268
1269 COMMAND_HANDLER(stm32x_handle_unlock_command)
1270 {
1271 struct target *target = NULL;
1272
1273 if (CMD_ARGC < 1)
1274 return ERROR_COMMAND_SYNTAX_ERROR;
1275
1276 struct flash_bank *bank;
1277 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1278 if (ERROR_OK != retval)
1279 return retval;
1280
1281 target = bank->target;
1282
1283 if (target->state != TARGET_HALTED) {
1284 LOG_ERROR("Target not halted");
1285 return ERROR_TARGET_NOT_HALTED;
1286 }
1287
1288 retval = stm32x_check_operation_supported(bank);
1289 if (ERROR_OK != retval)
1290 return retval;
1291
1292 if (stm32x_erase_options(bank) != ERROR_OK) {
1293 command_print(CMD_CTX, "stm32x failed to unlock device");
1294 return ERROR_OK;
1295 }
1296
1297 if (stm32x_write_options(bank) != ERROR_OK) {
1298 command_print(CMD_CTX, "stm32x failed to lock device");
1299 return ERROR_OK;
1300 }
1301
1302 command_print(CMD_CTX, "stm32x unlocked.\n"
1303 "INFO: a reset or power cycle is required "
1304 "for the new settings to take effect.");
1305
1306 return ERROR_OK;
1307 }
1308
1309 COMMAND_HANDLER(stm32x_handle_options_read_command)
1310 {
1311 uint32_t optionbyte;
1312 struct target *target = NULL;
1313 struct stm32x_flash_bank *stm32x_info = NULL;
1314
1315 if (CMD_ARGC < 1)
1316 return ERROR_COMMAND_SYNTAX_ERROR;
1317
1318 struct flash_bank *bank;
1319 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1320 if (ERROR_OK != retval)
1321 return retval;
1322
1323 stm32x_info = bank->driver_priv;
1324
1325 target = bank->target;
1326
1327 if (target->state != TARGET_HALTED) {
1328 LOG_ERROR("Target not halted");
1329 return ERROR_TARGET_NOT_HALTED;
1330 }
1331
1332 retval = stm32x_check_operation_supported(bank);
1333 if (ERROR_OK != retval)
1334 return retval;
1335
1336 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1337 if (retval != ERROR_OK)
1338 return retval;
1339 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1340
1341 int user_data = optionbyte;
1342
1343 if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1344 command_print(CMD_CTX, "Option Byte Complement Error");
1345
1346 if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1347 command_print(CMD_CTX, "Readout Protection On");
1348 else
1349 command_print(CMD_CTX, "Readout Protection Off");
1350
1351 /* user option bytes are offset depending on variant */
1352 optionbyte >>= stm32x_info->option_offset;
1353
1354 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1355 command_print(CMD_CTX, "Software Watchdog");
1356 else
1357 command_print(CMD_CTX, "Hardware Watchdog");
1358
1359 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1360 command_print(CMD_CTX, "Stop: No reset generated");
1361 else
1362 command_print(CMD_CTX, "Stop: Reset generated");
1363
1364 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1365 command_print(CMD_CTX, "Standby: No reset generated");
1366 else
1367 command_print(CMD_CTX, "Standby: Reset generated");
1368
1369 if (stm32x_info->has_dual_banks) {
1370 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1371 command_print(CMD_CTX, "Boot: Bank 0");
1372 else
1373 command_print(CMD_CTX, "Boot: Bank 1");
1374 }
1375
1376 command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1377 (user_data >> stm32x_info->user_data_offset) & 0xff);
1378 command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1379 (user_data >> (stm32x_info->user_data_offset + 8)) & 0xff);
1380
1381 return ERROR_OK;
1382 }
1383
1384 COMMAND_HANDLER(stm32x_handle_options_write_command)
1385 {
1386 struct target *target = NULL;
1387 struct stm32x_flash_bank *stm32x_info = NULL;
1388 uint16_t optionbyte;
1389
1390 if (CMD_ARGC < 2)
1391 return ERROR_COMMAND_SYNTAX_ERROR;
1392
1393 struct flash_bank *bank;
1394 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1395 if (ERROR_OK != retval)
1396 return retval;
1397
1398 stm32x_info = bank->driver_priv;
1399
1400 target = bank->target;
1401
1402 if (target->state != TARGET_HALTED) {
1403 LOG_ERROR("Target not halted");
1404 return ERROR_TARGET_NOT_HALTED;
1405 }
1406
1407 retval = stm32x_check_operation_supported(bank);
1408 if (ERROR_OK != retval)
1409 return retval;
1410
1411 retval = stm32x_read_options(bank);
1412 if (ERROR_OK != retval)
1413 return retval;
1414
1415 /* start with current options */
1416 optionbyte = stm32x_info->option_bytes.user_options;
1417
1418 /* skip over flash bank */
1419 CMD_ARGC--;
1420 CMD_ARGV++;
1421
1422 while (CMD_ARGC) {
1423 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1424 optionbyte |= (1 << 0);
1425 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1426 optionbyte &= ~(1 << 0);
1427 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1428 optionbyte &= ~(1 << 1);
1429 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1430 optionbyte &= ~(1 << 1);
1431 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1432 optionbyte &= ~(1 << 2);
1433 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1434 optionbyte &= ~(1 << 2);
1435 else if (stm32x_info->has_dual_banks) {
1436 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1437 optionbyte |= (1 << 3);
1438 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1439 optionbyte &= ~(1 << 3);
1440 else
1441 return ERROR_COMMAND_SYNTAX_ERROR;
1442 } else
1443 return ERROR_COMMAND_SYNTAX_ERROR;
1444 CMD_ARGC--;
1445 CMD_ARGV++;
1446 }
1447
1448 if (stm32x_erase_options(bank) != ERROR_OK) {
1449 command_print(CMD_CTX, "stm32x failed to erase options");
1450 return ERROR_OK;
1451 }
1452
1453 stm32x_info->option_bytes.user_options = optionbyte;
1454
1455 if (stm32x_write_options(bank) != ERROR_OK) {
1456 command_print(CMD_CTX, "stm32x failed to write options");
1457 return ERROR_OK;
1458 }
1459
1460 command_print(CMD_CTX, "stm32x write options complete.\n"
1461 "INFO: a reset or power cycle is required "
1462 "for the new settings to take effect.");
1463
1464 return ERROR_OK;
1465 }
1466
1467 static int stm32x_mass_erase(struct flash_bank *bank)
1468 {
1469 struct target *target = bank->target;
1470
1471 if (target->state != TARGET_HALTED) {
1472 LOG_ERROR("Target not halted");
1473 return ERROR_TARGET_NOT_HALTED;
1474 }
1475
1476 /* unlock option flash registers */
1477 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1478 if (retval != ERROR_OK)
1479 return retval;
1480 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1481 if (retval != ERROR_OK)
1482 return retval;
1483
1484 /* mass erase flash memory */
1485 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1486 if (retval != ERROR_OK)
1487 return retval;
1488 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1489 FLASH_MER | FLASH_STRT);
1490 if (retval != ERROR_OK)
1491 return retval;
1492
1493 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1494 if (retval != ERROR_OK)
1495 return retval;
1496
1497 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1498 if (retval != ERROR_OK)
1499 return retval;
1500
1501 return ERROR_OK;
1502 }
1503
1504 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1505 {
1506 int i;
1507
1508 if (CMD_ARGC < 1)
1509 return ERROR_COMMAND_SYNTAX_ERROR;
1510
1511 struct flash_bank *bank;
1512 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1513 if (ERROR_OK != retval)
1514 return retval;
1515
1516 retval = stm32x_mass_erase(bank);
1517 if (retval == ERROR_OK) {
1518 /* set all sectors as erased */
1519 for (i = 0; i < bank->num_sectors; i++)
1520 bank->sectors[i].is_erased = 1;
1521
1522 command_print(CMD_CTX, "stm32x mass erase complete");
1523 } else
1524 command_print(CMD_CTX, "stm32x mass erase failed");
1525
1526 return retval;
1527 }
1528
1529 static const struct command_registration stm32x_exec_command_handlers[] = {
1530 {
1531 .name = "lock",
1532 .handler = stm32x_handle_lock_command,
1533 .mode = COMMAND_EXEC,
1534 .usage = "bank_id",
1535 .help = "Lock entire flash device.",
1536 },
1537 {
1538 .name = "unlock",
1539 .handler = stm32x_handle_unlock_command,
1540 .mode = COMMAND_EXEC,
1541 .usage = "bank_id",
1542 .help = "Unlock entire protected flash device.",
1543 },
1544 {
1545 .name = "mass_erase",
1546 .handler = stm32x_handle_mass_erase_command,
1547 .mode = COMMAND_EXEC,
1548 .usage = "bank_id",
1549 .help = "Erase entire flash device.",
1550 },
1551 {
1552 .name = "options_read",
1553 .handler = stm32x_handle_options_read_command,
1554 .mode = COMMAND_EXEC,
1555 .usage = "bank_id",
1556 .help = "Read and display device option byte.",
1557 },
1558 {
1559 .name = "options_write",
1560 .handler = stm32x_handle_options_write_command,
1561 .mode = COMMAND_EXEC,
1562 .usage = "bank_id ('SWWDG'|'HWWDG') "
1563 "('RSTSTNDBY'|'NORSTSTNDBY') "
1564 "('RSTSTOP'|'NORSTSTOP')",
1565 .help = "Replace bits in device option byte.",
1566 },
1567 COMMAND_REGISTRATION_DONE
1568 };
1569
1570 static const struct command_registration stm32x_command_handlers[] = {
1571 {
1572 .name = "stm32f1x",
1573 .mode = COMMAND_ANY,
1574 .help = "stm32f1x flash command group",
1575 .usage = "",
1576 .chain = stm32x_exec_command_handlers,
1577 },
1578 COMMAND_REGISTRATION_DONE
1579 };
1580
1581 struct flash_driver stm32f1x_flash = {
1582 .name = "stm32f1x",
1583 .commands = stm32x_command_handlers,
1584 .flash_bank_command = stm32x_flash_bank_command,
1585 .erase = stm32x_erase,
1586 .protect = stm32x_protect,
1587 .write = stm32x_write,
1588 .read = default_flash_read,
1589 .probe = stm32x_probe,
1590 .auto_probe = stm32x_auto_probe,
1591 .erase_check = default_flash_blank_check,
1592 .protect_check = stm32x_protect_check,
1593 .info = get_stm32x_info,
1594 };
Official OpenOCD Mirror