src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the
  23  * Free Software Foundation, Inc.,
  24  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25  */
  26 #ifndef ARM_H
  27 #define ARM_H
  28
  29 #include <helper/command.h>
  30 #include "target.h"
  31
  32
  33 /**
  34  * @file
  35  * Holds the interface to ARM cores.
  36  *
  37  * At this writing, only "classic ARM" cores built on the ARMv4 register
  38  * and mode model are supported.  The Thumb2-only microcontroller profile
  39  * support has not yet been integrated, affecting Cortex-M parts.
  40  */
  41
  42 /**
  43  * These numbers match the five low bits of the *PSR registers on
  44  * "classic ARM" processors, which build on the ARMv4 processor
  45  * modes and register set.
  46  */
  47 enum arm_mode {
  48         ARM_MODE_USR = 16,
  49         ARM_MODE_FIQ = 17,
  50         ARM_MODE_IRQ = 18,
  51         ARM_MODE_SVC = 19,
  52         ARM_MODE_ABT = 23,
  53         ARM_MODE_MON = 26,
  54         ARM_MODE_UND = 27,
  55         ARM_MODE_SYS = 31,
  56         ARM_MODE_ANY = -1
  57 };
  58
  59 const char *arm_mode_name(unsigned psr_mode);
  60 bool is_arm_mode(unsigned psr_mode);
  61
  62 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  63 enum arm_state {
  64         ARM_STATE_ARM,
  65         ARM_STATE_THUMB,
  66         ARM_STATE_JAZELLE,
  67         ARM_STATE_THUMB_EE,
  68 };
  69
  70 extern const char *arm_state_strings[];
  71
  72 #define ARM_COMMON_MAGIC 0x0A450A45
  73
  74 /**
  75  * Represents a generic ARM core, with standard application registers.
  76  *
  77  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  78  * Cortex-M series cores do not support as many core states or shadowed
  79  * registers as traditional ARM cores, and only support Thumb2 instructions.
  80  */
  81 struct arm {
  82         int common_magic;
  83         struct reg_cache *core_cache;
  84
  85         /** Handle to the CPSR; valid in all core modes. */
  86         struct reg *cpsr;
  87
  88         /** Handle to the SPSR; valid only in core modes with an SPSR. */
  89         struct reg *spsr;
  90
  91         /** Support for arm_reg_current() */
  92         const int *map;
  93
  94         /**
  95          * Indicates what registers are in the ARM state core register set.
  96          * ARM_MODE_ANY indicates the standard set of 37 registers,
  97          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
  98          * more registers are shadowed, for "Secure Monitor" mode.
  99          */
 100         enum arm_mode core_type;
 101
 102         /** Record the current core mode: SVC, USR, or some other mode. */
 103         enum arm_mode core_mode;
 104
 105         /** Record the current core state: ARM, Thumb, or otherwise. */
 106         enum arm_state core_state;
 107
 108         /** Flag reporting unavailability of the BKPT instruction. */
 109         bool is_armv4;
 110
 111         /** Flag reporting whether semihosting is active. */
 112         bool is_semihosting;
 113
 114         /** Value to be returned by semihosting SYS_ERRNO request. */
 115         int semihosting_errno;
 116
 117         /** Backpointer to the target. */
 118         struct target *target;
 119
 120         /** Handle for the debug module, if one is present. */
 121         struct arm_dpm *dpm;
 122
 123         /** Handle for the Embedded Trace Module, if one is present. */
 124         struct etm_context *etm;
 125
 126         /* FIXME all these methods should take "struct arm *" not target */
 127
 128         /** Retrieve all core registers, for display. */
 129         int (*full_context)(struct target *target);
 130
 131         /** Retrieve a single core register. */
 132         int (*read_core_reg)(struct target *target, struct reg *reg,
 133                         int num, enum arm_mode mode);
 134         int (*write_core_reg)(struct target *target, struct reg *reg,
 135                         int num, enum arm_mode mode, uint32_t value);
 136
 137         /** Read coprocessor register.  */
 138         int (*mrc)(struct target *target, int cpnum,
 139                         uint32_t op1, uint32_t op2,
 140                         uint32_t CRn, uint32_t CRm,
 141                         uint32_t *value);
 142
 143         /** Write coprocessor register.  */
 144         int (*mcr)(struct target *target, int cpnum,
 145                         uint32_t op1, uint32_t op2,
 146                         uint32_t CRn, uint32_t CRm,
 147                         uint32_t value);
 148
 149         void *arch_info;
 150 };
 151
 152 /** Convert target handle to generic ARM target state handle. */
 153 static inline struct arm *target_to_arm(struct target *target)
 154 {
 155         return target->arch_info;
 156 }
 157
 158 static inline bool is_arm(struct arm *arm)
 159 {
 160         return arm && arm->common_magic == ARM_COMMON_MAGIC;
 161 }
 162
 163 struct arm_algorithm {
 164         int common_magic;
 165
 166         enum arm_mode core_mode;
 167         enum arm_state core_state;
 168 };
 169
 170 struct arm_reg {
 171         int num;
 172         enum arm_mode mode;
 173         struct target *target;
 174         struct arm *armv4_5_common;
 175         uint32_t value;
 176 };
 177
 178 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 179
 180 extern const struct command_registration arm_command_handlers[];
 181
 182 int arm_arch_state(struct target *target);
 183 int arm_get_gdb_reg_list(struct target *target,
 184                 struct reg **reg_list[], int *reg_list_size);
 185
 186 int arm_init_arch_info(struct target *target, struct arm *arm);
 187
 188 /* REVISIT rename this once it's usable by ARMv7-M */
 189 int armv4_5_run_algorithm(struct target *target,
 190                 int num_mem_params, struct mem_param *mem_params,
 191                 int num_reg_params, struct reg_param *reg_params,
 192                 uint32_t entry_point, uint32_t exit_point,
 193                 int timeout_ms, void *arch_info);
 194 int armv4_5_run_algorithm_inner(struct target *target,
 195                 int num_mem_params, struct mem_param *mem_params,
 196                 int num_reg_params, struct reg_param *reg_params,
 197                 uint32_t entry_point, uint32_t exit_point,
 198                 int timeout_ms, void *arch_info,
 199                 int (*run_it)(struct target *target, uint32_t exit_point,
 200                                 int timeout_ms, void *arch_info));
 201
 202 int arm_checksum_memory(struct target *target,
 203                 uint32_t address, uint32_t count, uint32_t *checksum);
 204 int arm_blank_check_memory(struct target *target,
 205                 uint32_t address, uint32_t count, uint32_t *blank);
 206
 207 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 208 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 209
 210 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
 211
 212 extern struct reg arm_gdb_dummy_fp_reg;
 213 extern struct reg arm_gdb_dummy_fps_reg;
 214
 215 #endif /* ARM_H */