1 /***************************************************************************
2 * Copyright (C) 2008 by John McCarthy *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by David T.L. Wong *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ***************************************************************************/
30 #include "mips32_dmaacc.h"
32 static int mips32_dmaacc_read_mem8(struct mips_ejtag
*ejtag_info
,
33 uint32_t addr
, int count
, uint8_t *buf
);
34 static int mips32_dmaacc_read_mem16(struct mips_ejtag
*ejtag_info
,
35 uint32_t addr
, int count
, uint16_t *buf
);
36 static int mips32_dmaacc_read_mem32(struct mips_ejtag
*ejtag_info
,
37 uint32_t addr
, int count
, uint32_t *buf
);
39 static int mips32_dmaacc_write_mem8(struct mips_ejtag
*ejtag_info
,
40 uint32_t addr
, int count
, uint8_t *buf
);
41 static int mips32_dmaacc_write_mem16(struct mips_ejtag
*ejtag_info
,
42 uint32_t addr
, int count
, uint16_t *buf
);
43 static int mips32_dmaacc_write_mem32(struct mips_ejtag
*ejtag_info
,
44 uint32_t addr
, int count
, uint32_t *buf
);
47 * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
48 * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
49 * (and any others that support EJTAG DMA transfers).
50 * Note: This only supports memory read/write. Since the BCM5352 doesn't
51 * appear to support PRACC accesses, all debug functions except halt
52 * do not work. Still, this does allow erasing/writing flash as well as
53 * displaying/modifying memory and memory mapped registers.
56 static void ejtag_dma_dstrt_poll(struct mips_ejtag
*ejtag_info
)
60 ejtag_ctrl
= EJTAG_CTRL_DMAACC
| ejtag_info
->ejtag_ctrl
;
61 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
62 } while (ejtag_ctrl
& EJTAG_CTRL_DSTRT
);
65 static int ejtag_dma_read(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint32_t *data
)
69 int retries
= RETRY_ATTEMPTS
;
75 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
76 mips_ejtag_drscan_32(ejtag_info
, &v
);
78 /* Initiate DMA Read & set DSTRT */
79 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
80 ejtag_ctrl
= EJTAG_CTRL_DMAACC
| EJTAG_CTRL_DRWN
| EJTAG_CTRL_DMA_WORD
| EJTAG_CTRL_DSTRT
| ejtag_info
->ejtag_ctrl
;
81 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
83 /* Wait for DSTRT to Clear */
84 ejtag_dma_dstrt_poll(ejtag_info
);
87 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
88 mips_ejtag_drscan_32(ejtag_info
, data
);
90 /* Clear DMA & Check DERR */
91 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
92 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
93 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
94 if (ejtag_ctrl
& EJTAG_CTRL_DERR
) {
96 LOG_ERROR("DMA Read Addr = %08" PRIx32
" Data = ERROR ON READ (retrying)", addr
);
97 goto begin_ejtag_dma_read
;
99 LOG_ERROR("DMA Read Addr = %08" PRIx32
" Data = ERROR ON READ", addr
);
100 return ERROR_JTAG_DEVICE_ERROR
;
106 static int ejtag_dma_read_h(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint16_t *data
)
110 int retries
= RETRY_ATTEMPTS
;
112 begin_ejtag_dma_read_h
:
116 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
117 mips_ejtag_drscan_32(ejtag_info
, &v
);
119 /* Initiate DMA Read & set DSTRT */
120 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
121 ejtag_ctrl
= EJTAG_CTRL_DMAACC
| EJTAG_CTRL_DRWN
| EJTAG_CTRL_DMA_HALFWORD
|
122 EJTAG_CTRL_DSTRT
| ejtag_info
->ejtag_ctrl
;
123 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
125 /* Wait for DSTRT to Clear */
126 ejtag_dma_dstrt_poll(ejtag_info
);
129 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
130 mips_ejtag_drscan_32(ejtag_info
, &v
);
132 /* Clear DMA & Check DERR */
133 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
134 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
135 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
136 if (ejtag_ctrl
& EJTAG_CTRL_DERR
) {
138 LOG_ERROR("DMA Read Addr = %08" PRIx32
" Data = ERROR ON READ (retrying)", addr
);
139 goto begin_ejtag_dma_read_h
;
141 LOG_ERROR("DMA Read Addr = %08" PRIx32
" Data = ERROR ON READ", addr
);
142 return ERROR_JTAG_DEVICE_ERROR
;
145 /* Handle the bigendian/littleendian */
147 *data
= (v
>> 16) & 0xffff;
149 *data
= (v
& 0x0000ffff);
154 static int ejtag_dma_read_b(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint8_t *data
)
158 int retries
= RETRY_ATTEMPTS
;
160 begin_ejtag_dma_read_b
:
164 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
165 mips_ejtag_drscan_32(ejtag_info
, &v
);
167 /* Initiate DMA Read & set DSTRT */
168 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
169 ejtag_ctrl
= EJTAG_CTRL_DMAACC
| EJTAG_CTRL_DRWN
| EJTAG_CTRL_DMA_BYTE
| EJTAG_CTRL_DSTRT
| ejtag_info
->ejtag_ctrl
;
170 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
172 /* Wait for DSTRT to Clear */
173 ejtag_dma_dstrt_poll(ejtag_info
);
176 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
177 mips_ejtag_drscan_32(ejtag_info
, &v
);
179 /* Clear DMA & Check DERR */
180 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
181 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
182 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
183 if (ejtag_ctrl
& EJTAG_CTRL_DERR
) {
185 LOG_ERROR("DMA Read Addr = %08" PRIx32
" Data = ERROR ON READ (retrying)", addr
);
186 goto begin_ejtag_dma_read_b
;
188 LOG_ERROR("DMA Read Addr = %08" PRIx32
" Data = ERROR ON READ", addr
);
189 return ERROR_JTAG_DEVICE_ERROR
;
192 /* Handle the bigendian/littleendian */
193 switch (addr
& 0x3) {
198 *data
= (v
>> 8) & 0xff;
201 *data
= (v
>> 16) & 0xff;
204 *data
= (v
>> 24) & 0xff;
211 static int ejtag_dma_write(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint32_t data
)
215 int retries
= RETRY_ATTEMPTS
;
217 begin_ejtag_dma_write
:
221 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
222 mips_ejtag_drscan_32(ejtag_info
, &v
);
226 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
227 mips_ejtag_drscan_32(ejtag_info
, &v
);
229 /* Initiate DMA Write & set DSTRT */
230 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
231 ejtag_ctrl
= EJTAG_CTRL_DMAACC
| EJTAG_CTRL_DMA_WORD
| EJTAG_CTRL_DSTRT
| ejtag_info
->ejtag_ctrl
;
232 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
234 /* Wait for DSTRT to Clear */
235 ejtag_dma_dstrt_poll(ejtag_info
);
237 /* Clear DMA & Check DERR */
238 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
239 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
240 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
241 if (ejtag_ctrl
& EJTAG_CTRL_DERR
) {
243 LOG_ERROR("DMA Write Addr = %08" PRIx32
" Data = ERROR ON WRITE (retrying)", addr
);
244 goto begin_ejtag_dma_write
;
246 LOG_ERROR("DMA Write Addr = %08" PRIx32
" Data = ERROR ON WRITE", addr
);
247 return ERROR_JTAG_DEVICE_ERROR
;
253 static int ejtag_dma_write_h(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint32_t data
)
257 int retries
= RETRY_ATTEMPTS
;
259 /* Handle the bigendian/littleendian */
263 begin_ejtag_dma_write_h
:
267 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
268 mips_ejtag_drscan_32(ejtag_info
, &v
);
272 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
273 mips_ejtag_drscan_32(ejtag_info
, &v
);
275 /* Initiate DMA Write & set DSTRT */
276 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
277 ejtag_ctrl
= EJTAG_CTRL_DMAACC
| EJTAG_CTRL_DMA_HALFWORD
| EJTAG_CTRL_DSTRT
| ejtag_info
->ejtag_ctrl
;
278 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
280 /* Wait for DSTRT to Clear */
281 ejtag_dma_dstrt_poll(ejtag_info
);
283 /* Clear DMA & Check DERR */
284 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
285 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
286 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
287 if (ejtag_ctrl
& EJTAG_CTRL_DERR
) {
289 LOG_ERROR("DMA Write Addr = %08" PRIx32
" Data = ERROR ON WRITE (retrying)", addr
);
290 goto begin_ejtag_dma_write_h
;
292 LOG_ERROR("DMA Write Addr = %08" PRIx32
" Data = ERROR ON WRITE", addr
);
293 return ERROR_JTAG_DEVICE_ERROR
;
299 static int ejtag_dma_write_b(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint32_t data
)
303 int retries
= RETRY_ATTEMPTS
;
305 /* Handle the bigendian/littleendian */
310 begin_ejtag_dma_write_b
:
314 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
315 mips_ejtag_drscan_32(ejtag_info
, &v
);
319 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
320 mips_ejtag_drscan_32(ejtag_info
, &v
);
322 /* Initiate DMA Write & set DSTRT */
323 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
324 ejtag_ctrl
= EJTAG_CTRL_DMAACC
| EJTAG_CTRL_DMA_BYTE
| EJTAG_CTRL_DSTRT
| ejtag_info
->ejtag_ctrl
;
325 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
327 /* Wait for DSTRT to Clear */
328 ejtag_dma_dstrt_poll(ejtag_info
);
330 /* Clear DMA & Check DERR */
331 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
332 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
333 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
334 if (ejtag_ctrl
& EJTAG_CTRL_DERR
) {
336 LOG_ERROR("DMA Write Addr = %08" PRIx32
" Data = ERROR ON WRITE (retrying)", addr
);
337 goto begin_ejtag_dma_write_b
;
339 LOG_ERROR("DMA Write Addr = %08" PRIx32
" Data = ERROR ON WRITE", addr
);
340 return ERROR_JTAG_DEVICE_ERROR
;
346 int mips32_dmaacc_read_mem(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int size
, int count
, void *buf
)
350 return mips32_dmaacc_read_mem8(ejtag_info
, addr
, count
, (uint8_t *)buf
);
352 return mips32_dmaacc_read_mem16(ejtag_info
, addr
, count
, (uint16_t *)buf
);
354 return mips32_dmaacc_read_mem32(ejtag_info
, addr
, count
, (uint32_t *)buf
);
360 static int mips32_dmaacc_read_mem32(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int count
, uint32_t *buf
)
365 for (i
= 0; i
< count
; i
++) {
366 retval
= ejtag_dma_read(ejtag_info
, addr
+ i
* sizeof(*buf
), &buf
[i
]);
367 if (retval
!= ERROR_OK
)
374 static int mips32_dmaacc_read_mem16(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int count
, uint16_t *buf
)
379 for (i
= 0; i
< count
; i
++) {
380 retval
= ejtag_dma_read_h(ejtag_info
, addr
+ i
* sizeof(*buf
), &buf
[i
]);
381 if (retval
!= ERROR_OK
)
388 static int mips32_dmaacc_read_mem8(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int count
, uint8_t *buf
)
393 for (i
= 0; i
< count
; i
++) {
394 retval
= ejtag_dma_read_b(ejtag_info
, addr
+ i
* sizeof(*buf
), &buf
[i
]);
395 if (retval
!= ERROR_OK
)
402 int mips32_dmaacc_write_mem(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int size
, int count
, void *buf
)
406 return mips32_dmaacc_write_mem8(ejtag_info
, addr
, count
, (uint8_t *)buf
);
408 return mips32_dmaacc_write_mem16(ejtag_info
, addr
, count
, (uint16_t *)buf
);
410 return mips32_dmaacc_write_mem32(ejtag_info
, addr
, count
, (uint32_t *)buf
);
416 static int mips32_dmaacc_write_mem32(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int count
, uint32_t *buf
)
421 for (i
= 0; i
< count
; i
++) {
422 retval
= ejtag_dma_write(ejtag_info
, addr
+ i
* sizeof(*buf
), buf
[i
]);
423 if (retval
!= ERROR_OK
)
430 static int mips32_dmaacc_write_mem16(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int count
, uint16_t *buf
)
435 for (i
= 0; i
< count
; i
++) {
436 retval
= ejtag_dma_write_h(ejtag_info
, addr
+ i
* sizeof(*buf
), buf
[i
]);
437 if (retval
!= ERROR_OK
)
444 static int mips32_dmaacc_write_mem8(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int count
, uint8_t *buf
)
449 for (i
= 0; i
< count
; i
++) {
450 retval
= ejtag_dma_write_b(ejtag_info
, addr
+ i
* sizeof(*buf
), buf
[i
]);
451 if (retval
!= ERROR_OK
)