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target: move regmaps to armv7m.c
[openocd.git] / src / target / armv7m.c
blob6c1732e92d5702faa02e92b7be46042ee3abc3c0
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
31 * *
32 ***************************************************************************/
33 #ifdef HAVE_CONFIG_H
34 #include "config.h"
35 #endif
36
37 #include "breakpoints.h"
38 #include "armv7m.h"
39 #include "algorithm.h"
40 #include "register.h"
41
42
43 #if 0
44 #define _DEBUG_INSTRUCTION_EXECUTION_
45 #endif
46
47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
48 char *armv7m_mode_strings[] =
49 {
50 "Thread", "Thread (User)", "Handler",
51 };
52
53 static char *armv7m_exception_strings[] =
54 {
55 "", "Reset", "NMI", "HardFault",
56 "MemManage", "BusFault", "UsageFault", "RESERVED",
57 "RESERVED", "RESERVED", "RESERVED", "SVCall",
58 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
59 };
60
61 /* PSP is used in some thread modes */
62 const int armv7m_psp_reg_map[17] = {
63 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
64 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
65 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
66 ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
67 ARMV7M_xPSR,
68 };
69
70 /* MSP is used in handler and some thread modes */
71 const int armv7m_msp_reg_map[17] = {
72 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
73 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
74 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
75 ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
76 ARMV7M_xPSR,
77 };
78
79 #ifdef ARMV7_GDB_HACKS
80 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
81
82 struct reg armv7m_gdb_dummy_cpsr_reg =
83 {
84 .name = "GDB dummy cpsr register",
85 .value = armv7m_gdb_dummy_cpsr_value,
86 .dirty = 0,
87 .valid = 1,
88 .size = 32,
89 .arch_info = NULL,
90 };
91 #endif
92
93 /*
94 * These registers are not memory-mapped. The ARMv7-M profile includes
95 * memory mapped registers too, such as for the NVIC (interrupt controller)
96 * and SysTick (timer) modules; those can mostly be treated as peripherals.
97 *
98 * The ARMv6-M profile is almost identical in this respect, except that it
99 * doesn't include basepri or faultmask registers.
100 */
101 static const struct {
102 unsigned id;
103 const char *name;
104 unsigned bits;
105 } armv7m_regs[] = {
106 { ARMV7M_R0, "r0", 32 },
107 { ARMV7M_R1, "r1", 32 },
108 { ARMV7M_R2, "r2", 32 },
109 { ARMV7M_R3, "r3", 32 },
110
111 { ARMV7M_R4, "r4", 32 },
112 { ARMV7M_R5, "r5", 32 },
113 { ARMV7M_R6, "r6", 32 },
114 { ARMV7M_R7, "r7", 32 },
115
116 { ARMV7M_R8, "r8", 32 },
117 { ARMV7M_R9, "r9", 32 },
118 { ARMV7M_R10, "r10", 32 },
119 { ARMV7M_R11, "r11", 32 },
120
121 { ARMV7M_R12, "r12", 32 },
122 { ARMV7M_R13, "sp", 32 },
123 { ARMV7M_R14, "lr", 32 },
124 { ARMV7M_PC, "pc", 32 },
125
126 { ARMV7M_xPSR, "xPSR", 32 },
127 { ARMV7M_MSP, "msp", 32 },
128 { ARMV7M_PSP, "psp", 32 },
129
130 { ARMV7M_PRIMASK, "primask", 1 },
131 { ARMV7M_BASEPRI, "basepri", 8 },
132 { ARMV7M_FAULTMASK, "faultmask", 1 },
133 { ARMV7M_CONTROL, "control", 2 },
134 };
135
136 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
137
138 /**
139 * Restores target context using the cache of core registers set up
140 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
141 */
142 int armv7m_restore_context(struct target *target)
143 {
144 int i;
145 struct armv7m_common *armv7m = target_to_armv7m(target);
146
147 LOG_DEBUG(" ");
148
149 if (armv7m->pre_restore_context)
150 armv7m->pre_restore_context(target);
151
152 for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
153 {
154 if (armv7m->core_cache->reg_list[i].dirty)
155 {
156 armv7m->write_core_reg(target, i);
157 }
158 }
159
160 return ERROR_OK;
161 }
162
163 /* Core state functions */
164
165 /**
166 * Maps ISR number (from xPSR) to name.
167 * Note that while names and meanings for the first sixteen are standardized
168 * (with zero not a true exception), external interrupts are only numbered.
169 * They are assigned by vendors, which generally assign different numbers to
170 * peripherals (such as UART0 or a USB peripheral controller).
171 */
172 char *armv7m_exception_string(int number)
173 {
174 static char enamebuf[32];
175
176 if ((number < 0) | (number > 511))
177 return "Invalid exception";
178 if (number < 16)
179 return armv7m_exception_strings[number];
180 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
181 return enamebuf;
182 }
183
184 static int armv7m_get_core_reg(struct reg *reg)
185 {
186 int retval;
187 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
188 struct target *target = armv7m_reg->target;
189 struct armv7m_common *armv7m = target_to_armv7m(target);
190
191 if (target->state != TARGET_HALTED)
192 {
193 return ERROR_TARGET_NOT_HALTED;
194 }
195
196 retval = armv7m->read_core_reg(target, armv7m_reg->num);
197
198 return retval;
199 }
200
201 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
202 {
203 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
204 struct target *target = armv7m_reg->target;
205 uint32_t value = buf_get_u32(buf, 0, 32);
206
207 if (target->state != TARGET_HALTED)
208 {
209 return ERROR_TARGET_NOT_HALTED;
210 }
211
212 buf_set_u32(reg->value, 0, 32, value);
213 reg->dirty = 1;
214 reg->valid = 1;
215
216 return ERROR_OK;
217 }
218
219 static int armv7m_read_core_reg(struct target *target, unsigned num)
220 {
221 uint32_t reg_value;
222 int retval;
223 struct armv7m_core_reg * armv7m_core_reg;
224 struct armv7m_common *armv7m = target_to_armv7m(target);
225
226 if (num >= ARMV7M_NUM_REGS)
227 return ERROR_COMMAND_SYNTAX_ERROR;
228
229 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
230 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
231 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
232 armv7m->core_cache->reg_list[num].valid = 1;
233 armv7m->core_cache->reg_list[num].dirty = 0;
234
235 return retval;
236 }
237
238 static int armv7m_write_core_reg(struct target *target, unsigned num)
239 {
240 int retval;
241 uint32_t reg_value;
242 struct armv7m_core_reg *armv7m_core_reg;
243 struct armv7m_common *armv7m = target_to_armv7m(target);
244
245 if (num >= ARMV7M_NUM_REGS)
246 return ERROR_COMMAND_SYNTAX_ERROR;
247
248 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
249 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
250 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
251 if (retval != ERROR_OK)
252 {
253 LOG_ERROR("JTAG failure");
254 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
255 return ERROR_JTAG_DEVICE_ERROR;
256 }
257 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
258 armv7m->core_cache->reg_list[num].valid = 1;
259 armv7m->core_cache->reg_list[num].dirty = 0;
260
261 return ERROR_OK;
262 }
263
264 /**
265 * Returns generic ARM userspace registers to GDB.
266 * GDB doesn't quite understand that most ARMs don't have floating point
267 * hardware, so this also fakes a set of long-obsolete FPA registers that
268 * are not used in EABI based software stacks.
269 */
270 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
271 {
272 struct armv7m_common *armv7m = target_to_armv7m(target);
273 int i;
274
275 *reg_list_size = 26;
276 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
277
278 /*
279 * GDB register packet format for ARM:
280 * - the first 16 registers are r0..r15
281 * - (obsolete) 8 FPA registers
282 * - (obsolete) FPA status
283 * - CPSR
284 */
285 for (i = 0; i < 16; i++)
286 {
287 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
288 }
289
290 for (i = 16; i < 24; i++)
291 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
292 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
293
294 #ifdef ARMV7_GDB_HACKS
295 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
296 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
297
298 /* ARMV7M is always in thumb mode, try to make GDB understand this
299 * if it does not support this arch */
300 *((char*)armv7m->arm.pc->value) |= 1;
301 #else
302 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
303 #endif
304
305 return ERROR_OK;
306 }
307
308 /** Runs a Thumb algorithm in the target. */
309 int armv7m_run_algorithm(struct target *target,
310 int num_mem_params, struct mem_param *mem_params,
311 int num_reg_params, struct reg_param *reg_params,
312 uint32_t entry_point, uint32_t exit_point,
313 int timeout_ms, void *arch_info)
314 {
315 int retval;
316
317 retval = armv7m_start_algorithm(target,
318 num_mem_params, mem_params,
319 num_reg_params, reg_params,
320 entry_point, exit_point,
321 arch_info);
322
323 if (retval == ERROR_OK)
324 retval = armv7m_wait_algorithm(target,
325 num_mem_params, mem_params,
326 num_reg_params, reg_params,
327 exit_point, timeout_ms,
328 arch_info);
329
330 return retval;
331 }
332
333 /** Starts a Thumb algorithm in the target. */
334 int armv7m_start_algorithm(struct target *target,
335 int num_mem_params, struct mem_param *mem_params,
336 int num_reg_params, struct reg_param *reg_params,
337 uint32_t entry_point, uint32_t exit_point,
338 void *arch_info)
339 {
340 struct armv7m_common *armv7m = target_to_armv7m(target);
341 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
342 enum armv7m_mode core_mode = armv7m->core_mode;
343 int retval = ERROR_OK;
344
345 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
346 * at the exit point */
347
348 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
349 {
350 LOG_ERROR("current target isn't an ARMV7M target");
351 return ERROR_TARGET_INVALID;
352 }
353
354 if (target->state != TARGET_HALTED)
355 {
356 LOG_WARNING("target not halted");
357 return ERROR_TARGET_NOT_HALTED;
358 }
359
360 /* refresh core register cache */
361 /* Not needed if core register cache is always consistent with target process state */
362 for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++)
363 {
364 if (!armv7m->core_cache->reg_list[i].valid)
365 armv7m->read_core_reg(target, i);
366 armv7m_algorithm_info->context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
367 }
368
369 for (int i = 0; i < num_mem_params; i++)
370 {
371 // TODO: Write only out params
372 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
373 return retval;
374 }
375
376 for (int i = 0; i < num_reg_params; i++)
377 {
378 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
379 // uint32_t regvalue;
380
381 if (!reg)
382 {
383 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
384 return ERROR_COMMAND_SYNTAX_ERROR;
385 }
386
387 if (reg->size != reg_params[i].size)
388 {
389 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
390 return ERROR_COMMAND_SYNTAX_ERROR;
391 }
392
393 // regvalue = buf_get_u32(reg_params[i].value, 0, 32);
394 armv7m_set_core_reg(reg, reg_params[i].value);
395 }
396
397 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
398 {
399 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
400 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
401 0, 1, armv7m_algorithm_info->core_mode);
402 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
403 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
404 }
405 armv7m_algorithm_info->core_mode = core_mode;
406
407 retval = target_resume(target, 0, entry_point, 1, 1);
408
409 return retval;
410 }
411
412 /** Waits for an algorithm in the target. */
413 int armv7m_wait_algorithm(struct target *target,
414 int num_mem_params, struct mem_param *mem_params,
415 int num_reg_params, struct reg_param *reg_params,
416 uint32_t exit_point, int timeout_ms,
417 void *arch_info)
418 {
419 struct armv7m_common *armv7m = target_to_armv7m(target);
420 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
421 int retval = ERROR_OK;
422 uint32_t pc;
423
424 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
425 * at the exit point */
426
427 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
428 {
429 LOG_ERROR("current target isn't an ARMV7M target");
430 return ERROR_TARGET_INVALID;
431 }
432
433 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
434 /* If the target fails to halt due to the breakpoint, force a halt */
435 if (retval != ERROR_OK || target->state != TARGET_HALTED)
436 {
437 if ((retval = target_halt(target)) != ERROR_OK)
438 return retval;
439 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
440 {
441 return retval;
442 }
443 return ERROR_TARGET_TIMEOUT;
444 }
445
446 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
447 if (exit_point && (pc != exit_point))
448 {
449 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32 , pc, exit_point);
450 return ERROR_TARGET_TIMEOUT;
451 }
452
453 /* Read memory values to mem_params[] */
454 for (int i = 0; i < num_mem_params; i++)
455 {
456 if (mem_params[i].direction != PARAM_OUT)
457 if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
458 {
459 return retval;
460 }
461 }
462
463 /* Copy core register values to reg_params[] */
464 for (int i = 0; i < num_reg_params; i++)
465 {
466 if (reg_params[i].direction != PARAM_OUT)
467 {
468 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
469
470 if (!reg)
471 {
472 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
473 return ERROR_COMMAND_SYNTAX_ERROR;
474 }
475
476 if (reg->size != reg_params[i].size)
477 {
478 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
479 return ERROR_COMMAND_SYNTAX_ERROR;
480 }
481
482 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
483 }
484 }
485
486 for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
487 {
488 uint32_t regvalue;
489 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
490 if (regvalue != armv7m_algorithm_info->context[i])
491 {
492 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
493 armv7m->core_cache->reg_list[i].name, armv7m_algorithm_info->context[i]);
494 buf_set_u32(armv7m->core_cache->reg_list[i].value,
495 0, 32, armv7m_algorithm_info->context[i]);
496 armv7m->core_cache->reg_list[i].valid = 1;
497 armv7m->core_cache->reg_list[i].dirty = 1;
498 }
499 }
500
501 armv7m->core_mode = armv7m_algorithm_info->core_mode;
502
503 return retval;
504 }
505
506 /** Logs summary of ARMv7-M state for a halted target. */
507 int armv7m_arch_state(struct target *target)
508 {
509 struct armv7m_common *armv7m = target_to_armv7m(target);
510 struct arm *arm = &armv7m->arm;
511 uint32_t ctrl, sp;
512
513 ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
514 sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
515
516 LOG_USER("target halted due to %s, current mode: %s %s\n"
517 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
518 debug_reason_name(target),
519 armv7m_mode_strings[armv7m->core_mode],
520 armv7m_exception_string(armv7m->exception_number),
521 buf_get_u32(arm->cpsr->value, 0, 32),
522 buf_get_u32(arm->pc->value, 0, 32),
523 (ctrl & 0x02) ? 'p' : 'm',
524 sp,
525 arm->is_semihosting ? ", semihosting" : "");
526
527 return ERROR_OK;
528 }
529 static const struct reg_arch_type armv7m_reg_type = {
530 .get = armv7m_get_core_reg,
531 .set = armv7m_set_core_reg,
532 };
533
534 /** Builds cache of architecturally defined registers. */
535 struct reg_cache *armv7m_build_reg_cache(struct target *target)
536 {
537 struct armv7m_common *armv7m = target_to_armv7m(target);
538 struct arm *arm = &armv7m->arm;
539 int num_regs = ARMV7M_NUM_REGS;
540 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
541 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
542 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
543 struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
544 int i;
545
546 #ifdef ARMV7_GDB_HACKS
547 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
548 #endif
549
550 /* Build the process context cache */
551 cache->name = "arm v7m registers";
552 cache->next = NULL;
553 cache->reg_list = reg_list;
554 cache->num_regs = num_regs;
555 (*cache_p) = cache;
556 armv7m->core_cache = cache;
557
558 for (i = 0; i < num_regs; i++)
559 {
560 arch_info[i].num = armv7m_regs[i].id;
561 arch_info[i].target = target;
562 arch_info[i].armv7m_common = armv7m;
563 reg_list[i].name = armv7m_regs[i].name;
564 reg_list[i].size = armv7m_regs[i].bits;
565 reg_list[i].value = calloc(1, 4);
566 reg_list[i].dirty = 0;
567 reg_list[i].valid = 0;
568 reg_list[i].type = &armv7m_reg_type;
569 reg_list[i].arch_info = &arch_info[i];
570 }
571
572 arm->cpsr = reg_list + ARMV7M_xPSR;
573 arm->pc = reg_list + ARMV7M_PC;
574 arm->core_cache = cache;
575 return cache;
576 }
577
578 static int armv7m_setup_semihosting(struct target *target, int enable)
579 {
580 /* nothing todo for armv7m */
581 return ERROR_OK;
582 }
583
584 /** Sets up target as a generic ARMv7-M core */
585 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
586 {
587 struct arm *arm = &armv7m->arm;
588
589 armv7m->common_magic = ARMV7M_COMMON_MAGIC;
590
591 arm->core_type = ARM_MODE_THREAD;
592 arm->arch_info = armv7m;
593 arm->setup_semihosting = armv7m_setup_semihosting;
594
595 /* FIXME remove v7m-specific r/w core_reg functions;
596 * use the generic ARM core support..
597 */
598 armv7m->read_core_reg = armv7m_read_core_reg;
599 armv7m->write_core_reg = armv7m_write_core_reg;
600
601 return arm_init_arch_info(target, arm);
602 }
603
604 /** Generates a CRC32 checksum of a memory region. */
605 int armv7m_checksum_memory(struct target *target,
606 uint32_t address, uint32_t count, uint32_t* checksum)
607 {
608 struct working_area *crc_algorithm;
609 struct armv7m_algorithm armv7m_info;
610 struct reg_param reg_params[2];
611 int retval;
612
613 /* see contib/loaders/checksum/armv7m_crc.s for src */
614
615 static const uint16_t cortex_m3_crc_code[] = {
616 0x4602, /* mov r2, r0 */
617 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
618 0x460B, /* mov r3, r1 */
619 0xF04F, 0x0400, /* mov r4, #0 */
620 0xE013, /* b ncomp */
621 /* nbyte: */
622 0x5D11, /* ldrb r1, [r2, r4] */
623 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
624 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
625
626 0xF04F, 0x0500, /* mov r5, #0 */
627 /* loop: */
628 0x2800, /* cmp r0, #0 */
629 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
630 0xF105, 0x0501, /* add r5, r5, #1 */
631 0x4630, /* mov r0, r6 */
632 0xBFB8, /* it lt */
633 0xEA86, 0x0007, /* eor r0, r6, r7 */
634 0x2D08, /* cmp r5, #8 */
635 0xD1F4, /* bne loop */
636
637 0xF104, 0x0401, /* add r4, r4, #1 */
638 /* ncomp: */
639 0x429C, /* cmp r4, r3 */
640 0xD1E9, /* bne nbyte */
641 0xBE00, /* bkpt #0 */
642 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
643 };
644
645 uint32_t i;
646
647 retval = target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm);
648 if (retval != ERROR_OK)
649 return retval;
650
651 /* convert flash writing code into a buffer in target endianness */
652 for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++) {
653 retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i]);
654 if (retval != ERROR_OK)
655 goto cleanup;
656 }
657
658 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
659 armv7m_info.core_mode = ARMV7M_MODE_ANY;
660
661 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
662 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
663
664 buf_set_u32(reg_params[0].value, 0, 32, address);
665 buf_set_u32(reg_params[1].value, 0, 32, count);
666
667 int timeout = 20000 * (1 + (count / (1024 * 1024)));
668
669 retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
670 crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6),
671 timeout, &armv7m_info);
672
673 if (retval == ERROR_OK)
674 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
675 else
676 LOG_ERROR("error executing cortex_m3 crc algorithm");
677
678 destroy_reg_param(&reg_params[0]);
679 destroy_reg_param(&reg_params[1]);
680
681 cleanup:
682 target_free_working_area(target, crc_algorithm);
683
684 return retval;
685 }
686
687 /** Checks whether a memory region is zeroed. */
688 int armv7m_blank_check_memory(struct target *target,
689 uint32_t address, uint32_t count, uint32_t* blank)
690 {
691 struct working_area *erase_check_algorithm;
692 struct reg_param reg_params[3];
693 struct armv7m_algorithm armv7m_info;
694 int retval;
695 uint32_t i;
696
697 static const uint16_t erase_check_code[] =
698 {
699 /* loop: */
700 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
701 0xEA02, 0x0203, /* and r2, r2, r3 */
702 0x3901, /* subs r1, r1, #1 */
703 0xD1F9, /* bne loop */
704 0xBE00, /* bkpt #0 */
705 };
706
707 /* make sure we have a working area */
708 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
709 {
710 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
711 }
712
713 /* convert flash writing code into a buffer in target endianness */
714 for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
715 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
716
717 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
718 armv7m_info.core_mode = ARMV7M_MODE_ANY;
719
720 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
721 buf_set_u32(reg_params[0].value, 0, 32, address);
722
723 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
724 buf_set_u32(reg_params[1].value, 0, 32, count);
725
726 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
727 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
728
729 retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address,
730 erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
731 10000, &armv7m_info);
732
733 if (retval == ERROR_OK)
734 *blank = buf_get_u32(reg_params[2].value, 0, 32);
735
736 destroy_reg_param(&reg_params[0]);
737 destroy_reg_param(&reg_params[1]);
738 destroy_reg_param(&reg_params[2]);
739
740 target_free_working_area(target, erase_check_algorithm);
741
742 return retval;
743 }
744
745 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
746 {
747 struct armv7m_common *armv7m = target_to_armv7m(target);
748 struct reg *r = armv7m->arm.pc;
749 bool result = false;
750
751
752 /* if we halted last time due to a bkpt instruction
753 * then we have to manually step over it, otherwise
754 * the core will break again */
755
756 if (target->debug_reason == DBG_REASON_BREAKPOINT)
757 {
758 uint16_t op;
759 uint32_t pc = buf_get_u32(r->value, 0, 32);
760
761 pc &= ~1;
762 if (target_read_u16(target, pc, &op) == ERROR_OK)
763 {
764 if ((op & 0xFF00) == 0xBE00)
765 {
766 pc = buf_get_u32(r->value, 0, 32) + 2;
767 buf_set_u32(r->value, 0, 32, pc);
768 r->dirty = true;
769 r->valid = true;
770 result = true;
771 LOG_DEBUG("Skipping over BKPT instruction");
772 }
773 }
774 }
775
776 if (inst_found) {
777 *inst_found = result;
778 }
779
780 return ERROR_OK;
781 }
782
783 const struct command_registration armv7m_command_handlers[] = {
784 {
785 .chain = arm_command_handlers,
786 },
787 {
788 .chain = dap_command_handlers,
789 },
790 COMMAND_REGISTRATION_DONE
791 };
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