?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
NOR: cleanup driver decls
[openocd.git] / src / flash / nor / stm32x.c
blobeaa3a0e450177587d510c6de0c4c23a4f9ee0b1b
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
58 {
59 struct target *target = bank->target;
60 uint32_t status;
61
62 target_read_u32(target, STM32_FLASH_SR, &status);
63
64 return status;
65 }
66
67 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
68 {
69 struct target *target = bank->target;
70 uint32_t status;
71
72 /* wait for busy to clear */
73 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
74 {
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 alive_sleep(1);
77 }
78 /* Clear but report errors */
79 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
80 {
81 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
82 }
83 return status;
84 }
85
86 static int stm32x_read_options(struct flash_bank *bank)
87 {
88 uint32_t optiondata;
89 struct stm32x_flash_bank *stm32x_info = NULL;
90 struct target *target = bank->target;
91
92 stm32x_info = bank->driver_priv;
93
94 /* read current option bytes */
95 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
96
97 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
98 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
99
100 if (optiondata & (1 << OPT_READOUT))
101 LOG_INFO("Device Security Bit Set");
102
103 /* each bit refers to a 4bank protection */
104 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
105
106 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
107 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
108 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
109 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
110
111 return ERROR_OK;
112 }
113
114 static int stm32x_erase_options(struct flash_bank *bank)
115 {
116 struct stm32x_flash_bank *stm32x_info = NULL;
117 struct target *target = bank->target;
118 uint32_t status;
119
120 stm32x_info = bank->driver_priv;
121
122 /* read current options */
123 stm32x_read_options(bank);
124
125 /* unlock flash registers */
126 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
127 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
128
129 /* unlock option flash registers */
130 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
131 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
132
133 /* erase option bytes */
134 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
135 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
136
137 status = stm32x_wait_status_busy(bank, 10);
138
139 if (status & FLASH_WRPRTERR)
140 return ERROR_FLASH_OPERATION_FAILED;
141 if (status & FLASH_PGERR)
142 return ERROR_FLASH_OPERATION_FAILED;
143
144 /* clear readout protection and complementary option bytes
145 * this will also force a device unlock if set */
146 stm32x_info->option_bytes.RDP = 0x5AA5;
147
148 return ERROR_OK;
149 }
150
151 static int stm32x_write_options(struct flash_bank *bank)
152 {
153 struct stm32x_flash_bank *stm32x_info = NULL;
154 struct target *target = bank->target;
155 uint32_t status;
156
157 stm32x_info = bank->driver_priv;
158
159 /* unlock flash registers */
160 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
161 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
162
163 /* unlock option flash registers */
164 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
165 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
166
167 /* program option bytes */
168 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
169
170 /* write user option byte */
171 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
172
173 status = stm32x_wait_status_busy(bank, 10);
174
175 if (status & FLASH_WRPRTERR)
176 return ERROR_FLASH_OPERATION_FAILED;
177 if (status & FLASH_PGERR)
178 return ERROR_FLASH_OPERATION_FAILED;
179
180 /* write protection byte 1 */
181 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
182
183 status = stm32x_wait_status_busy(bank, 10);
184
185 if (status & FLASH_WRPRTERR)
186 return ERROR_FLASH_OPERATION_FAILED;
187 if (status & FLASH_PGERR)
188 return ERROR_FLASH_OPERATION_FAILED;
189
190 /* write protection byte 2 */
191 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
192
193 status = stm32x_wait_status_busy(bank, 10);
194
195 if (status & FLASH_WRPRTERR)
196 return ERROR_FLASH_OPERATION_FAILED;
197 if (status & FLASH_PGERR)
198 return ERROR_FLASH_OPERATION_FAILED;
199
200 /* write protection byte 3 */
201 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
202
203 status = stm32x_wait_status_busy(bank, 10);
204
205 if (status & FLASH_WRPRTERR)
206 return ERROR_FLASH_OPERATION_FAILED;
207 if (status & FLASH_PGERR)
208 return ERROR_FLASH_OPERATION_FAILED;
209
210 /* write protection byte 4 */
211 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
212
213 status = stm32x_wait_status_busy(bank, 10);
214
215 if (status & FLASH_WRPRTERR)
216 return ERROR_FLASH_OPERATION_FAILED;
217 if (status & FLASH_PGERR)
218 return ERROR_FLASH_OPERATION_FAILED;
219
220 /* write readout protection bit */
221 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
222
223 status = stm32x_wait_status_busy(bank, 10);
224
225 if (status & FLASH_WRPRTERR)
226 return ERROR_FLASH_OPERATION_FAILED;
227 if (status & FLASH_PGERR)
228 return ERROR_FLASH_OPERATION_FAILED;
229
230 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
231
232 return ERROR_OK;
233 }
234
235 static int stm32x_protect_check(struct flash_bank *bank)
236 {
237 struct target *target = bank->target;
238 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
239
240 uint32_t protection;
241 int i, s;
242 int num_bits;
243 int set;
244
245 if (target->state != TARGET_HALTED)
246 {
247 LOG_ERROR("Target not halted");
248 return ERROR_TARGET_NOT_HALTED;
249 }
250
251 /* medium density - each bit refers to a 4bank protection
252 * high density - each bit refers to a 2bank protection */
253 target_read_u32(target, STM32_FLASH_WRPR, &protection);
254
255 /* medium density - each protection bit is for 4 * 1K pages
256 * high density - each protection bit is for 2 * 2K pages */
257 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
258
259 if (stm32x_info->ppage_size == 2)
260 {
261 /* high density flash/connectivity line protection */
262
263 set = 1;
264
265 if (protection & (1 << 31))
266 set = 0;
267
268 /* bit 31 controls sector 62 - 255 protection for high density
269 * bit 31 controls sector 62 - 127 protection for connectivity line */
270 for (s = 62; s < bank->num_sectors; s++)
271 {
272 bank->sectors[s].is_protected = set;
273 }
274
275 if (bank->num_sectors > 61)
276 num_bits = 31;
277
278 for (i = 0; i < num_bits; i++)
279 {
280 set = 1;
281
282 if (protection & (1 << i))
283 set = 0;
284
285 for (s = 0; s < stm32x_info->ppage_size; s++)
286 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
287 }
288 }
289 else
290 {
291 /* low/medium density flash protection */
292 for (i = 0; i < num_bits; i++)
293 {
294 set = 1;
295
296 if (protection & (1 << i))
297 set = 0;
298
299 for (s = 0; s < stm32x_info->ppage_size; s++)
300 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
301 }
302 }
303
304 return ERROR_OK;
305 }
306
307 static int stm32x_erase(struct flash_bank *bank, int first, int last)
308 {
309 struct target *target = bank->target;
310 int i;
311 uint32_t status;
312
313 if (bank->target->state != TARGET_HALTED)
314 {
315 LOG_ERROR("Target not halted");
316 return ERROR_TARGET_NOT_HALTED;
317 }
318
319 if ((first == 0) && (last == (bank->num_sectors - 1)))
320 {
321 return stm32x_mass_erase(bank);
322 }
323
324 /* unlock flash registers */
325 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
326 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
327
328 for (i = first; i <= last; i++)
329 {
330 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
331 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
332 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
333
334 status = stm32x_wait_status_busy(bank, 10);
335
336 if (status & FLASH_WRPRTERR)
337 return ERROR_FLASH_OPERATION_FAILED;
338 if (status & FLASH_PGERR)
339 return ERROR_FLASH_OPERATION_FAILED;
340 bank->sectors[i].is_erased = 1;
341 }
342
343 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
344
345 return ERROR_OK;
346 }
347
348 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
349 {
350 struct stm32x_flash_bank *stm32x_info = NULL;
351 struct target *target = bank->target;
352 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
353 int i, reg, bit;
354 int status;
355 uint32_t protection;
356
357 stm32x_info = bank->driver_priv;
358
359 if (target->state != TARGET_HALTED)
360 {
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
363 }
364
365 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
366 {
367 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
368 return ERROR_FLASH_SECTOR_INVALID;
369 }
370
371 /* medium density - each bit refers to a 4bank protection
372 * high density - each bit refers to a 2bank protection */
373 target_read_u32(target, STM32_FLASH_WRPR, &protection);
374
375 prot_reg[0] = (uint16_t)protection;
376 prot_reg[1] = (uint16_t)(protection >> 8);
377 prot_reg[2] = (uint16_t)(protection >> 16);
378 prot_reg[3] = (uint16_t)(protection >> 24);
379
380 if (stm32x_info->ppage_size == 2)
381 {
382 /* high density flash */
383
384 /* bit 7 controls sector 62 - 255 protection */
385 if (last > 61)
386 {
387 if (set)
388 prot_reg[3] &= ~(1 << 7);
389 else
390 prot_reg[3] |= (1 << 7);
391 }
392
393 if (first > 61)
394 first = 62;
395 if (last > 61)
396 last = 61;
397
398 for (i = first; i <= last; i++)
399 {
400 reg = (i / stm32x_info->ppage_size) / 8;
401 bit = (i / stm32x_info->ppage_size) - (reg * 8);
402
403 if (set)
404 prot_reg[reg] &= ~(1 << bit);
405 else
406 prot_reg[reg] |= (1 << bit);
407 }
408 }
409 else
410 {
411 /* medium density flash */
412 for (i = first; i <= last; i++)
413 {
414 reg = (i / stm32x_info->ppage_size) / 8;
415 bit = (i / stm32x_info->ppage_size) - (reg * 8);
416
417 if (set)
418 prot_reg[reg] &= ~(1 << bit);
419 else
420 prot_reg[reg] |= (1 << bit);
421 }
422 }
423
424 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
425 return status;
426
427 stm32x_info->option_bytes.protection[0] = prot_reg[0];
428 stm32x_info->option_bytes.protection[1] = prot_reg[1];
429 stm32x_info->option_bytes.protection[2] = prot_reg[2];
430 stm32x_info->option_bytes.protection[3] = prot_reg[3];
431
432 return stm32x_write_options(bank);
433 }
434
435 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
436 {
437 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
438 struct target *target = bank->target;
439 uint32_t buffer_size = 16384;
440 struct working_area *source;
441 uint32_t address = bank->base + offset;
442 struct reg_param reg_params[4];
443 struct armv7m_algorithm armv7m_info;
444 int retval = ERROR_OK;
445
446 uint8_t stm32x_flash_write_code[] = {
447 /* write: */
448 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
449 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
450 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
451 0x23, 0x60, /* str r3, [r4, #0] */
452 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
453 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
454 /* busy: */
455 0x2B, 0x68, /* ldr r3, [r5, #0] */
456 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
457 0xFB, 0xD0, /* beq busy */
458 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
459 0x01, 0xD1, /* bne exit */
460 0x01, 0x3A, /* subs r2, r2, #1 */
461 0xED, 0xD1, /* bne write */
462 /* exit: */
463 0xFE, 0xE7, /* b exit */
464 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
465 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
466 };
467
468 /* flash write code */
469 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
470 {
471 LOG_WARNING("no working area available, can't do block memory writes");
472 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
473 };
474
475 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
476 return retval;
477
478 /* memory buffer */
479 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
480 {
481 buffer_size /= 2;
482 if (buffer_size <= 256)
483 {
484 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
485 if (stm32x_info->write_algorithm)
486 target_free_working_area(target, stm32x_info->write_algorithm);
487
488 LOG_WARNING("no large enough working area available, can't do block memory writes");
489 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
490 }
491 };
492
493 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
494 armv7m_info.core_mode = ARMV7M_MODE_ANY;
495
496 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
497 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
498 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
499 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
500
501 while (count > 0)
502 {
503 uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
504
505 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
506 break;
507
508 buf_set_u32(reg_params[0].value, 0, 32, source->address);
509 buf_set_u32(reg_params[1].value, 0, 32, address);
510 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
511
512 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
513 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
514 {
515 LOG_ERROR("error executing stm32x flash write algorithm");
516 retval = ERROR_FLASH_OPERATION_FAILED;
517 break;
518 }
519
520 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
521 {
522 LOG_ERROR("flash memory not erased before writing");
523 /* Clear but report errors */
524 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
525 retval = ERROR_FLASH_OPERATION_FAILED;
526 break;
527 }
528
529 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
530 {
531 LOG_ERROR("flash memory write protected");
532 /* Clear but report errors */
533 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
534 retval = ERROR_FLASH_OPERATION_FAILED;
535 break;
536 }
537
538 buffer += thisrun_count * 2;
539 address += thisrun_count * 2;
540 count -= thisrun_count;
541 }
542
543 target_free_working_area(target, source);
544 target_free_working_area(target, stm32x_info->write_algorithm);
545
546 destroy_reg_param(&reg_params[0]);
547 destroy_reg_param(&reg_params[1]);
548 destroy_reg_param(&reg_params[2]);
549 destroy_reg_param(&reg_params[3]);
550
551 return retval;
552 }
553
554 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
555 {
556 struct target *target = bank->target;
557 uint32_t words_remaining = (count / 2);
558 uint32_t bytes_remaining = (count & 0x00000001);
559 uint32_t address = bank->base + offset;
560 uint32_t bytes_written = 0;
561 uint8_t status;
562 int retval;
563
564 if (bank->target->state != TARGET_HALTED)
565 {
566 LOG_ERROR("Target not halted");
567 return ERROR_TARGET_NOT_HALTED;
568 }
569
570 if (offset & 0x1)
571 {
572 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
573 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
574 }
575
576 /* unlock flash registers */
577 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
578 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
579
580 /* multiple half words (2-byte) to be programmed? */
581 if (words_remaining > 0)
582 {
583 /* try using a block write */
584 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
585 {
586 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
587 {
588 /* if block write failed (no sufficient working area),
589 * we use normal (slow) single dword accesses */
590 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
591 }
592 else if (retval == ERROR_FLASH_OPERATION_FAILED)
593 {
594 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
595 return ERROR_FLASH_OPERATION_FAILED;
596 }
597 }
598 else
599 {
600 buffer += words_remaining * 2;
601 address += words_remaining * 2;
602 words_remaining = 0;
603 }
604 }
605
606 while (words_remaining > 0)
607 {
608 uint16_t value;
609 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
610
611 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
612 target_write_u16(target, address, value);
613
614 status = stm32x_wait_status_busy(bank, 5);
615
616 if (status & FLASH_WRPRTERR)
617 {
618 LOG_ERROR("flash memory not erased before writing");
619 return ERROR_FLASH_OPERATION_FAILED;
620 }
621 if (status & FLASH_PGERR)
622 {
623 LOG_ERROR("flash memory write protected");
624 return ERROR_FLASH_OPERATION_FAILED;
625 }
626
627 bytes_written += 2;
628 words_remaining--;
629 address += 2;
630 }
631
632 if (bytes_remaining)
633 {
634 uint16_t value = 0xffff;
635 memcpy(&value, buffer + bytes_written, bytes_remaining);
636
637 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
638 target_write_u16(target, address, value);
639
640 status = stm32x_wait_status_busy(bank, 5);
641
642 if (status & FLASH_WRPRTERR)
643 {
644 LOG_ERROR("flash memory not erased before writing");
645 return ERROR_FLASH_OPERATION_FAILED;
646 }
647 if (status & FLASH_PGERR)
648 {
649 LOG_ERROR("flash memory write protected");
650 return ERROR_FLASH_OPERATION_FAILED;
651 }
652 }
653
654 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
655
656 return ERROR_OK;
657 }
658
659 static int stm32x_probe(struct flash_bank *bank)
660 {
661 struct target *target = bank->target;
662 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
663 int i;
664 uint16_t num_pages;
665 uint32_t device_id;
666 int page_size;
667
668 if (bank->target->state != TARGET_HALTED)
669 {
670 LOG_ERROR("Target not halted");
671 return ERROR_TARGET_NOT_HALTED;
672 }
673
674 stm32x_info->probed = 0;
675
676 /* read stm32 device id register */
677 target_read_u32(target, 0xE0042000, &device_id);
678 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
679
680 /* get flash size from target */
681 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
682 {
683 /* failed reading flash size, default to max target family */
684 num_pages = 0xffff;
685 }
686
687 if ((device_id & 0x7ff) == 0x410)
688 {
689 /* medium density - we have 1k pages
690 * 4 pages for a protection area */
691 page_size = 1024;
692 stm32x_info->ppage_size = 4;
693
694 /* check for early silicon */
695 if (num_pages == 0xffff)
696 {
697 /* number of sectors incorrect on revA */
698 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
699 num_pages = 128;
700 }
701 }
702 else if ((device_id & 0x7ff) == 0x412)
703 {
704 /* low density - we have 1k pages
705 * 4 pages for a protection area */
706 page_size = 1024;
707 stm32x_info->ppage_size = 4;
708
709 /* check for early silicon */
710 if (num_pages == 0xffff)
711 {
712 /* number of sectors incorrect on revA */
713 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
714 num_pages = 32;
715 }
716 }
717 else if ((device_id & 0x7ff) == 0x414)
718 {
719 /* high density - we have 2k pages
720 * 2 pages for a protection area */
721 page_size = 2048;
722 stm32x_info->ppage_size = 2;
723
724 /* check for early silicon */
725 if (num_pages == 0xffff)
726 {
727 /* number of sectors incorrect on revZ */
728 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
729 num_pages = 512;
730 }
731 }
732 else if ((device_id & 0x7ff) == 0x418)
733 {
734 /* connectivity line density - we have 2k pages
735 * 2 pages for a protection area */
736 page_size = 2048;
737 stm32x_info->ppage_size = 2;
738
739 /* check for early silicon */
740 if (num_pages == 0xffff)
741 {
742 /* number of sectors incorrect on revZ */
743 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
744 num_pages = 256;
745 }
746 }
747 else
748 {
749 LOG_WARNING("Cannot identify target as a STM32 family.");
750 return ERROR_FLASH_OPERATION_FAILED;
751 }
752
753 LOG_INFO("flash size = %dkbytes", num_pages);
754
755 /* calculate numbers of pages */
756 num_pages /= (page_size / 1024);
757
758 bank->base = 0x08000000;
759 bank->size = (num_pages * page_size);
760 bank->num_sectors = num_pages;
761 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
762
763 for (i = 0; i < num_pages; i++)
764 {
765 bank->sectors[i].offset = i * page_size;
766 bank->sectors[i].size = page_size;
767 bank->sectors[i].is_erased = -1;
768 bank->sectors[i].is_protected = 1;
769 }
770
771 stm32x_info->probed = 1;
772
773 return ERROR_OK;
774 }
775
776 static int stm32x_auto_probe(struct flash_bank *bank)
777 {
778 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
779 if (stm32x_info->probed)
780 return ERROR_OK;
781 return stm32x_probe(bank);
782 }
783
784 #if 0
785 COMMAND_HANDLER(stm32x_handle_part_id_command)
786 {
787 return ERROR_OK;
788 }
789 #endif
790
791 static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
792 {
793 struct target *target = bank->target;
794 uint32_t device_id;
795 int printed;
796
797 /* read stm32 device id register */
798 target_read_u32(target, 0xE0042000, &device_id);
799
800 if ((device_id & 0x7ff) == 0x410)
801 {
802 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
803 buf += printed;
804 buf_size -= printed;
805
806 switch (device_id >> 16)
807 {
808 case 0x0000:
809 snprintf(buf, buf_size, "A");
810 break;
811
812 case 0x2000:
813 snprintf(buf, buf_size, "B");
814 break;
815
816 case 0x2001:
817 snprintf(buf, buf_size, "Z");
818 break;
819
820 case 0x2003:
821 snprintf(buf, buf_size, "Y");
822 break;
823
824 default:
825 snprintf(buf, buf_size, "unknown");
826 break;
827 }
828 }
829 else if ((device_id & 0x7ff) == 0x412)
830 {
831 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
832 buf += printed;
833 buf_size -= printed;
834
835 switch (device_id >> 16)
836 {
837 case 0x1000:
838 snprintf(buf, buf_size, "A");
839 break;
840
841 default:
842 snprintf(buf, buf_size, "unknown");
843 break;
844 }
845 }
846 else if ((device_id & 0x7ff) == 0x414)
847 {
848 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
849 buf += printed;
850 buf_size -= printed;
851
852 switch (device_id >> 16)
853 {
854 case 0x1000:
855 snprintf(buf, buf_size, "A");
856 break;
857
858 case 0x1001:
859 snprintf(buf, buf_size, "Z");
860 break;
861
862 default:
863 snprintf(buf, buf_size, "unknown");
864 break;
865 }
866 }
867 else if ((device_id & 0x7ff) == 0x418)
868 {
869 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
870 buf += printed;
871 buf_size -= printed;
872
873 switch (device_id >> 16)
874 {
875 case 0x1000:
876 snprintf(buf, buf_size, "A");
877 break;
878
879 case 0x1001:
880 snprintf(buf, buf_size, "Z");
881 break;
882
883 default:
884 snprintf(buf, buf_size, "unknown");
885 break;
886 }
887 }
888 else
889 {
890 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
891 return ERROR_FLASH_OPERATION_FAILED;
892 }
893
894 return ERROR_OK;
895 }
896
897 COMMAND_HANDLER(stm32x_handle_lock_command)
898 {
899 struct target *target = NULL;
900 struct stm32x_flash_bank *stm32x_info = NULL;
901
902 if (CMD_ARGC < 1)
903 {
904 command_print(CMD_CTX, "stm32x lock <bank>");
905 return ERROR_OK;
906 }
907
908 struct flash_bank *bank;
909 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
910 if (ERROR_OK != retval)
911 return retval;
912
913 stm32x_info = bank->driver_priv;
914
915 target = bank->target;
916
917 if (target->state != TARGET_HALTED)
918 {
919 LOG_ERROR("Target not halted");
920 return ERROR_TARGET_NOT_HALTED;
921 }
922
923 if (stm32x_erase_options(bank) != ERROR_OK)
924 {
925 command_print(CMD_CTX, "stm32x failed to erase options");
926 return ERROR_OK;
927 }
928
929 /* set readout protection */
930 stm32x_info->option_bytes.RDP = 0;
931
932 if (stm32x_write_options(bank) != ERROR_OK)
933 {
934 command_print(CMD_CTX, "stm32x failed to lock device");
935 return ERROR_OK;
936 }
937
938 command_print(CMD_CTX, "stm32x locked");
939
940 return ERROR_OK;
941 }
942
943 COMMAND_HANDLER(stm32x_handle_unlock_command)
944 {
945 struct target *target = NULL;
946 struct stm32x_flash_bank *stm32x_info = NULL;
947
948 if (CMD_ARGC < 1)
949 {
950 command_print(CMD_CTX, "stm32x unlock <bank>");
951 return ERROR_OK;
952 }
953
954 struct flash_bank *bank;
955 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
956 if (ERROR_OK != retval)
957 return retval;
958
959 stm32x_info = bank->driver_priv;
960
961 target = bank->target;
962
963 if (target->state != TARGET_HALTED)
964 {
965 LOG_ERROR("Target not halted");
966 return ERROR_TARGET_NOT_HALTED;
967 }
968
969 if (stm32x_erase_options(bank) != ERROR_OK)
970 {
971 command_print(CMD_CTX, "stm32x failed to unlock device");
972 return ERROR_OK;
973 }
974
975 if (stm32x_write_options(bank) != ERROR_OK)
976 {
977 command_print(CMD_CTX, "stm32x failed to lock device");
978 return ERROR_OK;
979 }
980
981 command_print(CMD_CTX, "stm32x unlocked");
982
983 return ERROR_OK;
984 }
985
986 COMMAND_HANDLER(stm32x_handle_options_read_command)
987 {
988 uint32_t optionbyte;
989 struct target *target = NULL;
990 struct stm32x_flash_bank *stm32x_info = NULL;
991
992 if (CMD_ARGC < 1)
993 {
994 command_print(CMD_CTX, "stm32x options_read <bank>");
995 return ERROR_OK;
996 }
997
998 struct flash_bank *bank;
999 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1000 if (ERROR_OK != retval)
1001 return retval;
1002
1003 stm32x_info = bank->driver_priv;
1004
1005 target = bank->target;
1006
1007 if (target->state != TARGET_HALTED)
1008 {
1009 LOG_ERROR("Target not halted");
1010 return ERROR_TARGET_NOT_HALTED;
1011 }
1012
1013 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1014 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1015
1016 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1017 command_print(CMD_CTX, "Option Byte Complement Error");
1018
1019 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1020 command_print(CMD_CTX, "Readout Protection On");
1021 else
1022 command_print(CMD_CTX, "Readout Protection Off");
1023
1024 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1025 command_print(CMD_CTX, "Software Watchdog");
1026 else
1027 command_print(CMD_CTX, "Hardware Watchdog");
1028
1029 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1030 command_print(CMD_CTX, "Stop: No reset generated");
1031 else
1032 command_print(CMD_CTX, "Stop: Reset generated");
1033
1034 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1035 command_print(CMD_CTX, "Standby: No reset generated");
1036 else
1037 command_print(CMD_CTX, "Standby: Reset generated");
1038
1039 return ERROR_OK;
1040 }
1041
1042 COMMAND_HANDLER(stm32x_handle_options_write_command)
1043 {
1044 struct target *target = NULL;
1045 struct stm32x_flash_bank *stm32x_info = NULL;
1046 uint16_t optionbyte = 0xF8;
1047
1048 if (CMD_ARGC < 4)
1049 {
1050 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1051 return ERROR_OK;
1052 }
1053
1054 struct flash_bank *bank;
1055 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1056 if (ERROR_OK != retval)
1057 return retval;
1058
1059 stm32x_info = bank->driver_priv;
1060
1061 target = bank->target;
1062
1063 if (target->state != TARGET_HALTED)
1064 {
1065 LOG_ERROR("Target not halted");
1066 return ERROR_TARGET_NOT_HALTED;
1067 }
1068
1069 /* REVISIT: ignores some options which we will display...
1070 * and doesn't insist on the specified syntax.
1071 */
1072
1073 /* OPT_RDWDGSW */
1074 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1075 {
1076 optionbyte |= (1 << 0);
1077 }
1078 else /* REVISIT must be "HWWDG" then ... */
1079 {
1080 optionbyte &= ~(1 << 0);
1081 }
1082
1083 /* OPT_RDRSTSTDBY */
1084 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1085 {
1086 optionbyte |= (1 << 1);
1087 }
1088 else /* REVISIT must be "RSTSTNDBY" then ... */
1089 {
1090 optionbyte &= ~(1 << 1);
1091 }
1092
1093 /* OPT_RDRSTSTOP */
1094 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1095 {
1096 optionbyte |= (1 << 2);
1097 }
1098 else /* REVISIT must be "RSTSTOP" then ... */
1099 {
1100 optionbyte &= ~(1 << 2);
1101 }
1102
1103 if (stm32x_erase_options(bank) != ERROR_OK)
1104 {
1105 command_print(CMD_CTX, "stm32x failed to erase options");
1106 return ERROR_OK;
1107 }
1108
1109 stm32x_info->option_bytes.user_options = optionbyte;
1110
1111 if (stm32x_write_options(bank) != ERROR_OK)
1112 {
1113 command_print(CMD_CTX, "stm32x failed to write options");
1114 return ERROR_OK;
1115 }
1116
1117 command_print(CMD_CTX, "stm32x write options complete");
1118
1119 return ERROR_OK;
1120 }
1121
1122 static int stm32x_mass_erase(struct flash_bank *bank)
1123 {
1124 struct target *target = bank->target;
1125 uint32_t status;
1126
1127 if (target->state != TARGET_HALTED)
1128 {
1129 LOG_ERROR("Target not halted");
1130 return ERROR_TARGET_NOT_HALTED;
1131 }
1132
1133 /* unlock option flash registers */
1134 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1135 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1136
1137 /* mass erase flash memory */
1138 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1139 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1140
1141 status = stm32x_wait_status_busy(bank, 10);
1142
1143 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1144
1145 if (status & FLASH_WRPRTERR)
1146 {
1147 LOG_ERROR("stm32x device protected");
1148 return ERROR_OK;
1149 }
1150
1151 if (status & FLASH_PGERR)
1152 {
1153 LOG_ERROR("stm32x device programming failed");
1154 return ERROR_OK;
1155 }
1156
1157 return ERROR_OK;
1158 }
1159
1160 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1161 {
1162 int i;
1163
1164 if (CMD_ARGC < 1)
1165 {
1166 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1167 return ERROR_OK;
1168 }
1169
1170 struct flash_bank *bank;
1171 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1172 if (ERROR_OK != retval)
1173 return retval;
1174
1175 if (stm32x_mass_erase(bank) == ERROR_OK)
1176 {
1177 /* set all sectors as erased */
1178 for (i = 0; i < bank->num_sectors; i++)
1179 {
1180 bank->sectors[i].is_erased = 1;
1181 }
1182
1183 command_print(CMD_CTX, "stm32x mass erase complete");
1184 }
1185 else
1186 {
1187 command_print(CMD_CTX, "stm32x mass erase failed");
1188 }
1189
1190 return ERROR_OK;
1191 }
1192
1193 static const struct command_registration stm32x_exec_command_handlers[] = {
1194 {
1195 .name = "lock",
1196 .handler = stm32x_handle_lock_command,
1197 .mode = COMMAND_EXEC,
1198 .usage = "bank_id",
1199 .help = "Lock entire flash device.",
1200 },
1201 {
1202 .name = "unlock",
1203 .handler = stm32x_handle_unlock_command,
1204 .mode = COMMAND_EXEC,
1205 .usage = "bank_id",
1206 .help = "Unlock entire protected flash device.",
1207 },
1208 {
1209 .name = "mass_erase",
1210 .handler = stm32x_handle_mass_erase_command,
1211 .mode = COMMAND_EXEC,
1212 .usage = "bank_id",
1213 .help = "Erase entire flash device.",
1214 },
1215 {
1216 .name = "options_read",
1217 .handler = stm32x_handle_options_read_command,
1218 .mode = COMMAND_EXEC,
1219 .usage = "bank_id",
1220 .help = "Read and display device option byte.",
1221 },
1222 {
1223 .name = "options_write",
1224 .handler = stm32x_handle_options_write_command,
1225 .mode = COMMAND_EXEC,
1226 .usage = "bank_id ('SWWDG'|'HWWDG') "
1227 "('RSTSTNDBY'|'NORSTSTNDBY') "
1228 "('RSTSTOP'|'NORSTSTOP')",
1229 .help = "Replace bits in device option byte.",
1230 },
1231 COMMAND_REGISTRATION_DONE
1232 };
1233 static const struct command_registration stm32x_command_handlers[] = {
1234 {
1235 .name = "stm32x",
1236 .mode = COMMAND_ANY,
1237 .help = "stm32x flash command group",
1238 .chain = stm32x_exec_command_handlers,
1239 },
1240 COMMAND_REGISTRATION_DONE
1241 };
1242
1243 struct flash_driver stm32x_flash = {
1244 .name = "stm32x",
1245 .commands = stm32x_command_handlers,
1246 .flash_bank_command = stm32x_flash_bank_command,
1247 .erase = stm32x_erase,
1248 .protect = stm32x_protect,
1249 .write = stm32x_write,
1250 .probe = stm32x_probe,
1251 .auto_probe = stm32x_auto_probe,
1252 .erase_check = default_flash_mem_blank_check,
1253 .protect_check = stm32x_protect_check,
1254 .info = stm32x_info,
1255 };
Official OpenOCD Mirror