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topic: STM32W support added to em357 driver
[openocd.git] / src / flash / nor / em357.c
blob664306ca5f4017be94dbc18c0d49b8902bac2260
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 *
8 * Copyright (C) 2011 by Erik Botö
9 * erik.boto@pelagicore.com
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* em357 register locations */
37
38 #define EM357_FLASH_ACR 0x40008000
39 #define EM357_FLASH_KEYR 0x40008004
40 #define EM357_FLASH_OPTKEYR 0x40008008
41 #define EM357_FLASH_SR 0x4000800C
42 #define EM357_FLASH_CR 0x40008010
43 #define EM357_FLASH_AR 0x40008014
44 #define EM357_FLASH_OBR 0x4000801C
45 #define EM357_FLASH_WRPR 0x40008020
46
47 #define EM357_FPEC_CLK 0x4000402c
48 /* option byte location */
49
50 #define EM357_OB_RDP 0x08040800
51 #define EM357_OB_WRP0 0x08040808
52 #define EM357_OB_WRP1 0x0804080A
53 #define EM357_OB_WRP2 0x0804080C
54
55 /* FLASH_CR register bits */
56
57 #define FLASH_PG (1 << 0)
58 #define FLASH_PER (1 << 1)
59 #define FLASH_MER (1 << 2)
60 #define FLASH_OPTPG (1 << 4)
61 #define FLASH_OPTER (1 << 5)
62 #define FLASH_STRT (1 << 6)
63 #define FLASH_LOCK (1 << 7)
64 #define FLASH_OPTWRE (1 << 9)
65
66 /* FLASH_SR register bits */
67
68 #define FLASH_BSY (1 << 0)
69 #define FLASH_PGERR (1 << 2)
70 #define FLASH_WRPRTERR (1 << 4)
71 #define FLASH_EOP (1 << 5)
72
73 /* EM357_FLASH_OBR bit definitions (reading) */
74
75 #define OPT_ERROR 0
76 #define OPT_READOUT 1
77
78 /* register unlock keys */
79
80 #define KEY1 0x45670123
81 #define KEY2 0xCDEF89AB
82
83 struct em357_options {
84 uint16_t RDP;
85 uint16_t user_options;
86 uint16_t protection[3];
87 };
88
89 struct em357_flash_bank {
90 struct em357_options option_bytes;
91 int ppage_size;
92 int probed;
93 };
94
95 static int em357_mass_erase(struct flash_bank *bank);
96
97 /* flash bank em357 <base> <size> 0 0 <target#>
98 */
99 FLASH_BANK_COMMAND_HANDLER(em357_flash_bank_command)
100 {
101 struct em357_flash_bank *em357_info;
102
103 if (CMD_ARGC < 6)
104 return ERROR_COMMAND_SYNTAX_ERROR;
105
106 em357_info = malloc(sizeof(struct em357_flash_bank));
107 bank->driver_priv = em357_info;
108
109 em357_info->probed = 0;
110
111 return ERROR_OK;
112 }
113
114 static inline int em357_get_flash_status(struct flash_bank *bank, uint32_t *status)
115 {
116 struct target *target = bank->target;
117 return target_read_u32(target, EM357_FLASH_SR, status);
118 }
119
120 static int em357_wait_status_busy(struct flash_bank *bank, int timeout)
121 {
122 struct target *target = bank->target;
123 uint32_t status;
124 int retval = ERROR_OK;
125
126 /* wait for busy to clear */
127 for (;; ) {
128 retval = em357_get_flash_status(bank, &status);
129 if (retval != ERROR_OK)
130 return retval;
131 LOG_DEBUG("status: 0x%" PRIx32 "", status);
132 if ((status & FLASH_BSY) == 0)
133 break;
134 if (timeout-- <= 0) {
135 LOG_ERROR("timed out waiting for flash");
136 return ERROR_FAIL;
137 }
138 alive_sleep(1);
139 }
140
141 if (status & FLASH_WRPRTERR) {
142 LOG_ERROR("em357 device protected");
143 retval = ERROR_FAIL;
144 }
145
146 if (status & FLASH_PGERR) {
147 LOG_ERROR("em357 device programming failed");
148 retval = ERROR_FAIL;
149 }
150
151 /* Clear but report errors */
152 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
153 /* If this operation fails, we ignore it and report the original
154 * retval
155 */
156 target_write_u32(target, EM357_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
157 }
158 return retval;
159 }
160
161 static int em357_read_options(struct flash_bank *bank)
162 {
163 uint32_t optiondata;
164 struct em357_flash_bank *em357_info = NULL;
165 struct target *target = bank->target;
166
167 em357_info = bank->driver_priv;
168
169 /* read current option bytes */
170 int retval = target_read_u32(target, EM357_FLASH_OBR, &optiondata);
171 if (retval != ERROR_OK)
172 return retval;
173
174 em357_info->option_bytes.user_options = (uint16_t)0xFFFC | ((optiondata >> 2) & 0x03);
175 em357_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
176
177 if (optiondata & (1 << OPT_READOUT))
178 LOG_INFO("Device Security Bit Set");
179
180 /* each bit refers to a 4bank protection */
181 retval = target_read_u32(target, EM357_FLASH_WRPR, &optiondata);
182 if (retval != ERROR_OK)
183 return retval;
184
185 em357_info->option_bytes.protection[0] = (uint16_t)optiondata;
186 em357_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
187 em357_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
188
189 return ERROR_OK;
190 }
191
192 static int em357_erase_options(struct flash_bank *bank)
193 {
194 struct em357_flash_bank *em357_info = NULL;
195 struct target *target = bank->target;
196
197 em357_info = bank->driver_priv;
198
199 /* read current options */
200 em357_read_options(bank);
201
202 /* unlock flash registers */
203 int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
204 if (retval != ERROR_OK)
205 return retval;
206
207 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
208 if (retval != ERROR_OK)
209 return retval;
210
211 /* unlock option flash registers */
212 retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY1);
213 if (retval != ERROR_OK)
214 return retval;
215 retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY2);
216 if (retval != ERROR_OK)
217 return retval;
218
219 /* erase option bytes */
220 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
221 if (retval != ERROR_OK)
222 return retval;
223 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
224 if (retval != ERROR_OK)
225 return retval;
226
227 retval = em357_wait_status_busy(bank, 10);
228 if (retval != ERROR_OK)
229 return retval;
230
231 /* clear readout protection and complementary option bytes
232 * this will also force a device unlock if set */
233 em357_info->option_bytes.RDP = 0x5AA5;
234
235 return ERROR_OK;
236 }
237
238 static int em357_write_options(struct flash_bank *bank)
239 {
240 struct em357_flash_bank *em357_info = NULL;
241 struct target *target = bank->target;
242
243 em357_info = bank->driver_priv;
244
245 /* unlock flash registers */
246 int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
247 if (retval != ERROR_OK)
248 return retval;
249 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
250 if (retval != ERROR_OK)
251 return retval;
252
253 /* unlock option flash registers */
254 retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY1);
255 if (retval != ERROR_OK)
256 return retval;
257 retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY2);
258 if (retval != ERROR_OK)
259 return retval;
260
261 /* program option bytes */
262 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
263 if (retval != ERROR_OK)
264 return retval;
265
266 retval = em357_wait_status_busy(bank, 10);
267 if (retval != ERROR_OK)
268 return retval;
269
270 /* write protection byte 1 */
271 retval = target_write_u16(target, EM357_OB_WRP0, em357_info->option_bytes.protection[0]);
272 if (retval != ERROR_OK)
273 return retval;
274
275 retval = em357_wait_status_busy(bank, 10);
276 if (retval != ERROR_OK)
277 return retval;
278
279 /* write protection byte 2 */
280 retval = target_write_u16(target, EM357_OB_WRP1, em357_info->option_bytes.protection[1]);
281 if (retval != ERROR_OK)
282 return retval;
283
284 retval = em357_wait_status_busy(bank, 10);
285 if (retval != ERROR_OK)
286 return retval;
287
288 /* write protection byte 3 */
289 retval = target_write_u16(target, EM357_OB_WRP2, em357_info->option_bytes.protection[2]);
290 if (retval != ERROR_OK)
291 return retval;
292
293 retval = em357_wait_status_busy(bank, 10);
294 if (retval != ERROR_OK)
295 return retval;
296
297 /* write readout protection bit */
298 retval = target_write_u16(target, EM357_OB_RDP, em357_info->option_bytes.RDP);
299 if (retval != ERROR_OK)
300 return retval;
301
302 retval = em357_wait_status_busy(bank, 10);
303 if (retval != ERROR_OK)
304 return retval;
305
306 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
307 if (retval != ERROR_OK)
308 return retval;
309
310 return ERROR_OK;
311 }
312
313 static int em357_protect_check(struct flash_bank *bank)
314 {
315 struct target *target = bank->target;
316 struct em357_flash_bank *em357_info = bank->driver_priv;
317
318 uint32_t protection;
319 int i, s;
320 int num_bits;
321 int set;
322
323 if (target->state != TARGET_HALTED) {
324 LOG_ERROR("Target not halted");
325 return ERROR_TARGET_NOT_HALTED;
326 }
327
328 /* each bit refers to a 4bank protection (bit 0-23) */
329 int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
330 if (retval != ERROR_OK)
331 return retval;
332
333 /* each protection bit is for 4 * 2K pages */
334 num_bits = (bank->num_sectors / em357_info->ppage_size);
335
336 for (i = 0; i < num_bits; i++) {
337 set = 1;
338 if (protection & (1 << i))
339 set = 0;
340
341 for (s = 0; s < em357_info->ppage_size; s++)
342 bank->sectors[(i * em357_info->ppage_size) + s].is_protected = set;
343 }
344
345 return ERROR_OK;
346 }
347
348 static int em357_erase(struct flash_bank *bank, int first, int last)
349 {
350 struct target *target = bank->target;
351 int i;
352
353 if (bank->target->state != TARGET_HALTED) {
354 LOG_ERROR("Target not halted");
355 return ERROR_TARGET_NOT_HALTED;
356 }
357
358 if ((first == 0) && (last == (bank->num_sectors - 1)))
359 return em357_mass_erase(bank);
360
361 /* Enable FPEC clock */
362 target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
363
364 /* unlock flash registers */
365 int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
366 if (retval != ERROR_OK)
367 return retval;
368 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
369 if (retval != ERROR_OK)
370 return retval;
371
372 for (i = first; i <= last; i++) {
373 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PER);
374 if (retval != ERROR_OK)
375 return retval;
376 retval = target_write_u32(target, EM357_FLASH_AR,
377 bank->base + bank->sectors[i].offset);
378 if (retval != ERROR_OK)
379 return retval;
380 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PER | FLASH_STRT);
381 if (retval != ERROR_OK)
382 return retval;
383
384 retval = em357_wait_status_busy(bank, 100);
385 if (retval != ERROR_OK)
386 return retval;
387
388 bank->sectors[i].is_erased = 1;
389 }
390
391 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
392 if (retval != ERROR_OK)
393 return retval;
394
395 return ERROR_OK;
396 }
397
398 static int em357_protect(struct flash_bank *bank, int set, int first, int last)
399 {
400 struct em357_flash_bank *em357_info = NULL;
401 struct target *target = bank->target;
402 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
403 int i, reg, bit;
404 int status;
405 uint32_t protection;
406
407 em357_info = bank->driver_priv;
408
409 if (target->state != TARGET_HALTED) {
410 LOG_ERROR("Target not halted");
411 return ERROR_TARGET_NOT_HALTED;
412 }
413
414 if ((first % em357_info->ppage_size) != 0) {
415 LOG_WARNING("aligned start protect sector to a %d sector boundary",
416 em357_info->ppage_size);
417 first = first - (first % em357_info->ppage_size);
418 }
419 if (((last + 1) % em357_info->ppage_size) != 0) {
420 LOG_WARNING("aligned end protect sector to a %d sector boundary",
421 em357_info->ppage_size);
422 last++;
423 last = last - (last % em357_info->ppage_size);
424 last--;
425 }
426
427 /* each bit refers to a 4bank protection */
428 int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
429 if (retval != ERROR_OK)
430 return retval;
431
432 prot_reg[0] = (uint16_t)protection;
433 prot_reg[1] = (uint16_t)(protection >> 8);
434 prot_reg[2] = (uint16_t)(protection >> 16);
435
436 for (i = first; i <= last; i++) {
437 reg = (i / em357_info->ppage_size) / 8;
438 bit = (i / em357_info->ppage_size) - (reg * 8);
439
440 LOG_WARNING("reg, bit: %d, %d", reg, bit);
441 if (set)
442 prot_reg[reg] &= ~(1 << bit);
443 else
444 prot_reg[reg] |= (1 << bit);
445 }
446
447 status = em357_erase_options(bank);
448 if (retval != ERROR_OK)
449 return status;
450
451 em357_info->option_bytes.protection[0] = prot_reg[0];
452 em357_info->option_bytes.protection[1] = prot_reg[1];
453 em357_info->option_bytes.protection[2] = prot_reg[2];
454
455 return em357_write_options(bank);
456 }
457
458 static int em357_write_block(struct flash_bank *bank, uint8_t *buffer,
459 uint32_t offset, uint32_t count)
460 {
461 struct target *target = bank->target;
462 uint32_t buffer_size = 16384;
463 struct working_area *write_algorithm;
464 struct working_area *source;
465 uint32_t address = bank->base + offset;
466 struct reg_param reg_params[4];
467 struct armv7m_algorithm armv7m_info;
468 int retval = ERROR_OK;
469
470 /* see contib/loaders/flash/stm32x.s for src, the same is used here except for
471 * a modified *_FLASH_BASE */
472
473 static const uint8_t em357_flash_write_code[] = {
474 /* #define EM357_FLASH_CR_OFFSET 0x10
475 * #define EM357_FLASH_SR_OFFSET 0x0C
476 * write: */
477 0x08, 0x4c, /* ldr r4, EM357_FLASH_BASE */
478 0x1c, 0x44, /* add r4, r3 */
479 /* write_half_word: */
480 0x01, 0x23, /* movs r3, #0x01 */
481 0x23, 0x61, /* str r3, [r4,
482 *#EM357_FLASH_CR_OFFSET] */
483 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
484 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
485 /* busy: */
486 0xe3, 0x68, /* ldr r3, [r4,
487 *#EM357_FLASH_SR_OFFSET] */
488 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
489 0xfb, 0xd0, /* beq busy */
490 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
491 0x01, 0xd1, /* bne exit */
492 0x01, 0x3a, /* subs r2, r2, #0x01 */
493 0xf0, 0xd1, /* bne write_half_word */
494 /* exit: */
495 0x00, 0xbe, /* bkpt #0x00 */
496 0x00, 0x80, 0x00, 0x40, /* EM357_FLASH_BASE: .word 0x40008000 */
497 };
498
499 /* flash write code */
500 if (target_alloc_working_area(target, sizeof(em357_flash_write_code),
501 &write_algorithm) != ERROR_OK) {
502 LOG_WARNING("no working area available, can't do block memory writes");
503 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
504 }
505 ;
506
507 retval = target_write_buffer(target, write_algorithm->address,
508 sizeof(em357_flash_write_code), (uint8_t *)em357_flash_write_code);
509 if (retval != ERROR_OK)
510 return retval;
511
512 /* memory buffer */
513 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
514 buffer_size /= 2;
515 if (buffer_size <= 256) {
516 /* we already allocated the writing code, but failed to get a
517 * buffer, free the algorithm */
518 target_free_working_area(target, write_algorithm);
519
520 LOG_WARNING(
521 "no large enough working area available, can't do block memory writes");
522 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
523 }
524 }
525
526 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
527 armv7m_info.core_mode = ARM_MODE_THREAD;
528
529 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
530 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
531 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
532 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
533
534 while (count > 0) {
535 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
536 (buffer_size / 2) : count;
537
538 retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer);
539 if (retval != ERROR_OK)
540 break;
541
542 buf_set_u32(reg_params[0].value, 0, 32, source->address);
543 buf_set_u32(reg_params[1].value, 0, 32, address);
544 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
545 buf_set_u32(reg_params[3].value, 0, 32, 0);
546
547 retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
548 write_algorithm->address, 0, 10000, &armv7m_info);
549 if (retval != ERROR_OK) {
550 LOG_ERROR("error executing em357 flash write algorithm");
551 break;
552 }
553
554 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR) {
555 LOG_ERROR("flash memory not erased before writing");
556 /* Clear but report errors */
557 target_write_u32(target, EM357_FLASH_SR, FLASH_PGERR);
558 retval = ERROR_FAIL;
559 break;
560 }
561
562 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR) {
563 LOG_ERROR("flash memory write protected");
564 /* Clear but report errors */
565 target_write_u32(target, EM357_FLASH_SR, FLASH_WRPRTERR);
566 retval = ERROR_FAIL;
567 break;
568 }
569
570 buffer += thisrun_count * 2;
571 address += thisrun_count * 2;
572 count -= thisrun_count;
573 }
574
575 target_free_working_area(target, source);
576 target_free_working_area(target, write_algorithm);
577
578 destroy_reg_param(&reg_params[0]);
579 destroy_reg_param(&reg_params[1]);
580 destroy_reg_param(&reg_params[2]);
581 destroy_reg_param(&reg_params[3]);
582
583 return retval;
584 }
585
586 static int em357_write(struct flash_bank *bank, uint8_t *buffer,
587 uint32_t offset, uint32_t count)
588 {
589 struct target *target = bank->target;
590 uint32_t words_remaining = (count / 2);
591 uint32_t bytes_remaining = (count & 0x00000001);
592 uint32_t address = bank->base + offset;
593 uint32_t bytes_written = 0;
594 int retval;
595
596 if (bank->target->state != TARGET_HALTED) {
597 LOG_ERROR("Target not halted");
598 return ERROR_TARGET_NOT_HALTED;
599 }
600
601 if (offset & 0x1) {
602 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
603 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
604 }
605
606 /* unlock flash registers */
607 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
608 if (retval != ERROR_OK)
609 return retval;
610 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
611 if (retval != ERROR_OK)
612 return retval;
613
614 target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
615
616 /* multiple half words (2-byte) to be programmed? */
617 if (words_remaining > 0) {
618 /* try using a block write */
619 retval = em357_write_block(bank, buffer, offset, words_remaining);
620 if (retval != ERROR_OK) {
621 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
622 /* if block write failed (no sufficient working area),
623 * we use normal (slow) single dword accesses */
624 LOG_WARNING(
625 "couldn't use block writes, falling back to single memory accesses");
626 }
627 } else {
628 buffer += words_remaining * 2;
629 address += words_remaining * 2;
630 words_remaining = 0;
631 }
632 }
633
634 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
635 return retval;
636
637 while (words_remaining > 0) {
638 uint16_t value;
639 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
640
641 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PG);
642 if (retval != ERROR_OK)
643 return retval;
644 retval = target_write_u16(target, address, value);
645 if (retval != ERROR_OK)
646 return retval;
647
648 retval = em357_wait_status_busy(bank, 5);
649 if (retval != ERROR_OK)
650 return retval;
651
652 bytes_written += 2;
653 words_remaining--;
654 address += 2;
655 }
656
657 if (bytes_remaining) {
658 uint16_t value = 0xffff;
659 memcpy(&value, buffer + bytes_written, bytes_remaining);
660
661 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PG);
662 if (retval != ERROR_OK)
663 return retval;
664 retval = target_write_u16(target, address, value);
665 if (retval != ERROR_OK)
666 return retval;
667
668 retval = em357_wait_status_busy(bank, 5);
669 if (retval != ERROR_OK)
670 return retval;
671 }
672
673 return target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
674 }
675
676 static int em357_probe(struct flash_bank *bank)
677 {
678 struct target *target = bank->target;
679 struct em357_flash_bank *em357_info = bank->driver_priv;
680 int i;
681 uint16_t num_pages;
682 int page_size;
683 uint32_t base_address = 0x08000000;
684
685 em357_info->probed = 0;
686
687 switch (bank->size) {
688 case 0x10000:
689 /* 64k -- 64 1k pages */
690 num_pages = 64;
691 page_size = 1024;
692 break;
693 case 0x20000:
694 /* 128k -- 128 1k pages */
695 num_pages = 128;
696 page_size = 1024;
697 break;
698 case 0x30000:
699 /* 192k -- 96 2k pages */
700 num_pages = 96;
701 page_size = 2048;
702 break;
703 case 0x40000:
704 /* 256k -- 128 2k pages */
705 num_pages = 128;
706 page_size = 2048;
707 break;
708 default:
709 LOG_WARNING("No size specified for em357 flash driver, assuming 192k!");
710 num_pages = 96;
711 page_size = 2048;
712 break;
713 }
714
715 /* Enable FPEC CLK */
716 int retval = target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
717 if (retval != ERROR_OK)
718 return retval;
719
720 em357_info->ppage_size = 4;
721
722 LOG_INFO("flash size = %dkbytes", num_pages*page_size/1024);
723
724 if (bank->sectors) {
725 free(bank->sectors);
726 bank->sectors = NULL;
727 }
728
729 bank->base = base_address;
730 bank->size = (num_pages * page_size);
731 bank->num_sectors = num_pages;
732 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
733
734 for (i = 0; i < num_pages; i++) {
735 bank->sectors[i].offset = i * page_size;
736 bank->sectors[i].size = page_size;
737 bank->sectors[i].is_erased = -1;
738 bank->sectors[i].is_protected = 1;
739 }
740
741 em357_info->probed = 1;
742
743 return ERROR_OK;
744 }
745
746 static int em357_auto_probe(struct flash_bank *bank)
747 {
748 struct em357_flash_bank *em357_info = bank->driver_priv;
749 if (em357_info->probed)
750 return ERROR_OK;
751 return em357_probe(bank);
752 }
753
754
755 static int get_em357_info(struct flash_bank *bank, char *buf, int buf_size)
756 {
757 snprintf(buf, buf_size, "em357\n");
758 return ERROR_OK;
759 }
760
761 COMMAND_HANDLER(em357_handle_lock_command)
762 {
763 struct target *target = NULL;
764 struct em357_flash_bank *em357_info = NULL;
765
766 if (CMD_ARGC < 1)
767 return ERROR_COMMAND_SYNTAX_ERROR;
768
769 struct flash_bank *bank;
770 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
771 if (ERROR_OK != retval)
772 return retval;
773
774 em357_info = bank->driver_priv;
775
776 target = bank->target;
777
778 if (target->state != TARGET_HALTED) {
779 LOG_ERROR("Target not halted");
780 return ERROR_TARGET_NOT_HALTED;
781 }
782
783 if (em357_erase_options(bank) != ERROR_OK) {
784 command_print(CMD_CTX, "em357 failed to erase options");
785 return ERROR_OK;
786 }
787
788 /* set readout protection */
789 em357_info->option_bytes.RDP = 0;
790
791 if (em357_write_options(bank) != ERROR_OK) {
792 command_print(CMD_CTX, "em357 failed to lock device");
793 return ERROR_OK;
794 }
795
796 command_print(CMD_CTX, "em357 locked");
797
798 return ERROR_OK;
799 }
800
801 COMMAND_HANDLER(em357_handle_unlock_command)
802 {
803 struct target *target = NULL;
804
805 if (CMD_ARGC < 1)
806 return ERROR_COMMAND_SYNTAX_ERROR;
807
808 struct flash_bank *bank;
809 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
810 if (ERROR_OK != retval)
811 return retval;
812
813 target = bank->target;
814
815 if (target->state != TARGET_HALTED) {
816 LOG_ERROR("Target not halted");
817 return ERROR_TARGET_NOT_HALTED;
818 }
819
820 if (em357_erase_options(bank) != ERROR_OK) {
821 command_print(CMD_CTX, "em357 failed to unlock device");
822 return ERROR_OK;
823 }
824
825 if (em357_write_options(bank) != ERROR_OK) {
826 command_print(CMD_CTX, "em357 failed to lock device");
827 return ERROR_OK;
828 }
829
830 command_print(CMD_CTX, "em357 unlocked.\n"
831 "INFO: a reset or power cycle is required "
832 "for the new settings to take effect.");
833
834 return ERROR_OK;
835 }
836
837 static int em357_mass_erase(struct flash_bank *bank)
838 {
839 struct target *target = bank->target;
840
841 if (target->state != TARGET_HALTED) {
842 LOG_ERROR("Target not halted");
843 return ERROR_TARGET_NOT_HALTED;
844 }
845
846 /* Make sure the flash clock is on */
847 target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
848
849 /* unlock option flash registers */
850 int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
851 if (retval != ERROR_OK)
852 return retval;
853 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
854 if (retval != ERROR_OK)
855 return retval;
856
857 /* mass erase flash memory */
858 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER);
859 if (retval != ERROR_OK)
860 return retval;
861 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER | FLASH_STRT);
862 if (retval != ERROR_OK)
863 return retval;
864
865 retval = em357_wait_status_busy(bank, 100);
866 if (retval != ERROR_OK)
867 return retval;
868
869 retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
870 if (retval != ERROR_OK)
871 return retval;
872
873 return ERROR_OK;
874 }
875
876 COMMAND_HANDLER(em357_handle_mass_erase_command)
877 {
878 int i;
879
880 if (CMD_ARGC < 1)
881 return ERROR_COMMAND_SYNTAX_ERROR;
882
883 struct flash_bank *bank;
884 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
885 if (ERROR_OK != retval)
886 return retval;
887
888 retval = em357_mass_erase(bank);
889 if (retval == ERROR_OK) {
890 /* set all sectors as erased */
891 for (i = 0; i < bank->num_sectors; i++)
892 bank->sectors[i].is_erased = 1;
893
894 command_print(CMD_CTX, "em357 mass erase complete");
895 } else
896 command_print(CMD_CTX, "em357 mass erase failed");
897
898 return retval;
899 }
900
901 static const struct command_registration em357_exec_command_handlers[] = {
902 {
903 .name = "lock",
904 .usage = "<bank>",
905 .handler = em357_handle_lock_command,
906 .mode = COMMAND_EXEC,
907 .help = "Lock entire flash device.",
908 },
909 {
910 .name = "unlock",
911 .usage = "<bank>",
912 .handler = em357_handle_unlock_command,
913 .mode = COMMAND_EXEC,
914 .help = "Unlock entire protected flash device.",
915 },
916 {
917 .name = "mass_erase",
918 .usage = "<bank>",
919 .handler = em357_handle_mass_erase_command,
920 .mode = COMMAND_EXEC,
921 .help = "Erase entire flash device.",
922 },
923 COMMAND_REGISTRATION_DONE
924 };
925
926 static const struct command_registration em357_command_handlers[] = {
927 {
928 .name = "em357",
929 .mode = COMMAND_ANY,
930 .help = "em357 flash command group",
931 .usage = "",
932 .chain = em357_exec_command_handlers,
933 },
934 COMMAND_REGISTRATION_DONE
935 };
936
937 struct flash_driver em357_flash = {
938 .name = "em357",
939 .commands = em357_command_handlers,
940 .flash_bank_command = em357_flash_bank_command,
941 .erase = em357_erase,
942 .protect = em357_protect,
943 .write = em357_write,
944 .read = default_flash_read,
945 .probe = em357_probe,
946 .auto_probe = em357_auto_probe,
947 .erase_check = default_flash_blank_check,
948 .protect_check = em357_protect_check,
949 .info = get_em357_info,
950 };
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