?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hla: Make consistent parameter naming
[openocd.git] / src / target / nds32_v3_common.c
blob531cab09452e0ecccfeed918c065e002418b41ca
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "breakpoints.h"
26 #include "nds32_reg.h"
27 #include "nds32_disassembler.h"
28 #include "nds32.h"
29 #include "nds32_aice.h"
30 #include "nds32_v3_common.h"
31
32 static struct nds32_v3_common_callback *v3_common_callback;
33
34 static int nds32_v3_register_mapping(struct nds32 *nds32, int reg_no)
35 {
36 if (reg_no == PC)
37 return IR11;
38
39 return reg_no;
40 }
41
42 static int nds32_v3_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
43 {
44 uint32_t edmsw;
45 struct aice_port_s *aice = target_to_aice(nds32->target);
46 aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
47
48 *reason = (edmsw >> 12) & 0x0F;
49
50 return ERROR_OK;
51 }
52
53 /**
54 * Save processor state. This is called after a HALT instruction
55 * succeeds, and on other occasions the processor enters debug mode
56 * (breakpoint, watchpoint, etc).
57 */
58 static int nds32_v3_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
59 {
60 LOG_DEBUG("nds32_v3_debug_entry");
61
62 enum target_state backup_state = nds32->target->state;
63 nds32->target->state = TARGET_HALTED;
64
65 if (nds32->init_arch_info_after_halted == false) {
66 /* init architecture info according to config registers */
67 CHECK_RETVAL(nds32_config(nds32));
68
69 nds32->init_arch_info_after_halted = true;
70 }
71
72 /* REVISIT entire cache should already be invalid !!! */
73 register_cache_invalidate(nds32->core_cache);
74
75 /* deactivate all hardware breakpoints */
76 CHECK_RETVAL(v3_common_callback->deactivate_hardware_breakpoint(nds32->target));
77
78 if (enable_watchpoint)
79 CHECK_RETVAL(v3_common_callback->deactivate_hardware_watchpoint(nds32->target));
80
81 struct breakpoint *syscall_break = &(nds32->syscall_break);
82 if (nds32->virtual_hosting) {
83 if (syscall_break->set) {
84 /** disable virtual hosting */
85
86 /* remove breakpoint at syscall entry */
87 target_remove_breakpoint(nds32->target, syscall_break);
88 syscall_break->set = 0;
89
90 uint32_t value_pc;
91 nds32_get_mapped_reg(nds32, PC, &value_pc);
92 if (value_pc == syscall_break->address)
93 /** process syscall for virtual hosting */
94 nds32->hit_syscall = true;
95 }
96 }
97
98 if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
99 nds32->target->state = backup_state;
100
101 /* re-activate all hardware breakpoints & watchpoints */
102 CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(nds32->target));
103
104 if (enable_watchpoint)
105 CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(nds32->target));
106
107 return ERROR_FAIL;
108 }
109
110 /* Save registers. */
111 nds32_full_context(nds32);
112
113 /* check interrupt level */
114 v3_common_callback->check_interrupt_stack(nds32);
115
116 return ERROR_OK;
117 }
118
119 /**
120 * Restore processor state.
121 */
122 static int nds32_v3_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
123 {
124 LOG_DEBUG("nds32_v3_leave_debug_state");
125
126 struct target *target = nds32->target;
127
128 /* activate all hardware breakpoints */
129 CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(target));
130
131 if (enable_watchpoint) {
132 /* activate all watchpoints */
133 CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(target));
134 }
135
136 /* restore interrupt stack */
137 v3_common_callback->restore_interrupt_stack(nds32);
138
139 /* REVISIT once we start caring about MMU and cache state,
140 * address it here ...
141 */
142
143 /* restore PSW, PC, and R0 ... after flushing any modified
144 * registers.
145 */
146 CHECK_RETVAL(nds32_restore_context(target));
147
148 if (nds32->virtual_hosting) {
149 /** enable virtual hosting */
150 uint32_t value_ir3;
151 uint32_t entry_size;
152 uint32_t syscall_address;
153
154 /* get syscall entry address */
155 nds32_get_mapped_reg(nds32, IR3, &value_ir3);
156 entry_size = 0x4 << (((value_ir3 >> 14) & 0x3) << 1);
157 syscall_address = (value_ir3 & 0xFFFF0000) + entry_size * 8; /* The index of SYSCALL is 8 */
158
159 if (nds32->hit_syscall) {
160 /* single step to skip syscall entry */
161 /* use IRET to skip syscall */
162 struct aice_port_s *aice = target_to_aice(target);
163 uint32_t value_ir9;
164 uint32_t value_ir6;
165 uint32_t syscall_id;
166
167 nds32_get_mapped_reg(nds32, IR6, &value_ir6);
168 syscall_id = (value_ir6 >> 16) & 0x7FFF;
169
170 if (syscall_id == NDS32_SYSCALL_EXIT) {
171 /* If target hits exit syscall, do not use IRET to skip handler. */
172 aice_step(aice);
173 } else {
174 /* use api->read/write_reg to skip nds32 register cache */
175 uint32_t value_dimbr;
176 aice_read_debug_reg(aice, NDS_EDM_SR_DIMBR, &value_dimbr);
177 aice_write_register(aice, IR11, value_dimbr + 0xC);
178
179 aice_read_register(aice, IR9, &value_ir9);
180 value_ir9 += 4; /* syscall is always 4 bytes */
181 aice_write_register(aice, IR9, value_ir9);
182
183 /* backup hardware breakpoint 0 */
184 uint32_t backup_bpa, backup_bpam, backup_bpc;
185 aice_read_debug_reg(aice, NDS_EDM_SR_BPA0, &backup_bpa);
186 aice_read_debug_reg(aice, NDS_EDM_SR_BPAM0, &backup_bpam);
187 aice_read_debug_reg(aice, NDS_EDM_SR_BPC0, &backup_bpc);
188
189 /* use hardware breakpoint 0 to stop cpu after skipping syscall */
190 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0, value_ir9);
191 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0, 0);
192 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0, 0xA);
193
194 /* Execute two IRET.
195 * First IRET is used to quit debug mode.
196 * Second IRET is used to quit current syscall. */
197 uint32_t dim_inst[4] = {NOP, NOP, IRET, IRET};
198 aice_execute(aice, dim_inst, 4);
199
200 /* restore origin hardware breakpoint 0 */
201 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0, backup_bpa);
202 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0, backup_bpam);
203 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0, backup_bpc);
204 }
205
206 nds32->hit_syscall = false;
207 }
208
209 /* insert breakpoint at syscall entry */
210 struct breakpoint *syscall_break = &(nds32->syscall_break);
211
212 syscall_break->address = syscall_address;
213 syscall_break->type = BKPT_SOFT;
214 syscall_break->set = 1;
215 target_add_breakpoint(target, syscall_break);
216 }
217
218 return ERROR_OK;
219 }
220
221 static int nds32_v3_get_exception_address(struct nds32 *nds32,
222 uint32_t *address, uint32_t reason)
223 {
224 LOG_DEBUG("nds32_v3_get_exception_address");
225
226 struct aice_port_s *aice = target_to_aice(nds32->target);
227 struct target *target = nds32->target;
228 uint32_t edmsw;
229 uint32_t edm_cfg;
230 uint32_t match_bits;
231 uint32_t match_count;
232 int32_t i;
233 static int32_t number_of_hard_break;
234 uint32_t bp_control;
235
236 if (number_of_hard_break == 0) {
237 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
238 number_of_hard_break = (edm_cfg & 0x7) + 1;
239 }
240
241 aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
242 /* clear matching bits (write-one-clear) */
243 aice_write_debug_reg(aice, NDS_EDM_SR_EDMSW, edmsw);
244 match_bits = (edmsw >> 4) & 0xFF;
245 match_count = 0;
246 for (i = 0 ; i < number_of_hard_break ; i++) {
247 if (match_bits & (1 << i)) {
248 aice_read_debug_reg(aice, NDS_EDM_SR_BPA0 + i, address);
249 match_count++;
250
251 /* If target hits multiple read/access watchpoint,
252 * select the first one. */
253 aice_read_debug_reg(aice, NDS_EDM_SR_BPC0 + i, &bp_control);
254 if (0x3 == (bp_control & 0x3)) {
255 match_count = 1;
256 break;
257 }
258 }
259 }
260
261 if (match_count > 1) { /* multiple hits */
262 *address = 0;
263 return ERROR_OK;
264 } else if (match_count == 1) {
265 uint32_t val_pc;
266 uint32_t opcode;
267 struct nds32_instruction instruction;
268 struct watchpoint *wp;
269 bool hit;
270
271 nds32_get_mapped_reg(nds32, PC, &val_pc);
272
273 if ((NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE == reason) ||
274 (NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE == reason)) {
275 if (edmsw & 0x4) /* check EDMSW.IS_16BIT */
276 val_pc -= 2;
277 else
278 val_pc -= 4;
279 }
280
281 nds32_read_opcode(nds32, val_pc, &opcode);
282 nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
283
284 LOG_DEBUG("PC: 0x%08x, access start: 0x%08x, end: 0x%08x", val_pc,
285 instruction.access_start, instruction.access_end);
286
287 /* check if multiple hits in the access range */
288 uint32_t in_range_watch_count = 0;
289 for (wp = target->watchpoints; wp; wp = wp->next) {
290 if ((instruction.access_start <= wp->address) &&
291 (wp->address < instruction.access_end))
292 in_range_watch_count++;
293 }
294 if (in_range_watch_count > 1) {
295 /* Hit LSMW instruction. */
296 *address = 0;
297 return ERROR_OK;
298 }
299
300 /* dispel false match */
301 hit = false;
302 for (wp = target->watchpoints; wp; wp = wp->next) {
303 if (((*address ^ wp->address) & (~wp->mask)) == 0) {
304 uint32_t watch_start;
305 uint32_t watch_end;
306
307 watch_start = wp->address;
308 watch_end = wp->address + wp->length;
309
310 if ((watch_end <= instruction.access_start) ||
311 (instruction.access_end <= watch_start))
312 continue;
313
314 hit = true;
315 break;
316 }
317 }
318
319 if (hit)
320 return ERROR_OK;
321 else
322 return ERROR_FAIL;
323 } else if (match_count == 0) {
324 /* global stop is precise exception */
325 if ((NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP == reason) && nds32->global_stop) {
326 /* parse instruction to get correct access address */
327 uint32_t val_pc;
328 uint32_t opcode;
329 struct nds32_instruction instruction;
330
331 nds32_get_mapped_reg(nds32, PC, &val_pc);
332 nds32_read_opcode(nds32, val_pc, &opcode);
333 nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
334
335 *address = instruction.access_start;
336
337 return ERROR_OK;
338 }
339 }
340
341 *address = 0xFFFFFFFF;
342 return ERROR_FAIL;
343 }
344
345 void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback)
346 {
347 v3_common_callback = callback;
348 }
349
350 /** target_type functions: */
351 /* target request support */
352 int nds32_v3_target_request_data(struct target *target,
353 uint32_t size, uint8_t *buffer)
354 {
355 /* AndesCore could use DTR register to communicate with OpenOCD
356 * to output messages
357 * Target data will be put in buffer
358 * The format of DTR is as follow
359 * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
360 * target_req_cmd has three possible values:
361 * TARGET_REQ_TRACEMSG
362 * TARGET_REQ_DEBUGMSG
363 * TARGET_REQ_DEBUGCHAR
364 * if size == 0, target will call target_asciimsg(),
365 * else call target_hexmsg()
366 */
367 LOG_WARNING("Not implemented: %s", __func__);
368
369 return ERROR_OK;
370 }
371
372 int nds32_v3_checksum_memory(struct target *target,
373 uint32_t address, uint32_t count, uint32_t *checksum)
374 {
375 LOG_WARNING("Not implemented: %s", __func__);
376
377 return ERROR_FAIL;
378 }
379
380 /**
381 * find out which watchpoint hits
382 * get exception address and compare the address to watchpoints
383 */
384 int nds32_v3_hit_watchpoint(struct target *target,
385 struct watchpoint **hit_watchpoint)
386 {
387 static struct watchpoint scan_all_watchpoint;
388
389 uint32_t exception_address;
390 struct watchpoint *wp;
391 struct nds32 *nds32 = target_to_nds32(target);
392
393 exception_address = nds32->watched_address;
394
395 if (exception_address == 0xFFFFFFFF)
396 return ERROR_FAIL;
397
398 if (exception_address == 0) {
399 scan_all_watchpoint.address = 0;
400 scan_all_watchpoint.rw = WPT_WRITE;
401 scan_all_watchpoint.next = 0;
402 scan_all_watchpoint.unique_id = 0x5CA8;
403
404 *hit_watchpoint = &scan_all_watchpoint;
405 return ERROR_OK;
406 }
407
408 for (wp = target->watchpoints; wp; wp = wp->next) {
409 if (((exception_address ^ wp->address) & (~wp->mask)) == 0) {
410 *hit_watchpoint = wp;
411
412 return ERROR_OK;
413 }
414 }
415
416 return ERROR_FAIL;
417 }
418
419 int nds32_v3_target_create_common(struct target *target, struct nds32 *nds32)
420 {
421 nds32->register_map = nds32_v3_register_mapping;
422 nds32->get_debug_reason = nds32_v3_get_debug_reason;
423 nds32->enter_debug_state = nds32_v3_debug_entry;
424 nds32->leave_debug_state = nds32_v3_leave_debug_state;
425 nds32->get_watched_address = nds32_v3_get_exception_address;
426
427 /* Init target->arch_info in nds32_init_arch_info().
428 * After this, user could use target_to_nds32() to get nds32 object */
429 nds32_init_arch_info(target, nds32);
430
431 return ERROR_OK;
432 }
433
434 int nds32_v3_run_algorithm(struct target *target,
435 int num_mem_params,
436 struct mem_param *mem_params,
437 int num_reg_params,
438 struct reg_param *reg_params,
439 uint32_t entry_point,
440 uint32_t exit_point,
441 int timeout_ms,
442 void *arch_info)
443 {
444 LOG_WARNING("Not implemented: %s", __func__);
445
446 return ERROR_FAIL;
447 }
448
449 int nds32_v3_read_buffer(struct target *target, uint32_t address,
450 uint32_t size, uint8_t *buffer)
451 {
452 struct nds32 *nds32 = target_to_nds32(target);
453 struct nds32_memory *memory = &(nds32->memory);
454
455 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
456 (target->state != TARGET_HALTED)) {
457 LOG_WARNING("target was not halted");
458 return ERROR_TARGET_NOT_HALTED;
459 }
460
461 uint32_t physical_address;
462 /* BUG: If access range crosses multiple pages, the translation will not correct
463 * for second page or so. */
464
465 /* When DEX is set to one, hardware will enforce the following behavior without
466 * modifying the corresponding control bits in PSW.
467 *
468 * Disable all interrupts
469 * Become superuser mode
470 * Turn off IT/DT
471 * Use MMU_CFG.DE as the data access endian
472 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
473 * Disable audio special features
474 * Disable inline function call
475 *
476 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
477 * to physical address.
478 */
479 if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
480 address = physical_address;
481 else
482 return ERROR_FAIL;
483
484 int result;
485 struct aice_port_s *aice = target_to_aice(target);
486 /* give arbitrary initial value to avoid warning messages */
487 enum nds_memory_access origin_access_channel = NDS_MEMORY_ACC_CPU;
488
489 if (nds32->hit_syscall) {
490 /* Use bus mode to access memory during virtual hosting */
491 origin_access_channel = memory->access_channel;
492 memory->access_channel = NDS_MEMORY_ACC_BUS;
493 aice_memory_access(aice, NDS_MEMORY_ACC_BUS);
494 }
495
496 result = nds32_read_buffer(target, address, size, buffer);
497
498 if (nds32->hit_syscall) {
499 /* Restore access_channel after virtual hosting */
500 memory->access_channel = origin_access_channel;
501 aice_memory_access(aice, origin_access_channel);
502 }
503
504 return result;
505 }
506
507 int nds32_v3_write_buffer(struct target *target, uint32_t address,
508 uint32_t size, const uint8_t *buffer)
509 {
510 struct nds32 *nds32 = target_to_nds32(target);
511 struct nds32_memory *memory = &(nds32->memory);
512
513 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
514 (target->state != TARGET_HALTED)) {
515 LOG_WARNING("target was not halted");
516 return ERROR_TARGET_NOT_HALTED;
517 }
518
519 uint32_t physical_address;
520 /* BUG: If access range crosses multiple pages, the translation will not correct
521 * for second page or so. */
522
523 /* When DEX is set to one, hardware will enforce the following behavior without
524 * modifying the corresponding control bits in PSW.
525 *
526 * Disable all interrupts
527 * Become superuser mode
528 * Turn off IT/DT
529 * Use MMU_CFG.DE as the data access endian
530 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
531 * Disable audio special features
532 * Disable inline function call
533 *
534 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
535 * to physical address.
536 */
537 if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
538 address = physical_address;
539 else
540 return ERROR_FAIL;
541
542 if (nds32->hit_syscall) {
543 struct aice_port_s *aice = target_to_aice(target);
544 enum nds_memory_access origin_access_channel;
545 origin_access_channel = memory->access_channel;
546
547 /* If target has no cache, use BUS mode to access memory. */
548 if ((memory->dcache.line_size == 0)
549 || (memory->dcache.enable == false)) {
550 /* There is no Dcache or Dcache is disabled. */
551 memory->access_channel = NDS_MEMORY_ACC_BUS;
552 aice_memory_access(aice, NDS_MEMORY_ACC_BUS);
553 }
554
555 int result;
556 result = nds32_gdb_fileio_write_memory(nds32, address, size, buffer);
557
558 if (NDS_MEMORY_ACC_CPU == origin_access_channel) {
559 memory->access_channel = NDS_MEMORY_ACC_CPU;
560 aice_memory_access(aice, NDS_MEMORY_ACC_CPU);
561 }
562
563 return result;
564 }
565
566 return nds32_write_buffer(target, address, size, buffer);
567 }
568
569 int nds32_v3_read_memory(struct target *target, uint32_t address,
570 uint32_t size, uint32_t count, uint8_t *buffer)
571 {
572 struct nds32 *nds32 = target_to_nds32(target);
573 struct nds32_memory *memory = &(nds32->memory);
574
575 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
576 (target->state != TARGET_HALTED)) {
577 LOG_WARNING("target was not halted");
578 return ERROR_TARGET_NOT_HALTED;
579 }
580
581 uint32_t physical_address;
582 /* BUG: If access range crosses multiple pages, the translation will not correct
583 * for second page or so. */
584
585 /* When DEX is set to one, hardware will enforce the following behavior without
586 * modifying the corresponding control bits in PSW.
587 *
588 * Disable all interrupts
589 * Become superuser mode
590 * Turn off IT/DT
591 * Use MMU_CFG.DE as the data access endian
592 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
593 * Disable audio special features
594 * Disable inline function call
595 *
596 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
597 * to physical address.
598 */
599 if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
600 address = physical_address;
601 else
602 return ERROR_FAIL;
603
604 struct aice_port_s *aice = target_to_aice(target);
605 /* give arbitrary initial value to avoid warning messages */
606 enum nds_memory_access origin_access_channel = NDS_MEMORY_ACC_CPU;
607 int result;
608
609 if (nds32->hit_syscall) {
610 /* Use bus mode to access memory during virtual hosting */
611 origin_access_channel = memory->access_channel;
612 memory->access_channel = NDS_MEMORY_ACC_BUS;
613 aice_memory_access(aice, NDS_MEMORY_ACC_BUS);
614 }
615
616 result = nds32_read_memory(target, address, size, count, buffer);
617
618 if (nds32->hit_syscall) {
619 /* Restore access_channel after virtual hosting */
620 memory->access_channel = origin_access_channel;
621 aice_memory_access(aice, origin_access_channel);
622 }
623
624 return result;
625 }
626
627 int nds32_v3_write_memory(struct target *target, uint32_t address,
628 uint32_t size, uint32_t count, const uint8_t *buffer)
629 {
630 struct nds32 *nds32 = target_to_nds32(target);
631 struct nds32_memory *memory = &(nds32->memory);
632
633 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
634 (target->state != TARGET_HALTED)) {
635 LOG_WARNING("target was not halted");
636 return ERROR_TARGET_NOT_HALTED;
637 }
638
639 uint32_t physical_address;
640 /* BUG: If access range crosses multiple pages, the translation will not correct
641 * for second page or so. */
642
643 /* When DEX is set to one, hardware will enforce the following behavior without
644 * modifying the corresponding control bits in PSW.
645 *
646 * Disable all interrupts
647 * Become superuser mode
648 * Turn off IT/DT
649 * Use MMU_CFG.DE as the data access endian
650 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
651 * Disable audio special features
652 * Disable inline function call
653 *
654 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
655 * to physical address.
656 */
657 if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
658 address = physical_address;
659 else
660 return ERROR_FAIL;
661
662 return nds32_write_memory(target, address, size, count, buffer);
663 }
664
665 int nds32_v3_init_target(struct command_context *cmd_ctx,
666 struct target *target)
667 {
668 /* Initialize anything we can set up without talking to the target */
669 struct nds32 *nds32 = target_to_nds32(target);
670
671 nds32_init(nds32);
672
673 target->fileio_info = malloc(sizeof(struct gdb_fileio_info));
674 target->fileio_info->identifier = NULL;
675
676 return ERROR_OK;
677 }
Official OpenOCD Mirror