1 /***************************************************************************
2 * Copyright (C) 2007, 2008 by Ben Dooks *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
22 * S3C2440 OpenOCD NAND Flash controller support.
24 * Many thanks to Simtec Electronics for sponsoring this work.
34 NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command
)
36 struct s3c24xx_nand_controller
*info
;
37 CALL_S3C24XX_DEVICE_COMMAND(nand
, &info
);
39 /* fill in the address fields for the core device */
40 info
->cmd
= S3C2440_NFCMD
;
41 info
->addr
= S3C2440_NFADDR
;
42 info
->data
= S3C2440_NFDATA
;
43 info
->nfstat
= S3C2440_NFSTAT
;
48 static int s3c2440_init(struct nand_device
*nand
)
50 struct target
*target
= nand
->target
;
52 target_write_u32(target
, S3C2410_NFCONF
,
53 S3C2440_NFCONF_TACLS(3) |
54 S3C2440_NFCONF_TWRPH0(7) |
55 S3C2440_NFCONF_TWRPH1(7));
57 target_write_u32(target
, S3C2440_NFCONT
,
58 S3C2440_NFCONT_INITECC
| S3C2440_NFCONT_ENABLE
);
63 int s3c2440_nand_ready(struct nand_device
*nand
, int timeout
)
65 struct s3c24xx_nand_controller
*s3c24xx_info
= nand
->controller_priv
;
66 struct target
*target
= nand
->target
;
69 if (target
->state
!= TARGET_HALTED
) {
70 LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
71 return ERROR_NAND_OPERATION_FAILED
;
75 target_read_u8(target
, s3c24xx_info
->nfstat
, &status
);
77 if (status
& S3C2440_NFSTAT_READY
)
81 } while (timeout
-- > 0);
87 /* use the fact we can read/write 4 bytes in one go via a single 32bit op */
89 int s3c2440_read_block_data(struct nand_device
*nand
, uint8_t *data
, int data_size
)
91 struct s3c24xx_nand_controller
*s3c24xx_info
= nand
->controller_priv
;
92 struct target
*target
= nand
->target
;
93 uint32_t nfdata
= s3c24xx_info
->data
;
96 LOG_INFO("%s: reading data: %p, %p, %d\n", __func__
, nand
, data
, data_size
);
98 if (target
->state
!= TARGET_HALTED
) {
99 LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
100 return ERROR_NAND_OPERATION_FAILED
;
103 while (data_size
>= 4) {
104 target_read_u32(target
, nfdata
, &tmp
);
115 while (data_size
> 0) {
116 target_read_u8(target
, nfdata
, data
);
125 int s3c2440_write_block_data(struct nand_device
*nand
, uint8_t *data
, int data_size
)
127 struct s3c24xx_nand_controller
*s3c24xx_info
= nand
->controller_priv
;
128 struct target
*target
= nand
->target
;
129 uint32_t nfdata
= s3c24xx_info
->data
;
132 if (target
->state
!= TARGET_HALTED
) {
133 LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
134 return ERROR_NAND_OPERATION_FAILED
;
137 while (data_size
>= 4) {
138 tmp
= le_to_h_u32(data
);
139 target_write_u32(target
, nfdata
, tmp
);
145 while (data_size
> 0) {
146 target_write_u8(target
, nfdata
, *data
);
155 struct nand_flash_controller s3c2440_nand_controller
= {
157 .nand_device_command
= &s3c2440_nand_device_command
,
158 .init
= &s3c2440_init
,
159 .reset
= &s3c24xx_reset
,
160 .command
= &s3c24xx_command
,
161 .address
= &s3c24xx_address
,
162 .write_data
= &s3c24xx_write_data
,
163 .read_data
= &s3c24xx_read_data
,
164 .write_page
= s3c24xx_write_page
,
165 .read_page
= s3c24xx_read_page
,
166 .write_block_data
= &s3c2440_write_block_data
,
167 .read_block_data
= &s3c2440_read_block_data
,
168 .nand_ready
= &s3c2440_nand_ready
,