src/flash/nand/mxc.h

   1
   2 /***************************************************************************
   3  *   Copyright (C) 2009 by Alexei Babich                                   *
   4  *   Rezonans plc., Chelyabinsk, Russia                                    *
   5  *   impatt@mail.ru                                                        *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Erik Ahlen                                      *
   8  *   Avalon Innovation, Sweden                                             *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  24  ***************************************************************************/
  25
  26 /*
  27  * Freescale iMX OpenOCD NAND Flash controller support.
  28  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  29  *
  30  * Many thanks to Ben Dooks for writing s3c24xx driver.
  31  */
  32
  33 #define         MXC_NF_BUFSIZ                           (mxc_nf_info->mxc_regs_addr + 0x00)
  34 #define         MXC_NF_BUFADDR                          (mxc_nf_info->mxc_regs_addr + 0x04)
  35 #define         MXC_NF_FADDR                            (mxc_nf_info->mxc_regs_addr + 0x06)
  36 #define         MXC_NF_FCMD                                     (mxc_nf_info->mxc_regs_addr + 0x08)
  37 #define         MXC_NF_BUFCFG                           (mxc_nf_info->mxc_regs_addr + 0x0a)
  38 #define         MXC_NF_ECCSTATUS                        (mxc_nf_info->mxc_regs_addr + 0x0c)
  39 #define         MXC_NF_ECCMAINPOS                       (mxc_nf_info->mxc_regs_addr + 0x0e)
  40 #define         MXC_NF_V1_ECCSPAREPOS           (mxc_nf_info->mxc_regs_addr + 0x10)
  41 #define         MXC_NF_V2_SPAS                          (mxc_nf_info->mxc_regs_addr + 0x10)
  42 #define         MXC_NF_FWP                                      (mxc_nf_info->mxc_regs_addr + 0x12)
  43 #define         MXC_NF_V1_UNLOCKSTART           (mxc_nf_info->mxc_regs_addr + 0x14)
  44 #define         MXC_NF_V1_UNLOCKEND                     (mxc_nf_info->mxc_regs_addr + 0x16)
  45 #define         MXC_NF_V2_UNLOCKSTART0          (mxc_nf_info->mxc_regs_addr + 0x20)
  46 #define         MXC_NF_V2_UNLOCKSTART1          (mxc_nf_info->mxc_regs_addr + 0x24)
  47 #define         MXC_NF_V2_UNLOCKSTART2          (mxc_nf_info->mxc_regs_addr + 0x28)
  48 #define         MXC_NF_V2_UNLOCKSTART3          (mxc_nf_info->mxc_regs_addr + 0x2c)
  49 #define         MXC_NF_V2_UNLOCKEND0            (mxc_nf_info->mxc_regs_addr + 0x22)
  50 #define         MXC_NF_V2_UNLOCKEND1            (mxc_nf_info->mxc_regs_addr + 0x26)
  51 #define         MXC_NF_V2_UNLOCKEND2            (mxc_nf_info->mxc_regs_addr + 0x2a)
  52 #define         MXC_NF_V2_UNLOCKEND3            (mxc_nf_info->mxc_regs_addr + 0x2e)
  53 #define         MXC_NF_FWPSTATUS                        (mxc_nf_info->mxc_regs_addr + 0x18)
  54  /*
  55   * all bits not marked as self-clearing bit
  56   */
  57 #define         MXC_NF_CFG1                                     (mxc_nf_info->mxc_regs_addr + 0x1a)
  58 #define         MXC_NF_CFG2                                     (mxc_nf_info->mxc_regs_addr + 0x1c)
  59
  60 #define         MXC_NF_MAIN_BUFFER0                     (mxc_nf_info->mxc_base_addr + 0x0000)
  61 #define         MXC_NF_MAIN_BUFFER1                     (mxc_nf_info->mxc_base_addr + 0x0200)
  62 #define         MXC_NF_MAIN_BUFFER2                     (mxc_nf_info->mxc_base_addr + 0x0400)
  63 #define         MXC_NF_MAIN_BUFFER3                     (mxc_nf_info->mxc_base_addr + 0x0600)
  64 #define         MXC_NF_V1_SPARE_BUFFER0         (mxc_nf_info->mxc_base_addr + 0x0800)
  65 #define         MXC_NF_V1_SPARE_BUFFER1         (mxc_nf_info->mxc_base_addr + 0x0810)
  66 #define         MXC_NF_V1_SPARE_BUFFER2         (mxc_nf_info->mxc_base_addr + 0x0820)
  67 #define         MXC_NF_V1_SPARE_BUFFER3         (mxc_nf_info->mxc_base_addr + 0x0830)
  68 #define         MXC_NF_V2_MAIN_BUFFER4          (mxc_nf_info->mxc_base_addr + 0x0800)
  69 #define         MXC_NF_V2_MAIN_BUFFER5          (mxc_nf_info->mxc_base_addr + 0x0a00)
  70 #define         MXC_NF_V2_MAIN_BUFFER6          (mxc_nf_info->mxc_base_addr + 0x0c00)
  71 #define         MXC_NF_V2_MAIN_BUFFER7          (mxc_nf_info->mxc_base_addr + 0x0e00)
  72 #define         MXC_NF_V2_SPARE_BUFFER0         (mxc_nf_info->mxc_base_addr + 0x1000)
  73 #define         MXC_NF_V2_SPARE_BUFFER1         (mxc_nf_info->mxc_base_addr + 0x1040)
  74 #define         MXC_NF_V2_SPARE_BUFFER2         (mxc_nf_info->mxc_base_addr + 0x1080)
  75 #define         MXC_NF_V2_SPARE_BUFFER3         (mxc_nf_info->mxc_base_addr + 0x10c0)
  76 #define         MXC_NF_V2_SPARE_BUFFER4         (mxc_nf_info->mxc_base_addr + 0x1100)
  77 #define         MXC_NF_V2_SPARE_BUFFER5         (mxc_nf_info->mxc_base_addr + 0x1140)
  78 #define         MXC_NF_V2_SPARE_BUFFER6         (mxc_nf_info->mxc_base_addr + 0x1180)
  79 #define         MXC_NF_V2_SPARE_BUFFER7         (mxc_nf_info->mxc_base_addr + 0x11c0)
  80 #define         MXC_NF_MAIN_BUFFER_LEN          512
  81 #define         MXC_NF_SPARE_BUFFER_LEN         16
  82 #define         MXC_NF_SPARE_BUFFER_MAX         64
  83 #define         MXC_NF_V1_LAST_BUFFADDR         ((MXC_NF_V1_SPARE_BUFFER3) + \
  84         MXC_NF_SPARE_BUFFER_LEN - 2)
  85 #define         MXC_NF_V2_LAST_BUFFADDR         ((MXC_NF_V2_SPARE_BUFFER7) + \
  86         MXC_NF_SPARE_BUFFER_LEN - 2)
  87
  88 /* bits in MXC_NF_CFG1 register */
  89 #define         MXC_NF_BIT_ECC_4BIT                     (1<<0)
  90 #define         MXC_NF_BIT_SPARE_ONLY_EN        (1<<2)
  91 #define         MXC_NF_BIT_ECC_EN                       (1<<3)
  92 #define         MXC_NF_BIT_INT_DIS                      (1<<4)
  93 #define         MXC_NF_BIT_BE_EN                        (1<<5)
  94 #define         MXC_NF_BIT_RESET_EN                     (1<<6)
  95 #define         MXC_NF_BIT_FORCE_CE                     (1<<7)
  96 #define         MXC_NF_V2_CFG1_PPB(x)           (((x) & 0x3) << 9)
  97
  98 /* bits in MXC_NF_CFG2 register */
  99
 100 /*Flash Command Input*/
 101 #define         MXC_NF_BIT_OP_FCI                       (1<<0)
 102  /*
 103   * Flash Address Input
 104   */
 105 #define         MXC_NF_BIT_OP_FAI                       (1<<1)
 106  /*
 107   * Flash Data Input
 108   */
 109 #define         MXC_NF_BIT_OP_FDI                       (1<<2)
 110
 111 /* see "enum mx_dataout_type" below */
 112 #define         MXC_NF_BIT_DATAOUT_TYPE(x)      ((x)<<3)
 113 #define         MXC_NF_BIT_OP_DONE                      (1<<15)
 114
 115 #define         MXC_CCM_CGR2                            0x53f80028
 116 #define         MXC_GPR                                         0x43fac008
 117 #define         MX2_FMCR                                        0x10027814
 118 #define         MX2_FMCR_NF_16BIT_SEL           (1<<4)
 119 #define         MX2_FMCR_NF_FMS                         (1<<5)
 120 #define         MX25_RCSR                                       0x53f80018
 121 #define         MX25_RCSR_NF_16BIT_SEL          (1<<14)
 122 #define         MX25_RCSR_NF_FMS                        (1<<8)
 123 #define         MX25_RCSR_NF_4K                         (1<<9)
 124 #define         MX3_PCSR                                        0x53f8000c
 125 #define         MX3_PCSR_NF_16BIT_SEL           (1<<31)
 126 #define         MX3_PCSR_NF_FMS                         (1<<30)
 127 #define         MX35_RCSR                                       0x53f80018
 128 #define         MX35_RCSR_NF_16BIT_SEL          (1<<14)
 129 #define         MX35_RCSR_NF_FMS                        (1<<8)
 130 #define         MX35_RCSR_NF_4K                         (1<<9)
 131
 132 enum mxc_version {
 133         MXC_VERSION_UKWN = 0,
 134         MXC_VERSION_MX25 = 1,
 135         MXC_VERSION_MX27 = 2,
 136         MXC_VERSION_MX31 = 3,
 137         MXC_VERSION_MX35 = 4
 138 };
 139
 140 enum mxc_dataout_type {
 141         MXC_NF_DATAOUT_PAGE = 1,
 142         MXC_NF_DATAOUT_NANDID = 2,
 143         MXC_NF_DATAOUT_NANDSTATUS = 4,
 144 };
 145
 146 enum mxc_nf_finalize_action {
 147         MXC_NF_FIN_NONE,
 148         MXC_NF_FIN_DATAOUT,
 149 };
 150
 151 struct mxc_nf_flags {
 152         unsigned host_little_endian:1;
 153         unsigned target_little_endian:1;
 154         unsigned nand_readonly:1;
 155         unsigned one_kb_sram:1;
 156         unsigned hw_ecc_enabled:1;
 157         unsigned biswap_enabled:1;
 158 };
 159
 160 struct mxc_nf_controller {
 161         enum mxc_version mxc_version;
 162         uint32_t mxc_base_addr;
 163         uint32_t mxc_regs_addr;
 164         enum mxc_dataout_type optype;
 165         enum mxc_nf_finalize_action fin;
 166         struct mxc_nf_flags flags;
 167 };