1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program; if not, write to the *
29 * Free Software Foundation, Inc., *
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
32 * Cortex-A8(tm) TRM, ARM DDI 0344H *
33 * Cortex-A9(tm) TRM, ARM DDI 0407F *
35 ***************************************************************************/
40 #include "breakpoints.h"
43 #include "target_request.h"
44 #include "target_type.h"
45 #include "arm_opcodes.h"
46 #include <helper/time_support.h>
48 static int cortex_a8_poll(struct target
*target
);
49 static int cortex_a8_debug_entry(struct target
*target
);
50 static int cortex_a8_restore_context(struct target
*target
, bool bpwp
);
51 static int cortex_a8_set_breakpoint(struct target
*target
,
52 struct breakpoint
*breakpoint
, uint8_t matchmode
);
53 static int cortex_a8_unset_breakpoint(struct target
*target
,
54 struct breakpoint
*breakpoint
);
55 static int cortex_a8_dap_read_coreregister_u32(struct target
*target
,
56 uint32_t *value
, int regnum
);
57 static int cortex_a8_dap_write_coreregister_u32(struct target
*target
,
58 uint32_t value
, int regnum
);
59 static int cortex_a8_mmu(struct target
*target
, int *enabled
);
60 static int cortex_a8_virt2phys(struct target
*target
,
61 uint32_t virt
, uint32_t *phys
);
62 static int cortex_a8_disable_mmu_caches(struct target
*target
, int mmu
,
63 int d_u_cache
, int i_cache
);
64 static int cortex_a8_enable_mmu_caches(struct target
*target
, int mmu
,
65 int d_u_cache
, int i_cache
);
66 static int cortex_a8_get_ttb(struct target
*target
, uint32_t *result
);
70 * FIXME do topology discovery using the ROM; don't
71 * assume this is an OMAP3. Also, allow for multiple ARMv7-A
72 * cores, with different AP numbering ... don't use a #define
73 * for these numbers, use per-core armv7a state.
75 #define swjdp_memoryap 0
76 #define swjdp_debugap 1
79 * Cortex-A8 Basic debug access, very low level assumes state is saved
81 static int cortex_a8_init_debug_access(struct target
*target
)
83 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
84 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
90 /* Unlocking the debug registers for modification */
91 /* The debugport might be uninitialised so try twice */
92 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
,
93 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
94 if (retval
!= ERROR_OK
)
97 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
,
98 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
99 if (retval
== ERROR_OK
)
101 LOG_USER("Locking debug access failed on first, but succeeded on second try.");
104 if (retval
!= ERROR_OK
)
106 /* Clear Sticky Power Down status Bit in PRSR to enable access to
107 the registers in the Core Power Domain */
108 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
109 armv7a
->debug_base
+ CPUDBG_PRSR
, &dummy
);
110 if (retval
!= ERROR_OK
)
113 /* Enabling of instruction execution in debug mode is done in debug_entry code */
115 /* Resync breakpoint registers */
117 /* Since this is likely called from init or reset, update target state information*/
118 return cortex_a8_poll(target
);
121 /* To reduce needless round-trips, pass in a pointer to the current
122 * DSCR value. Initialize it to zero if you just need to know the
123 * value on return from this function; or DSCR_INSTR_COMP if you
124 * happen to know that no instruction is pending.
126 static int cortex_a8_exec_opcode(struct target
*target
,
127 uint32_t opcode
, uint32_t *dscr_p
)
131 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
132 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
134 dscr
= dscr_p
? *dscr_p
: 0;
136 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
138 /* Wait for InstrCompl bit to be set */
139 long long then
= timeval_ms();
140 while ((dscr
& DSCR_INSTR_COMP
) == 0)
142 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
143 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
144 if (retval
!= ERROR_OK
)
146 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32
, opcode
);
149 if (timeval_ms() > then
+ 1000)
151 LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
156 retval
= mem_ap_sel_write_u32(swjdp
, swjdp_debugap
,
157 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
158 if (retval
!= ERROR_OK
)
164 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
165 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
166 if (retval
!= ERROR_OK
)
168 LOG_ERROR("Could not read DSCR register");
171 if (timeval_ms() > then
+ 1000)
173 LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
177 while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
185 /**************************************************************************
186 Read core register with very few exec_opcode, fast but needs work_area.
187 This can cause problems with MMU active.
188 **************************************************************************/
189 static int cortex_a8_read_regs_through_mem(struct target
*target
, uint32_t address
,
192 int retval
= ERROR_OK
;
193 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
194 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
196 retval
= cortex_a8_dap_read_coreregister_u32(target
, regfile
, 0);
197 if (retval
!= ERROR_OK
)
199 retval
= cortex_a8_dap_write_coreregister_u32(target
, address
, 0);
200 if (retval
!= ERROR_OK
)
202 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
203 if (retval
!= ERROR_OK
)
206 retval
= mem_ap_sel_read_buf_u32(swjdp
, swjdp_memoryap
,
207 (uint8_t *)(®file
[1]), 4*15, address
);
212 static int cortex_a8_dap_read_coreregister_u32(struct target
*target
,
213 uint32_t *value
, int regnum
)
215 int retval
= ERROR_OK
;
216 uint8_t reg
= regnum
&0xFF;
218 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
219 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
226 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
227 retval
= cortex_a8_exec_opcode(target
,
228 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
230 if (retval
!= ERROR_OK
)
235 /* "MOV r0, r15"; then move r0 to DCCTX */
236 retval
= cortex_a8_exec_opcode(target
, 0xE1A0000F, &dscr
);
237 if (retval
!= ERROR_OK
)
239 retval
= cortex_a8_exec_opcode(target
,
240 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
242 if (retval
!= ERROR_OK
)
247 /* "MRS r0, CPSR" or "MRS r0, SPSR"
248 * then move r0 to DCCTX
250 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
251 if (retval
!= ERROR_OK
)
253 retval
= cortex_a8_exec_opcode(target
,
254 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
256 if (retval
!= ERROR_OK
)
260 /* Wait for DTRRXfull then read DTRRTX */
261 long long then
= timeval_ms();
262 while ((dscr
& DSCR_DTR_TX_FULL
) == 0)
264 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
265 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
266 if (retval
!= ERROR_OK
)
268 if (timeval_ms() > then
+ 1000)
270 LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
275 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
276 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
277 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
282 static int cortex_a8_dap_write_coreregister_u32(struct target
*target
,
283 uint32_t value
, int regnum
)
285 int retval
= ERROR_OK
;
286 uint8_t Rd
= regnum
&0xFF;
288 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
289 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
291 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
293 /* Check that DCCRX is not full */
294 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
295 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
296 if (retval
!= ERROR_OK
)
298 if (dscr
& DSCR_DTR_RX_FULL
)
300 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
301 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
302 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
304 if (retval
!= ERROR_OK
)
311 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
312 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
313 retval
= mem_ap_sel_write_u32(swjdp
, swjdp_debugap
,
314 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
315 if (retval
!= ERROR_OK
)
320 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
321 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
324 if (retval
!= ERROR_OK
)
329 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
332 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
334 if (retval
!= ERROR_OK
)
336 retval
= cortex_a8_exec_opcode(target
, 0xE1A0F000, &dscr
);
337 if (retval
!= ERROR_OK
)
342 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
343 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
345 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
347 if (retval
!= ERROR_OK
)
349 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
351 if (retval
!= ERROR_OK
)
354 /* "Prefetch flush" after modifying execution status in CPSR */
357 retval
= cortex_a8_exec_opcode(target
,
358 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
360 if (retval
!= ERROR_OK
)
368 /* Write to memory mapped registers directly with no cache or mmu handling */
369 static int cortex_a8_dap_write_memap_register_u32(struct target
*target
, uint32_t address
, uint32_t value
)
372 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
373 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
375 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
, address
, value
);
381 * Cortex-A8 implementation of Debug Programmer's Model
383 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
384 * so there's no need to poll for it before executing an instruction.
386 * NOTE that in several of these cases the "stall" mode might be useful.
387 * It'd let us queue a few operations together... prepare/finish might
388 * be the places to enable/disable that mode.
391 static inline struct cortex_a8_common
*dpm_to_a8(struct arm_dpm
*dpm
)
393 return container_of(dpm
, struct cortex_a8_common
, armv7a_common
.dpm
);
396 static int cortex_a8_write_dcc(struct cortex_a8_common
*a8
, uint32_t data
)
398 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
399 return mem_ap_sel_write_u32(a8
->armv7a_common
.armv4_5_common
.dap
,
400 swjdp_debugap
,a8
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
403 static int cortex_a8_read_dcc(struct cortex_a8_common
*a8
, uint32_t *data
,
406 struct adiv5_dap
*swjdp
= a8
->armv7a_common
.armv4_5_common
.dap
;
407 uint32_t dscr
= DSCR_INSTR_COMP
;
413 /* Wait for DTRRXfull */
414 long long then
= timeval_ms();
415 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
416 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
417 a8
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
419 if (retval
!= ERROR_OK
)
421 if (timeval_ms() > then
+ 1000)
423 LOG_ERROR("Timeout waiting for read dcc");
428 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
429 a8
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
430 if (retval
!= ERROR_OK
)
432 //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
440 static int cortex_a8_dpm_prepare(struct arm_dpm
*dpm
)
442 struct cortex_a8_common
*a8
= dpm_to_a8(dpm
);
443 struct adiv5_dap
*swjdp
= a8
->armv7a_common
.armv4_5_common
.dap
;
447 /* set up invariant: INSTR_COMP is set after ever DPM operation */
448 long long then
= timeval_ms();
451 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
452 a8
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
454 if (retval
!= ERROR_OK
)
456 if ((dscr
& DSCR_INSTR_COMP
) != 0)
458 if (timeval_ms() > then
+ 1000)
460 LOG_ERROR("Timeout waiting for dpm prepare");
465 /* this "should never happen" ... */
466 if (dscr
& DSCR_DTR_RX_FULL
) {
467 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
469 retval
= cortex_a8_exec_opcode(
470 a8
->armv7a_common
.armv4_5_common
.target
,
471 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
473 if (retval
!= ERROR_OK
)
480 static int cortex_a8_dpm_finish(struct arm_dpm
*dpm
)
482 /* REVISIT what could be done here? */
486 static int cortex_a8_instr_write_data_dcc(struct arm_dpm
*dpm
,
487 uint32_t opcode
, uint32_t data
)
489 struct cortex_a8_common
*a8
= dpm_to_a8(dpm
);
491 uint32_t dscr
= DSCR_INSTR_COMP
;
493 retval
= cortex_a8_write_dcc(a8
, data
);
494 if (retval
!= ERROR_OK
)
497 return cortex_a8_exec_opcode(
498 a8
->armv7a_common
.armv4_5_common
.target
,
503 static int cortex_a8_instr_write_data_r0(struct arm_dpm
*dpm
,
504 uint32_t opcode
, uint32_t data
)
506 struct cortex_a8_common
*a8
= dpm_to_a8(dpm
);
507 uint32_t dscr
= DSCR_INSTR_COMP
;
510 retval
= cortex_a8_write_dcc(a8
, data
);
511 if (retval
!= ERROR_OK
)
514 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
515 retval
= cortex_a8_exec_opcode(
516 a8
->armv7a_common
.armv4_5_common
.target
,
517 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
519 if (retval
!= ERROR_OK
)
522 /* then the opcode, taking data from R0 */
523 retval
= cortex_a8_exec_opcode(
524 a8
->armv7a_common
.armv4_5_common
.target
,
531 static int cortex_a8_instr_cpsr_sync(struct arm_dpm
*dpm
)
533 struct target
*target
= dpm
->arm
->target
;
534 uint32_t dscr
= DSCR_INSTR_COMP
;
536 /* "Prefetch flush" after modifying execution status in CPSR */
537 return cortex_a8_exec_opcode(target
,
538 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
542 static int cortex_a8_instr_read_data_dcc(struct arm_dpm
*dpm
,
543 uint32_t opcode
, uint32_t *data
)
545 struct cortex_a8_common
*a8
= dpm_to_a8(dpm
);
547 uint32_t dscr
= DSCR_INSTR_COMP
;
549 /* the opcode, writing data to DCC */
550 retval
= cortex_a8_exec_opcode(
551 a8
->armv7a_common
.armv4_5_common
.target
,
554 if (retval
!= ERROR_OK
)
557 return cortex_a8_read_dcc(a8
, data
, &dscr
);
561 static int cortex_a8_instr_read_data_r0(struct arm_dpm
*dpm
,
562 uint32_t opcode
, uint32_t *data
)
564 struct cortex_a8_common
*a8
= dpm_to_a8(dpm
);
565 uint32_t dscr
= DSCR_INSTR_COMP
;
568 /* the opcode, writing data to R0 */
569 retval
= cortex_a8_exec_opcode(
570 a8
->armv7a_common
.armv4_5_common
.target
,
573 if (retval
!= ERROR_OK
)
576 /* write R0 to DCC */
577 retval
= cortex_a8_exec_opcode(
578 a8
->armv7a_common
.armv4_5_common
.target
,
579 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
581 if (retval
!= ERROR_OK
)
584 return cortex_a8_read_dcc(a8
, data
, &dscr
);
587 static int cortex_a8_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
588 uint32_t addr
, uint32_t control
)
590 struct cortex_a8_common
*a8
= dpm_to_a8(dpm
);
591 uint32_t vr
= a8
->armv7a_common
.debug_base
;
592 uint32_t cr
= a8
->armv7a_common
.debug_base
;
596 case 0 ... 15: /* breakpoints */
597 vr
+= CPUDBG_BVR_BASE
;
598 cr
+= CPUDBG_BCR_BASE
;
600 case 16 ... 31: /* watchpoints */
601 vr
+= CPUDBG_WVR_BASE
;
602 cr
+= CPUDBG_WCR_BASE
;
611 LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
612 (unsigned) vr
, (unsigned) cr
);
614 retval
= cortex_a8_dap_write_memap_register_u32(dpm
->arm
->target
,
616 if (retval
!= ERROR_OK
)
618 retval
= cortex_a8_dap_write_memap_register_u32(dpm
->arm
->target
,
623 static int cortex_a8_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
625 struct cortex_a8_common
*a8
= dpm_to_a8(dpm
);
630 cr
= a8
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
633 cr
= a8
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
641 LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr
);
643 /* clear control register */
644 return cortex_a8_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
647 static int cortex_a8_dpm_setup(struct cortex_a8_common
*a8
, uint32_t didr
)
649 struct arm_dpm
*dpm
= &a8
->armv7a_common
.dpm
;
652 dpm
->arm
= &a8
->armv7a_common
.armv4_5_common
;
655 dpm
->prepare
= cortex_a8_dpm_prepare
;
656 dpm
->finish
= cortex_a8_dpm_finish
;
658 dpm
->instr_write_data_dcc
= cortex_a8_instr_write_data_dcc
;
659 dpm
->instr_write_data_r0
= cortex_a8_instr_write_data_r0
;
660 dpm
->instr_cpsr_sync
= cortex_a8_instr_cpsr_sync
;
662 dpm
->instr_read_data_dcc
= cortex_a8_instr_read_data_dcc
;
663 dpm
->instr_read_data_r0
= cortex_a8_instr_read_data_r0
;
665 dpm
->bpwp_enable
= cortex_a8_bpwp_enable
;
666 dpm
->bpwp_disable
= cortex_a8_bpwp_disable
;
668 retval
= arm_dpm_setup(dpm
);
669 if (retval
== ERROR_OK
)
670 retval
= arm_dpm_initialize(dpm
);
677 * Cortex-A8 Run control
680 static int cortex_a8_poll(struct target
*target
)
682 int retval
= ERROR_OK
;
684 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
685 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
686 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
687 enum target_state prev_target_state
= target
->state
;
689 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
690 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
691 if (retval
!= ERROR_OK
)
695 cortex_a8
->cpudbg_dscr
= dscr
;
697 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
))
699 if (prev_target_state
!= TARGET_HALTED
)
701 /* We have a halting debug event */
702 LOG_DEBUG("Target halted");
703 target
->state
= TARGET_HALTED
;
704 if ((prev_target_state
== TARGET_RUNNING
)
705 || (prev_target_state
== TARGET_RESET
))
707 retval
= cortex_a8_debug_entry(target
);
708 if (retval
!= ERROR_OK
)
711 target_call_event_callbacks(target
,
712 TARGET_EVENT_HALTED
);
714 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
718 retval
= cortex_a8_debug_entry(target
);
719 if (retval
!= ERROR_OK
)
722 target_call_event_callbacks(target
,
723 TARGET_EVENT_DEBUG_HALTED
);
727 else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
729 target
->state
= TARGET_RUNNING
;
733 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
734 target
->state
= TARGET_UNKNOWN
;
740 static int cortex_a8_halt(struct target
*target
)
742 int retval
= ERROR_OK
;
744 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
745 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
748 * Tell the core to be halted by writing DRCR with 0x1
749 * and then wait for the core to be halted.
751 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
,
752 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
753 if (retval
!= ERROR_OK
)
757 * enter halting debug mode
759 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
760 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
761 if (retval
!= ERROR_OK
)
764 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
,
765 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
766 if (retval
!= ERROR_OK
)
769 long long then
= timeval_ms();
772 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
773 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
774 if (retval
!= ERROR_OK
)
776 if ((dscr
& DSCR_CORE_HALTED
) != 0)
780 if (timeval_ms() > then
+ 1000)
782 LOG_ERROR("Timeout waiting for halt");
787 target
->debug_reason
= DBG_REASON_DBGRQ
;
792 static int cortex_a8_resume(struct target
*target
, int current
,
793 uint32_t address
, int handle_breakpoints
, int debug_execution
)
795 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
796 struct arm
*armv4_5
= &armv7a
->armv4_5_common
;
797 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
800 // struct breakpoint *breakpoint = NULL;
801 uint32_t resume_pc
, dscr
;
803 if (!debug_execution
)
804 target_free_all_working_areas(target
);
809 /* Disable interrupts */
810 /* We disable interrupts in the PRIMASK register instead of
811 * masking with C_MASKINTS,
812 * This is probably the same issue as Cortex-M3 Errata 377493:
813 * C_MASKINTS in parallel with disabled interrupts can cause
814 * local faults to not be taken. */
815 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
816 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
817 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
819 /* Make sure we are in Thumb mode */
820 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
821 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32) | (1 << 24));
822 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
823 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
827 /* current = 1: continue on current pc, otherwise continue at <address> */
828 resume_pc
= buf_get_u32(armv4_5
->pc
->value
, 0, 32);
832 /* Make sure that the Armv7 gdb thumb fixups does not
833 * kill the return address
835 switch (armv4_5
->core_state
)
838 resume_pc
&= 0xFFFFFFFC;
840 case ARM_STATE_THUMB
:
841 case ARM_STATE_THUMB_EE
:
842 /* When the return address is loaded into PC
843 * bit 0 must be 1 to stay in Thumb state
847 case ARM_STATE_JAZELLE
:
848 LOG_ERROR("How do I resume into Jazelle state??");
851 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
852 buf_set_u32(armv4_5
->pc
->value
, 0, 32, resume_pc
);
853 armv4_5
->pc
->dirty
= 1;
854 armv4_5
->pc
->valid
= 1;
856 retval
= cortex_a8_restore_context(target
, handle_breakpoints
);
857 if (retval
!= ERROR_OK
)
861 /* the front-end may request us not to handle breakpoints */
862 if (handle_breakpoints
)
864 /* Single step past breakpoint at current address */
865 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
867 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
868 cortex_m3_unset_breakpoint(target
, breakpoint
);
869 cortex_m3_single_step_core(target
);
870 cortex_m3_set_breakpoint(target
, breakpoint
);
877 * Restart core and wait for it to be started. Clear ITRen and sticky
878 * exception flags: see ARMv7 ARM, C5.9.
880 * REVISIT: for single stepping, we probably want to
881 * disable IRQs by default, with optional override...
884 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
885 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
886 if (retval
!= ERROR_OK
)
889 if ((dscr
& DSCR_INSTR_COMP
) == 0)
890 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
892 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
,
893 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
894 if (retval
!= ERROR_OK
)
897 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
,
898 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
| DRCR_CLEAR_EXCEPTIONS
);
899 if (retval
!= ERROR_OK
)
902 long long then
= timeval_ms();
905 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
906 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
907 if (retval
!= ERROR_OK
)
909 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
911 if (timeval_ms() > then
+ 1000)
913 LOG_ERROR("Timeout waiting for resume");
918 target
->debug_reason
= DBG_REASON_NOTHALTED
;
919 target
->state
= TARGET_RUNNING
;
921 /* registers are now invalid */
922 register_cache_invalidate(armv4_5
->core_cache
);
924 if (!debug_execution
)
926 target
->state
= TARGET_RUNNING
;
927 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
928 LOG_DEBUG("target resumed at 0x%" PRIx32
, resume_pc
);
932 target
->state
= TARGET_DEBUG_RUNNING
;
933 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
934 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, resume_pc
);
940 static int cortex_a8_debug_entry(struct target
*target
)
943 uint32_t regfile
[16], cpsr
, dscr
;
944 int retval
= ERROR_OK
;
945 struct working_area
*regfile_working_area
= NULL
;
946 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
947 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
948 struct arm
*armv4_5
= &armv7a
->armv4_5_common
;
949 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
952 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a8
->cpudbg_dscr
);
954 /* REVISIT surely we should not re-read DSCR !! */
955 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
956 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
957 if (retval
!= ERROR_OK
)
960 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
961 * imprecise data aborts get discarded by issuing a Data
962 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
965 /* Enable the ITR execution once we are in debug mode */
967 retval
= mem_ap_sel_write_atomic_u32(swjdp
, swjdp_debugap
,
968 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
969 if (retval
!= ERROR_OK
)
972 /* Examine debug reason */
973 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a8
->cpudbg_dscr
);
975 /* save address of instruction that triggered the watchpoint? */
976 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
979 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
980 armv7a
->debug_base
+ CPUDBG_WFAR
,
982 if (retval
!= ERROR_OK
)
984 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
987 /* REVISIT fast_reg_read is never set ... */
989 /* Examine target state and mode */
990 if (cortex_a8
->fast_reg_read
)
991 target_alloc_working_area(target
, 64, ®file_working_area
);
993 /* First load register acessible through core debug port*/
994 if (!regfile_working_area
)
996 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1000 retval
= cortex_a8_read_regs_through_mem(target
,
1001 regfile_working_area
->address
, regfile
);
1003 target_free_working_area(target
, regfile_working_area
);
1004 if (retval
!= ERROR_OK
)
1009 /* read Current PSR */
1010 retval
= cortex_a8_dap_read_coreregister_u32(target
, &cpsr
, 16);
1011 if (retval
!= ERROR_OK
)
1014 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1016 arm_set_cpsr(armv4_5
, cpsr
);
1019 for (i
= 0; i
<= ARM_PC
; i
++)
1021 reg
= arm_reg_current(armv4_5
, i
);
1023 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1028 /* Fixup PC Resume Address */
1029 if (cpsr
& (1 << 5))
1031 // T bit set for Thumb or ThumbEE state
1032 regfile
[ARM_PC
] -= 4;
1037 regfile
[ARM_PC
] -= 8;
1041 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1042 reg
->dirty
= reg
->valid
;
1046 /* TODO, Move this */
1047 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1048 cortex_a8_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1049 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1051 cortex_a8_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1052 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1054 cortex_a8_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1055 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1058 /* Are we in an exception handler */
1059 // armv4_5->exception_number = 0;
1060 if (armv7a
->post_debug_entry
)
1062 retval
= armv7a
->post_debug_entry(target
);
1063 if (retval
!= ERROR_OK
)
1070 static int cortex_a8_post_debug_entry(struct target
*target
)
1072 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
1073 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
1076 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1077 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
1078 0, 0, /* op1, op2 */
1079 1, 0, /* CRn, CRm */
1080 &cortex_a8
->cp15_control_reg
);
1081 if (retval
!= ERROR_OK
)
1083 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a8
->cp15_control_reg
);
1085 if (armv7a
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1087 uint32_t cache_type_reg
;
1089 /* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
1090 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
1091 0, 1, /* op1, op2 */
1092 0, 0, /* CRn, CRm */
1094 if (retval
!= ERROR_OK
)
1096 LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg
);
1098 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
1099 armv4_5_identify_cache(cache_type_reg
,
1100 &armv7a
->armv4_5_mmu
.armv4_5_cache
);
1103 armv7a
->armv4_5_mmu
.mmu_enabled
=
1104 (cortex_a8
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1105 armv7a
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
=
1106 (cortex_a8
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1107 armv7a
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
=
1108 (cortex_a8
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1113 static int cortex_a8_step(struct target
*target
, int current
, uint32_t address
,
1114 int handle_breakpoints
)
1116 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1117 struct arm
*armv4_5
= &armv7a
->armv4_5_common
;
1118 struct breakpoint
*breakpoint
= NULL
;
1119 struct breakpoint stepbreakpoint
;
1123 if (target
->state
!= TARGET_HALTED
)
1125 LOG_WARNING("target not halted");
1126 return ERROR_TARGET_NOT_HALTED
;
1129 /* current = 1: continue on current pc, otherwise continue at <address> */
1133 buf_set_u32(r
->value
, 0, 32, address
);
1137 address
= buf_get_u32(r
->value
, 0, 32);
1140 /* The front-end may request us not to handle breakpoints.
1141 * But since Cortex-A8 uses breakpoint for single step,
1142 * we MUST handle breakpoints.
1144 handle_breakpoints
= 1;
1145 if (handle_breakpoints
) {
1146 breakpoint
= breakpoint_find(target
, address
);
1148 cortex_a8_unset_breakpoint(target
, breakpoint
);
1151 /* Setup single step breakpoint */
1152 stepbreakpoint
.address
= address
;
1153 stepbreakpoint
.length
= (armv4_5
->core_state
== ARM_STATE_THUMB
)
1155 stepbreakpoint
.type
= BKPT_HARD
;
1156 stepbreakpoint
.set
= 0;
1158 /* Break on IVA mismatch */
1159 cortex_a8_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1161 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1163 retval
= cortex_a8_resume(target
, 1, address
, 0, 0);
1164 if (retval
!= ERROR_OK
)
1167 long long then
= timeval_ms();
1168 while (target
->state
!= TARGET_HALTED
)
1170 retval
= cortex_a8_poll(target
);
1171 if (retval
!= ERROR_OK
)
1173 if (timeval_ms() > then
+ 1000)
1175 LOG_ERROR("timeout waiting for target halt");
1180 cortex_a8_unset_breakpoint(target
, &stepbreakpoint
);
1182 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1185 cortex_a8_set_breakpoint(target
, breakpoint
, 0);
1187 if (target
->state
!= TARGET_HALTED
)
1188 LOG_DEBUG("target stepped");
1193 static int cortex_a8_restore_context(struct target
*target
, bool bpwp
)
1195 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1199 if (armv7a
->pre_restore_context
)
1200 armv7a
->pre_restore_context(target
);
1202 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1207 * Cortex-A8 Breakpoint and watchpoint functions
1210 /* Setup hardware Breakpoint Register Pair */
1211 static int cortex_a8_set_breakpoint(struct target
*target
,
1212 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1217 uint8_t byte_addr_select
= 0x0F;
1218 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
1219 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
1220 struct cortex_a8_brp
* brp_list
= cortex_a8
->brp_list
;
1222 if (breakpoint
->set
)
1224 LOG_WARNING("breakpoint already set");
1228 if (breakpoint
->type
== BKPT_HARD
)
1230 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a8
->brp_num
))
1232 if (brp_i
>= cortex_a8
->brp_num
)
1234 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1235 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1237 breakpoint
->set
= brp_i
+ 1;
1238 if (breakpoint
->length
== 2)
1240 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1242 control
= ((matchmode
& 0x7) << 20)
1243 | (byte_addr_select
<< 5)
1245 brp_list
[brp_i
].used
= 1;
1246 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1247 brp_list
[brp_i
].control
= control
;
1248 retval
= cortex_a8_dap_write_memap_register_u32(target
, armv7a
->debug_base
1249 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1250 brp_list
[brp_i
].value
);
1251 if (retval
!= ERROR_OK
)
1253 retval
= cortex_a8_dap_write_memap_register_u32(target
, armv7a
->debug_base
1254 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1255 brp_list
[brp_i
].control
);
1256 if (retval
!= ERROR_OK
)
1258 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1259 brp_list
[brp_i
].control
,
1260 brp_list
[brp_i
].value
);
1262 else if (breakpoint
->type
== BKPT_SOFT
)
1265 if (breakpoint
->length
== 2)
1267 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1271 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1273 retval
= target
->type
->read_memory(target
,
1274 breakpoint
->address
& 0xFFFFFFFE,
1275 breakpoint
->length
, 1,
1276 breakpoint
->orig_instr
);
1277 if (retval
!= ERROR_OK
)
1279 retval
= target
->type
->write_memory(target
,
1280 breakpoint
->address
& 0xFFFFFFFE,
1281 breakpoint
->length
, 1, code
);
1282 if (retval
!= ERROR_OK
)
1284 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1290 static int cortex_a8_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1293 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
1294 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
1295 struct cortex_a8_brp
* brp_list
= cortex_a8
->brp_list
;
1297 if (!breakpoint
->set
)
1299 LOG_WARNING("breakpoint not set");
1303 if (breakpoint
->type
== BKPT_HARD
)
1305 int brp_i
= breakpoint
->set
- 1;
1306 if ((brp_i
< 0) || (brp_i
>= cortex_a8
->brp_num
))
1308 LOG_DEBUG("Invalid BRP number in breakpoint");
1311 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1312 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1313 brp_list
[brp_i
].used
= 0;
1314 brp_list
[brp_i
].value
= 0;
1315 brp_list
[brp_i
].control
= 0;
1316 retval
= cortex_a8_dap_write_memap_register_u32(target
, armv7a
->debug_base
1317 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1318 brp_list
[brp_i
].control
);
1319 if (retval
!= ERROR_OK
)
1321 retval
= cortex_a8_dap_write_memap_register_u32(target
, armv7a
->debug_base
1322 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1323 brp_list
[brp_i
].value
);
1324 if (retval
!= ERROR_OK
)
1329 /* restore original instruction (kept in target endianness) */
1330 if (breakpoint
->length
== 4)
1332 retval
= target
->type
->write_memory(target
,
1333 breakpoint
->address
& 0xFFFFFFFE,
1334 4, 1, breakpoint
->orig_instr
);
1335 if (retval
!= ERROR_OK
)
1340 retval
= target
->type
->write_memory(target
,
1341 breakpoint
->address
& 0xFFFFFFFE,
1342 2, 1, breakpoint
->orig_instr
);
1343 if (retval
!= ERROR_OK
)
1347 breakpoint
->set
= 0;
1352 static int cortex_a8_add_breakpoint(struct target
*target
,
1353 struct breakpoint
*breakpoint
)
1355 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
1357 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a8
->brp_num_available
< 1))
1359 LOG_INFO("no hardware breakpoint available");
1360 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1363 if (breakpoint
->type
== BKPT_HARD
)
1364 cortex_a8
->brp_num_available
--;
1366 return cortex_a8_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1369 static int cortex_a8_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1371 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
1374 /* It is perfectly possible to remove breakpoints while the target is running */
1375 if (target
->state
!= TARGET_HALTED
)
1377 LOG_WARNING("target not halted");
1378 return ERROR_TARGET_NOT_HALTED
;
1382 if (breakpoint
->set
)
1384 cortex_a8_unset_breakpoint(target
, breakpoint
);
1385 if (breakpoint
->type
== BKPT_HARD
)
1386 cortex_a8
->brp_num_available
++ ;
1396 * Cortex-A8 Reset functions
1399 static int cortex_a8_assert_reset(struct target
*target
)
1401 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1405 /* FIXME when halt is requested, make it work somehow... */
1407 /* Issue some kind of warm reset. */
1408 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1409 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1410 } else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1411 /* REVISIT handle "pulls" cases, if there's
1412 * hardware that needs them to work.
1414 jtag_add_reset(0, 1);
1416 LOG_ERROR("%s: how to reset?", target_name(target
));
1420 /* registers are now invalid */
1421 register_cache_invalidate(armv7a
->armv4_5_common
.core_cache
);
1423 target
->state
= TARGET_RESET
;
1428 static int cortex_a8_deassert_reset(struct target
*target
)
1434 /* be certain SRST is off */
1435 jtag_add_reset(0, 0);
1437 retval
= cortex_a8_poll(target
);
1438 if (retval
!= ERROR_OK
)
1441 if (target
->reset_halt
) {
1442 if (target
->state
!= TARGET_HALTED
) {
1443 LOG_WARNING("%s: ran after reset and before halt ...",
1444 target_name(target
));
1445 if ((retval
= target_halt(target
)) != ERROR_OK
)
1453 static int cortex_a8_write_apb_ab_memory(struct target
*target
,
1454 uint32_t address
, uint32_t size
,
1455 uint32_t count
, const uint8_t *buffer
)
1457 int retval
= ERROR_INVALID_ARGUMENTS
;
1458 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1459 struct arm
*armv4_5
= &armv7a
->armv4_5_common
;
1460 int nbytes
= count
* size
;
1464 if (target
->state
!= TARGET_HALTED
)
1466 LOG_WARNING("target not halted");
1467 return ERROR_TARGET_NOT_HALTED
;
1469 reg
= arm_reg_current(armv4_5
, 0);
1471 reg
= arm_reg_current(armv4_5
, 1);
1473 retval
= cortex_a8_dap_write_coreregister_u32(target
, address
, 0);
1474 if (retval
!= ERROR_OK
)
1477 while (nbytes
> 0) {
1479 retval
= cortex_a8_dap_write_coreregister_u32(target
, data
, 1);
1480 if (retval
!= ERROR_OK
)
1483 /* execute instruction STRB r1, [r0], 1 (0xe4c01001) */
1484 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_STRB_IP(1, 0) , NULL
);
1485 if (retval
!= ERROR_OK
)
1493 static int cortex_a8_read_apb_ab_memory(struct target
*target
,
1494 uint32_t address
, uint32_t size
,
1495 uint32_t count
, uint8_t *buffer
)
1497 int retval
= ERROR_INVALID_ARGUMENTS
;
1498 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1499 struct arm
*armv4_5
= &armv7a
->armv4_5_common
;
1500 /* read memory through APB-AP */
1501 int nbytes
= count
* size
;
1505 if (target
->state
!= TARGET_HALTED
)
1507 LOG_WARNING("target not halted");
1508 return ERROR_TARGET_NOT_HALTED
;
1511 reg
= arm_reg_current(armv4_5
, 0);
1513 reg
= arm_reg_current(armv4_5
, 1);
1516 retval
= cortex_a8_dap_write_coreregister_u32(target
, address
, 0);
1517 if (retval
!= ERROR_OK
)
1520 while (nbytes
> 0) {
1523 /* execute instruction LDRB r1, [r0], 1 (0xe4d01001) */
1524 retval
= cortex_a8_exec_opcode(target
, ARMV4_5_LDRB_IP(1, 0) , NULL
);
1525 if (retval
!= ERROR_OK
)
1528 retval
= cortex_a8_dap_read_coreregister_u32(target
, &data
, 1);
1529 if (retval
!= ERROR_OK
)
1542 * Cortex-A8 Memory access
1544 * This is same Cortex M3 but we must also use the correct
1545 * ap number for every access.
1548 static int cortex_a8_read_phys_memory(struct target
*target
,
1549 uint32_t address
, uint32_t size
,
1550 uint32_t count
, uint8_t *buffer
)
1552 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1553 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
1554 int retval
= ERROR_INVALID_ARGUMENTS
;
1555 uint8_t apsel
= swjdp
->apsel
;
1556 LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d",
1557 address
, size
, count
);
1559 if (count
&& buffer
) {
1561 if ( apsel
== swjdp_memoryap
) {
1563 /* read memory through AHB-AP */
1567 retval
= mem_ap_sel_read_buf_u32(swjdp
, swjdp_memoryap
,
1568 buffer
, 4 * count
, address
);
1571 retval
= mem_ap_sel_read_buf_u16(swjdp
, swjdp_memoryap
,
1572 buffer
, 2 * count
, address
);
1575 retval
= mem_ap_sel_read_buf_u8(swjdp
, swjdp_memoryap
,
1576 buffer
, count
, address
);
1582 /* read memory through APB-AP */
1585 retval
= cortex_a8_mmu(target
, &enabled
);
1586 if (retval
!= ERROR_OK
)
1591 LOG_WARNING("Reading physical memory through \
1592 APB with MMU enabled is not yet implemented");
1593 return ERROR_TARGET_FAILURE
;
1595 retval
= cortex_a8_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
1601 static int cortex_a8_read_memory(struct target
*target
, uint32_t address
,
1602 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1605 uint32_t virt
, phys
;
1607 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1608 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
1609 uint8_t apsel
= swjdp
->apsel
;
1611 /* cortex_a8 handles unaligned memory access */
1612 LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address
,
1614 if (apsel
== swjdp_memoryap
) {
1615 retval
= cortex_a8_mmu(target
, &enabled
);
1616 if (retval
!= ERROR_OK
)
1622 retval
= cortex_a8_virt2phys(target
, virt
, &phys
);
1623 if (retval
!= ERROR_OK
)
1626 LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x",
1630 retval
= cortex_a8_read_phys_memory(target
, address
, size
, count
, buffer
);
1632 retval
= cortex_a8_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
1637 static int cortex_a8_write_phys_memory(struct target
*target
,
1638 uint32_t address
, uint32_t size
,
1639 uint32_t count
, const uint8_t *buffer
)
1641 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1642 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
1643 int retval
= ERROR_INVALID_ARGUMENTS
;
1644 uint8_t apsel
= swjdp
->apsel
;
1646 LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address
,
1649 if (count
&& buffer
) {
1651 if ( apsel
== swjdp_memoryap
) {
1653 /* write memory through AHB-AP */
1657 retval
= mem_ap_sel_write_buf_u32(swjdp
, swjdp_memoryap
,
1658 buffer
, 4 * count
, address
);
1661 retval
= mem_ap_sel_write_buf_u16(swjdp
, swjdp_memoryap
,
1662 buffer
, 2 * count
, address
);
1665 retval
= mem_ap_sel_write_buf_u8(swjdp
, swjdp_memoryap
,
1666 buffer
, count
, address
);
1672 /* write memory through APB-AP */
1675 retval
= cortex_a8_mmu(target
, &enabled
);
1676 if (retval
!= ERROR_OK
)
1681 LOG_WARNING("Writing physical memory through APB with MMU" \
1682 "enabled is not yet implemented");
1683 return ERROR_TARGET_FAILURE
;
1685 return cortex_a8_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
1690 /* REVISIT this op is generic ARMv7-A/R stuff */
1691 if (retval
== ERROR_OK
&& target
->state
== TARGET_HALTED
)
1693 struct arm_dpm
*dpm
= armv7a
->armv4_5_common
.dpm
;
1695 retval
= dpm
->prepare(dpm
);
1696 if (retval
!= ERROR_OK
)
1699 /* The Cache handling will NOT work with MMU active, the
1700 * wrong addresses will be invalidated!
1702 * For both ICache and DCache, walk all cache lines in the
1703 * address range. Cortex-A8 has fixed 64 byte line length.
1705 * REVISIT per ARMv7, these may trigger watchpoints ...
1708 /* invalidate I-Cache */
1709 if (armv7a
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
1711 /* ICIMVAU - Invalidate Cache single entry
1713 * MCR p15, 0, r0, c7, c5, 1
1715 for (uint32_t cacheline
= address
;
1716 cacheline
< address
+ size
* count
;
1718 retval
= dpm
->instr_write_data_r0(dpm
,
1719 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
1721 if (retval
!= ERROR_OK
)
1726 /* invalidate D-Cache */
1727 if (armv7a
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
1729 /* DCIMVAC - Invalidate data Cache line
1731 * MCR p15, 0, r0, c7, c6, 1
1733 for (uint32_t cacheline
= address
;
1734 cacheline
< address
+ size
* count
;
1736 retval
= dpm
->instr_write_data_r0(dpm
,
1737 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
1739 if (retval
!= ERROR_OK
)
1744 /* (void) */ dpm
->finish(dpm
);
1750 static int cortex_a8_write_memory(struct target
*target
, uint32_t address
,
1751 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1754 uint32_t virt
, phys
;
1756 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1757 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
1758 uint8_t apsel
= swjdp
->apsel
;
1759 /* cortex_a8 handles unaligned memory access */
1760 LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address
,
1762 if (apsel
== swjdp_memoryap
) {
1764 LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address
, size
, count
);
1765 retval
= cortex_a8_mmu(target
, &enabled
);
1766 if (retval
!= ERROR_OK
)
1772 retval
= cortex_a8_virt2phys(target
, virt
, &phys
);
1773 if (retval
!= ERROR_OK
)
1775 LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt
, phys
);
1779 retval
= cortex_a8_write_phys_memory(target
, address
, size
,
1783 retval
= cortex_a8_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
1788 static int cortex_a8_bulk_write_memory(struct target
*target
, uint32_t address
,
1789 uint32_t count
, const uint8_t *buffer
)
1791 return cortex_a8_write_memory(target
, address
, 4, count
, buffer
);
1795 static int cortex_a8_handle_target_request(void *priv
)
1797 struct target
*target
= priv
;
1798 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1799 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
1802 if (!target_was_examined(target
))
1804 if (!target
->dbg_msg_enabled
)
1807 if (target
->state
== TARGET_RUNNING
)
1811 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1812 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1814 /* check if we have data */
1815 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
==ERROR_OK
))
1817 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1818 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
1819 if (retval
== ERROR_OK
)
1821 target_request(target
, request
);
1822 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1823 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1832 * Cortex-A8 target information and configuration
1835 static int cortex_a8_examine_first(struct target
*target
)
1837 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
1838 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
1839 struct adiv5_dap
*swjdp
= armv7a
->armv4_5_common
.dap
;
1841 int retval
= ERROR_OK
;
1842 uint32_t didr
, ctypr
, ttypr
, cpuid
;
1844 /* We do one extra read to ensure DAP is configured,
1845 * we call ahbap_debugport_init(swjdp) instead
1847 retval
= ahbap_debugport_init(swjdp
);
1848 if (retval
!= ERROR_OK
)
1851 if (!target
->dbgbase_set
)
1854 /* Get ROM Table base */
1856 retval
= dap_get_debugbase(swjdp
, 1, &dbgbase
, &apid
);
1857 if (retval
!= ERROR_OK
)
1859 /* Lookup 0x15 -- Processor DAP */
1860 retval
= dap_lookup_cs_component(swjdp
, 1, dbgbase
, 0x15,
1861 &armv7a
->debug_base
);
1862 if (retval
!= ERROR_OK
)
1867 armv7a
->debug_base
= target
->dbgbase
;
1870 retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1871 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
1872 if (retval
!= ERROR_OK
)
1875 if ((retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1876 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
)) != ERROR_OK
)
1878 LOG_DEBUG("Examine %s failed", "CPUID");
1882 if ((retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1883 armv7a
->debug_base
+ CPUDBG_CTYPR
, &ctypr
)) != ERROR_OK
)
1885 LOG_DEBUG("Examine %s failed", "CTYPR");
1889 if ((retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1890 armv7a
->debug_base
+ CPUDBG_TTYPR
, &ttypr
)) != ERROR_OK
)
1892 LOG_DEBUG("Examine %s failed", "TTYPR");
1896 if ((retval
= mem_ap_sel_read_atomic_u32(swjdp
, swjdp_debugap
,
1897 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
)) != ERROR_OK
)
1899 LOG_DEBUG("Examine %s failed", "DIDR");
1903 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
1904 LOG_DEBUG("ctypr = 0x%08" PRIx32
, ctypr
);
1905 LOG_DEBUG("ttypr = 0x%08" PRIx32
, ttypr
);
1906 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
1908 armv7a
->armv4_5_common
.core_type
= ARM_MODE_MON
;
1909 retval
= cortex_a8_dpm_setup(cortex_a8
, didr
);
1910 if (retval
!= ERROR_OK
)
1913 /* Setup Breakpoint Register Pairs */
1914 cortex_a8
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
1915 cortex_a8
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
1916 cortex_a8
->brp_num_available
= cortex_a8
->brp_num
;
1917 cortex_a8
->brp_list
= calloc(cortex_a8
->brp_num
, sizeof(struct cortex_a8_brp
));
1918 // cortex_a8->brb_enabled = ????;
1919 for (i
= 0; i
< cortex_a8
->brp_num
; i
++)
1921 cortex_a8
->brp_list
[i
].used
= 0;
1922 if (i
< (cortex_a8
->brp_num
-cortex_a8
->brp_num_context
))
1923 cortex_a8
->brp_list
[i
].type
= BRP_NORMAL
;
1925 cortex_a8
->brp_list
[i
].type
= BRP_CONTEXT
;
1926 cortex_a8
->brp_list
[i
].value
= 0;
1927 cortex_a8
->brp_list
[i
].control
= 0;
1928 cortex_a8
->brp_list
[i
].BRPn
= i
;
1931 LOG_DEBUG("Configured %i hw breakpoints", cortex_a8
->brp_num
);
1933 target_set_examined(target
);
1937 static int cortex_a8_examine(struct target
*target
)
1939 int retval
= ERROR_OK
;
1941 /* don't re-probe hardware after each reset */
1942 if (!target_was_examined(target
))
1943 retval
= cortex_a8_examine_first(target
);
1945 /* Configure core debug access */
1946 if (retval
== ERROR_OK
)
1947 retval
= cortex_a8_init_debug_access(target
);
1953 * Cortex-A8 target creation and initialization
1956 static int cortex_a8_init_target(struct command_context
*cmd_ctx
,
1957 struct target
*target
)
1959 /* examine_first() does a bunch of this */
1963 static int cortex_a8_init_arch_info(struct target
*target
,
1964 struct cortex_a8_common
*cortex_a8
, struct jtag_tap
*tap
)
1966 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
1967 struct arm
*armv4_5
= &armv7a
->armv4_5_common
;
1968 struct adiv5_dap
*dap
= &armv7a
->dap
;
1970 armv7a
->armv4_5_common
.dap
= dap
;
1972 /* Setup struct cortex_a8_common */
1973 cortex_a8
->common_magic
= CORTEX_A8_COMMON_MAGIC
;
1974 /* tap has no dap initialized */
1977 armv7a
->armv4_5_common
.dap
= dap
;
1978 /* Setup struct cortex_a8_common */
1979 armv4_5
->arch_info
= armv7a
;
1981 /* prepare JTAG information for the new target */
1982 cortex_a8
->jtag_info
.tap
= tap
;
1983 cortex_a8
->jtag_info
.scann_size
= 4;
1985 /* Leave (only) generic DAP stuff for debugport_init() */
1986 dap
->jtag_info
= &cortex_a8
->jtag_info
;
1987 dap
->memaccess_tck
= 80;
1989 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1990 dap
->tar_autoincr_block
= (1 << 10);
1991 dap
->memaccess_tck
= 80;
1995 armv7a
->armv4_5_common
.dap
= tap
->dap
;
1997 cortex_a8
->fast_reg_read
= 0;
1999 /* Set default value */
2000 cortex_a8
->current_address_mode
= ARM_MODE_ANY
;
2002 /* register arch-specific functions */
2003 armv7a
->examine_debug_reason
= NULL
;
2005 armv7a
->post_debug_entry
= cortex_a8_post_debug_entry
;
2007 armv7a
->pre_restore_context
= NULL
;
2008 armv7a
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
2009 armv7a
->armv4_5_mmu
.get_ttb
= cortex_a8_get_ttb
;
2010 armv7a
->armv4_5_mmu
.read_memory
= cortex_a8_read_phys_memory
;
2011 armv7a
->armv4_5_mmu
.write_memory
= cortex_a8_write_phys_memory
;
2012 armv7a
->armv4_5_mmu
.disable_mmu_caches
= cortex_a8_disable_mmu_caches
;
2013 armv7a
->armv4_5_mmu
.enable_mmu_caches
= cortex_a8_enable_mmu_caches
;
2014 armv7a
->armv4_5_mmu
.has_tiny_pages
= 1;
2015 armv7a
->armv4_5_mmu
.mmu_enabled
= 0;
2018 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
2020 /* REVISIT v7a setup should be in a v7a-specific routine */
2021 arm_init_arch_info(target
, armv4_5
);
2022 armv7a
->common_magic
= ARMV7_COMMON_MAGIC
;
2024 target_register_timer_callback(cortex_a8_handle_target_request
, 1, 1, target
);
2029 static int cortex_a8_target_create(struct target
*target
, Jim_Interp
*interp
)
2031 struct cortex_a8_common
*cortex_a8
= calloc(1, sizeof(struct cortex_a8_common
));
2033 return cortex_a8_init_arch_info(target
, cortex_a8
, target
->tap
);
2036 static int cortex_a8_get_ttb(struct target
*target
, uint32_t *result
)
2038 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
2039 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
2040 uint32_t ttb
= 0, retval
= ERROR_OK
;
2042 /* current_address_mode is set inside cortex_a8_virt2phys()
2043 where we can determine if address belongs to user or kernel */
2044 if(cortex_a8
->current_address_mode
== ARM_MODE_SVC
)
2046 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
2047 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
2048 0, 1, /* op1, op2 */
2049 2, 0, /* CRn, CRm */
2051 if (retval
!= ERROR_OK
)
2054 else if(cortex_a8
->current_address_mode
== ARM_MODE_USR
)
2056 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
2057 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
2058 0, 0, /* op1, op2 */
2059 2, 0, /* CRn, CRm */
2061 if (retval
!= ERROR_OK
)
2064 /* we don't know whose address is: user or kernel
2065 we assume that if we are in kernel mode then
2066 address belongs to kernel else if in user mode
2068 else if(armv7a
->armv4_5_common
.core_mode
== ARM_MODE_SVC
)
2070 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
2071 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
2072 0, 1, /* op1, op2 */
2073 2, 0, /* CRn, CRm */
2075 if (retval
!= ERROR_OK
)
2078 else if(armv7a
->armv4_5_common
.core_mode
== ARM_MODE_USR
)
2080 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
2081 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
2082 0, 0, /* op1, op2 */
2083 2, 0, /* CRn, CRm */
2085 if (retval
!= ERROR_OK
)
2088 /* finally we don't know whose ttb to use: user or kernel */
2090 LOG_ERROR("Don't know how to get ttb for current mode!!!");
2099 static int cortex_a8_disable_mmu_caches(struct target
*target
, int mmu
,
2100 int d_u_cache
, int i_cache
)
2102 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
2103 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
2104 uint32_t cp15_control
;
2107 /* read cp15 control register */
2108 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
2109 0, 0, /* op1, op2 */
2110 1, 0, /* CRn, CRm */
2112 if (retval
!= ERROR_OK
)
2117 cp15_control
&= ~0x1U
;
2120 cp15_control
&= ~0x4U
;
2123 cp15_control
&= ~0x1000U
;
2125 retval
= armv7a
->armv4_5_common
.mcr(target
, 15,
2126 0, 0, /* op1, op2 */
2127 1, 0, /* CRn, CRm */
2132 static int cortex_a8_enable_mmu_caches(struct target
*target
, int mmu
,
2133 int d_u_cache
, int i_cache
)
2135 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
2136 struct armv7a_common
*armv7a
= &cortex_a8
->armv7a_common
;
2137 uint32_t cp15_control
;
2140 /* read cp15 control register */
2141 retval
= armv7a
->armv4_5_common
.mrc(target
, 15,
2142 0, 0, /* op1, op2 */
2143 1, 0, /* CRn, CRm */
2145 if (retval
!= ERROR_OK
)
2149 cp15_control
|= 0x1U
;
2152 cp15_control
|= 0x4U
;
2155 cp15_control
|= 0x1000U
;
2157 retval
= armv7a
->armv4_5_common
.mcr(target
, 15,
2158 0, 0, /* op1, op2 */
2159 1, 0, /* CRn, CRm */
2165 static int cortex_a8_mmu(struct target
*target
, int *enabled
)
2167 if (target
->state
!= TARGET_HALTED
) {
2168 LOG_ERROR("%s: target not halted", __func__
);
2169 return ERROR_TARGET_INVALID
;
2172 *enabled
= target_to_cortex_a8(target
)->armv7a_common
.armv4_5_mmu
.mmu_enabled
;
2176 static int cortex_a8_virt2phys(struct target
*target
,
2177 uint32_t virt
, uint32_t *phys
)
2180 struct cortex_a8_common
*cortex_a8
= target_to_cortex_a8(target
);
2181 // struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
2182 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2184 /* We assume that virtual address is separated
2185 between user and kernel in Linux style:
2186 0x00000000-0xbfffffff - User space
2187 0xc0000000-0xffffffff - Kernel space */
2188 if( virt
< 0xc0000000 ) /* Linux user space */
2189 cortex_a8
->current_address_mode
= ARM_MODE_USR
;
2190 else /* Linux kernel */
2191 cortex_a8
->current_address_mode
= ARM_MODE_SVC
;
2193 int retval
= armv4_5_mmu_translate_va(target
,
2194 &armv7a
->armv4_5_mmu
, virt
, &cb
, &ret
);
2195 if (retval
!= ERROR_OK
)
2197 /* Reset the flag. We don't want someone else to use it by error */
2198 cortex_a8
->current_address_mode
= ARM_MODE_ANY
;
2204 COMMAND_HANDLER(cortex_a8_handle_cache_info_command
)
2206 struct target
*target
= get_current_target(CMD_CTX
);
2207 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2209 return armv4_5_handle_cache_info_command(CMD_CTX
,
2210 &armv7a
->armv4_5_mmu
.armv4_5_cache
);
2214 COMMAND_HANDLER(cortex_a8_handle_dbginit_command
)
2216 struct target
*target
= get_current_target(CMD_CTX
);
2217 if (!target_was_examined(target
))
2219 LOG_ERROR("target not examined yet");
2223 return cortex_a8_init_debug_access(target
);
2226 static const struct command_registration cortex_a8_exec_command_handlers
[] = {
2228 .name
= "cache_info",
2229 .handler
= cortex_a8_handle_cache_info_command
,
2230 .mode
= COMMAND_EXEC
,
2231 .help
= "display information about target caches",
2235 .handler
= cortex_a8_handle_dbginit_command
,
2236 .mode
= COMMAND_EXEC
,
2237 .help
= "Initialize core debug",
2239 COMMAND_REGISTRATION_DONE
2241 static const struct command_registration cortex_a8_command_handlers
[] = {
2243 .chain
= arm_command_handlers
,
2246 .chain
= armv7a_command_handlers
,
2249 .name
= "cortex_a8",
2250 .mode
= COMMAND_ANY
,
2251 .help
= "Cortex-A8 command group",
2252 .chain
= cortex_a8_exec_command_handlers
,
2254 COMMAND_REGISTRATION_DONE
2257 struct target_type cortexa8_target
= {
2258 .name
= "cortex_a8",
2260 .poll
= cortex_a8_poll
,
2261 .arch_state
= armv7a_arch_state
,
2263 .target_request_data
= NULL
,
2265 .halt
= cortex_a8_halt
,
2266 .resume
= cortex_a8_resume
,
2267 .step
= cortex_a8_step
,
2269 .assert_reset
= cortex_a8_assert_reset
,
2270 .deassert_reset
= cortex_a8_deassert_reset
,
2271 .soft_reset_halt
= NULL
,
2273 /* REVISIT allow exporting VFP3 registers ... */
2274 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
2276 .read_memory
= cortex_a8_read_memory
,
2277 .write_memory
= cortex_a8_write_memory
,
2278 .bulk_write_memory
= cortex_a8_bulk_write_memory
,
2280 .checksum_memory
= arm_checksum_memory
,
2281 .blank_check_memory
= arm_blank_check_memory
,
2283 .run_algorithm
= armv4_5_run_algorithm
,
2285 .add_breakpoint
= cortex_a8_add_breakpoint
,
2286 .remove_breakpoint
= cortex_a8_remove_breakpoint
,
2287 .add_watchpoint
= NULL
,
2288 .remove_watchpoint
= NULL
,
2290 .commands
= cortex_a8_command_handlers
,
2291 .target_create
= cortex_a8_target_create
,
2292 .init_target
= cortex_a8_init_target
,
2293 .examine
= cortex_a8_examine
,
2295 .read_phys_memory
= cortex_a8_read_phys_memory
,
2296 .write_phys_memory
= cortex_a8_write_phys_memory
,
2297 .mmu
= cortex_a8_mmu
,
2298 .virt2phys
= cortex_a8_virt2phys
,