1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 /* stm32lx flash register locations */
38 #define FLASH_BASE 0x40023C00
39 #define FLASH_ACR 0x40023C00
40 #define FLASH_PECR 0x40023C04
41 #define FLASH_PDKEYR 0x40023C08
42 #define FLASH_PEKEYR 0x40023C0C
43 #define FLASH_PRGKEYR 0x40023C10
44 #define FLASH_OPTKEYR 0x40023C14
45 #define FLASH_SR 0x40023C18
46 #define FLASH_OBR 0x40023C1C
47 #define FLASH_WRPR 0x40023C20
50 #define FLASH_ACR__LATENCY (1<<0)
51 #define FLASH_ACR__PRFTEN (1<<1)
52 #define FLASH_ACR__ACC64 (1<<2)
53 #define FLASH_ACR__SLEEP_PD (1<<3)
54 #define FLASH_ACR__RUN_PD (1<<4)
57 #define FLASH_PECR__PELOCK (1<<0)
58 #define FLASH_PECR__PRGLOCK (1<<1)
59 #define FLASH_PECR__OPTLOCK (1<<2)
60 #define FLASH_PECR__PROG (1<<3)
61 #define FLASH_PECR__DATA (1<<4)
62 #define FLASH_PECR__FTDW (1<<8)
63 #define FLASH_PECR__ERASE (1<<9)
64 #define FLASH_PECR__FPRG (1<<10)
65 #define FLASH_PECR__EOPIE (1<<16)
66 #define FLASH_PECR__ERRIE (1<<17)
67 #define FLASH_PECR__OBL_LAUNCH (1<<18)
70 #define FLASH_SR__BSY (1<<0)
71 #define FLASH_SR__EOP (1<<1)
72 #define FLASH_SR__ENDHV (1<<2)
73 #define FLASH_SR__READY (1<<3)
74 #define FLASH_SR__WRPERR (1<<8)
75 #define FLASH_SR__PGAERR (1<<9)
76 #define FLASH_SR__SIZERR (1<<10)
77 #define FLASH_SR__OPTVERR (1<<11)
80 #define PEKEY1 0x89ABCDEF
81 #define PEKEY2 0x02030405
82 #define PRGKEY1 0x8C9DAEBF
83 #define PRGKEY2 0x13141516
84 #define OPTKEY1 0xFBEAD9C8
85 #define OPTKEY2 0x24252627
88 #define DBGMCU_IDCODE 0xE0042000
89 #define F_SIZE 0x1FF8004C
92 #define FLASH_PAGE_SIZE 256
93 #define FLASH_SECTOR_SIZE 4096
94 #define FLASH_PAGES_PER_SECTOR 16
95 #define FLASH_BANK0_ADDRESS 0x08000000
97 /* stm32lx option byte register location */
98 #define OB_RDP 0x1FF80000
99 #define OB_USER 0x1FF80004
100 #define OB_WRP0_1 0x1FF80008
101 #define OB_WRP2_3 0x1FF8000C
104 #define OB_RDP__LEVEL0 0xFF5500AA
105 #define OB_RDP__LEVEL1 0xFFFF0000
107 /* stm32lx RCC register locations */
108 #define RCC_CR 0x40023800
109 #define RCC_ICSCR 0x40023804
110 #define RCC_CFGR 0x40023808
113 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
115 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
116 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
117 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
118 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
119 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
121 struct stm32lx_flash_bank
{
122 struct working_area
*write_algorithm
;
126 /* flash bank stm32lx <base> <size> 0 0 <target#>
128 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
130 struct stm32lx_flash_bank
*stm32lx_info
;
132 return ERROR_COMMAND_SYNTAX_ERROR
;
134 /* Create the bank structure */
135 stm32lx_info
= malloc(sizeof(struct stm32lx_flash_bank
));
137 /* Check allocation */
138 if (stm32lx_info
== NULL
) {
139 LOG_ERROR("failed to allocate bank structure");
143 bank
->driver_priv
= stm32lx_info
;
145 stm32lx_info
->write_algorithm
= NULL
;
146 stm32lx_info
->probed
= 0;
151 static int stm32lx_protect_check(struct flash_bank
*bank
)
154 struct target
*target
= bank
->target
;
158 if (target
->state
!= TARGET_HALTED
) {
159 LOG_ERROR("Target not halted");
160 return ERROR_TARGET_NOT_HALTED
;
164 * Read the WRPR word, and check each bit (corresponding to each
167 retval
= target_read_u32(target
, FLASH_WRPR
, &wrpr
);
168 if (retval
!= ERROR_OK
)
171 for (int i
= 0; i
< 32; i
++) {
173 bank
->sectors
[i
].is_protected
= 1;
175 bank
->sectors
[i
].is_protected
= 0;
180 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
185 * It could be possible to do a mass erase if all sectors must be
186 * erased, but it is not implemented yet.
189 if (bank
->target
->state
!= TARGET_HALTED
) {
190 LOG_ERROR("Target not halted");
191 return ERROR_TARGET_NOT_HALTED
;
195 * Loop over the selected sectors and erase them
197 for (int i
= first
; i
<= last
; i
++) {
198 retval
= stm32lx_erase_sector(bank
, i
);
199 if (retval
!= ERROR_OK
)
201 bank
->sectors
[i
].is_erased
= 1;
206 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
209 LOG_WARNING("protection of the STM32L flash is not implemented");
213 static int stm32lx_write_half_pages(struct flash_bank
*bank
, uint8_t *buffer
,
214 uint32_t offset
, uint32_t count
)
216 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
217 struct target
*target
= bank
->target
;
218 uint32_t buffer_size
= 4096 * 4;
219 struct working_area
*source
;
220 uint32_t address
= bank
->base
+ offset
;
222 struct reg_param reg_params
[5];
223 struct armv7m_algorithm armv7m_info
;
225 int retval
= ERROR_OK
;
228 /* see contib/loaders/flash/stm32lx.s for src */
230 static const uint16_t stm32lx_flash_write_code_16
[] = {
231 /* 00000000 <write_word-0x4>: */
232 0x2300, /* 0: 2300 movs r3, #0 */
233 0xe004, /* 2: e004 b.n e <test_done> */
235 /* 00000004 <write_word>: */
236 0xf851, 0xcb04, /* 4: f851 cb04 ldr.w ip, [r1], #4 */
237 0xf840, 0xcb04, /* 8: f840 cb04 str.w ip, [r0], #4 */
238 0x3301, /* c: 3301 adds r3, #1 */
240 /* 0000000e <test_done>: */
241 0x4293, /* e: 4293 cmp r3, r2 */
242 0xd3f8, /* 10: d3f8 bcc.n 4 <write_word> */
243 0xbe00, /* 12: be00 bkpt 0x0000 */
248 uint8_t stm32lx_flash_write_code
[sizeof(stm32lx_flash_write_code_16
)];
249 for (unsigned int i
= 0; i
< sizeof(stm32lx_flash_write_code_16
) / 2; i
++) {
250 stm32lx_flash_write_code
[i
* 2 + 0] = stm32lx_flash_write_code_16
[i
]
252 stm32lx_flash_write_code
[i
* 2 + 1] = (stm32lx_flash_write_code_16
[i
]
255 /* Check if there is an even number of half pages (128bytes) */
257 LOG_ERROR("there should be an even number "
258 "of half pages = 128 bytes (count = %" PRIi32
" bytes)", count
);
262 /* Allocate working area */
263 reg32
= sizeof(stm32lx_flash_write_code
);
264 /* Add bytes to make 4byte aligned */
265 reg32
+= (4 - (reg32
% 4)) % 4;
266 retval
= target_alloc_working_area(target
, reg32
,
267 &stm32lx_info
->write_algorithm
);
268 if (retval
!= ERROR_OK
)
271 /* Write the flashing code */
272 retval
= target_write_buffer(target
,
273 stm32lx_info
->write_algorithm
->address
,
274 sizeof(stm32lx_flash_write_code
),
275 (uint8_t *)stm32lx_flash_write_code
);
276 if (retval
!= ERROR_OK
) {
277 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
281 /* Allocate half pages memory */
282 while (target_alloc_working_area_try(target
, buffer_size
, &source
)
284 if (buffer_size
> 1024)
289 if (buffer_size
<= 256) {
290 /* if we already allocated the writing code, but failed to get a
291 * buffer, free the algorithm */
292 if (stm32lx_info
->write_algorithm
)
293 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
295 LOG_WARNING("no large enough working area available, can't do block memory writes");
296 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
299 LOG_DEBUG("allocated working area for data (%" PRIx32
" bytes)", buffer_size
);
301 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
302 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
303 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
304 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
305 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
306 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
);
307 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
309 /* Enable half-page write */
310 retval
= stm32lx_enable_write_half_page(bank
);
311 if (retval
!= ERROR_OK
) {
312 target_free_working_area(target
, source
);
313 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
315 destroy_reg_param(®_params
[0]);
316 destroy_reg_param(®_params
[1]);
317 destroy_reg_param(®_params
[2]);
318 destroy_reg_param(®_params
[3]);
322 /* Loop while there are bytes to write */
325 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
327 /* Write the next half pages */
328 retval
= target_write_buffer(target
, source
->address
, this_count
,
330 if (retval
!= ERROR_OK
)
333 /* 4: Store useful information in the registers */
334 /* the destination address of the copy (R0) */
335 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
336 /* The source address of the copy (R1) */
337 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
338 /* The length of the copy (R2) */
339 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
341 /* 5: Execute the bunch of code */
342 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
343 / sizeof(*reg_params
), reg_params
,
344 stm32lx_info
->write_algorithm
->address
, 0, 20000, &armv7m_info
);
345 if (retval
!= ERROR_OK
)
348 /* 6: Wait while busy */
349 retval
= stm32lx_wait_until_bsy_clear(bank
);
350 if (retval
!= ERROR_OK
)
353 buffer
+= this_count
;
354 address
+= this_count
;
358 if (retval
== ERROR_OK
)
359 retval
= stm32lx_lock_program_memory(bank
);
361 target_free_working_area(target
, source
);
362 target_free_working_area(target
, stm32lx_info
->write_algorithm
);
364 destroy_reg_param(®_params
[0]);
365 destroy_reg_param(®_params
[1]);
366 destroy_reg_param(®_params
[2]);
367 destroy_reg_param(®_params
[3]);
371 static int stm32lx_write(struct flash_bank
*bank
, uint8_t *buffer
,
372 uint32_t offset
, uint32_t count
)
374 struct target
*target
= bank
->target
;
376 uint32_t halfpages_number
;
377 uint32_t words_remaining
;
378 uint32_t bytes_remaining
;
379 uint32_t address
= bank
->base
+ offset
;
380 uint32_t bytes_written
= 0;
383 if (bank
->target
->state
!= TARGET_HALTED
) {
384 LOG_ERROR("Target not halted");
385 return ERROR_TARGET_NOT_HALTED
;
389 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
390 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
393 /* Check if there are some full half pages */
394 if (((offset
% 128) == 0) && (count
>= 128)) {
395 halfpages_number
= count
/ 128;
396 words_remaining
= (count
- 128 * halfpages_number
) / 4;
397 bytes_remaining
= (count
& 0x3);
399 halfpages_number
= 0;
400 words_remaining
= (count
/ 4);
401 bytes_remaining
= (count
& 0x3);
404 if (halfpages_number
) {
405 retval
= stm32lx_write_half_pages(bank
, buffer
, offset
, 128
407 if (retval
!= ERROR_OK
)
411 bytes_written
= 128 * halfpages_number
;
412 address
+= bytes_written
;
414 retval
= stm32lx_unlock_program_memory(bank
);
415 if (retval
!= ERROR_OK
)
418 while (words_remaining
> 0) {
420 uint8_t *p
= buffer
+ bytes_written
;
422 /* Prepare the word, Little endian conversion */
423 value
= p
[0] + (p
[1] << 8) + (p
[2] << 16) + (p
[3] << 24);
425 retval
= target_write_u32(target
, address
, value
);
426 if (retval
!= ERROR_OK
)
433 retval
= stm32lx_wait_until_bsy_clear(bank
);
434 if (retval
!= ERROR_OK
)
438 if (bytes_remaining
) {
439 uint8_t last_word
[4] = {0xff, 0xff, 0xff, 0xff};
441 /* copy the last remaining bytes into the write buffer */
442 memcpy(last_word
, buffer
+bytes_written
, bytes_remaining
);
444 retval
= target_write_buffer(target
, address
, 4, last_word
);
445 if (retval
!= ERROR_OK
)
448 retval
= stm32lx_wait_until_bsy_clear(bank
);
449 if (retval
!= ERROR_OK
)
453 retval
= stm32lx_lock_program_memory(bank
);
454 if (retval
!= ERROR_OK
)
460 static int stm32lx_probe(struct flash_bank
*bank
)
462 struct target
*target
= bank
->target
;
463 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
465 uint16_t flash_size_in_kb
;
468 stm32lx_info
->probed
= 0;
470 /* read stm32 device id register */
471 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
472 if (retval
!= ERROR_OK
)
475 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
477 /* get flash size from target. */
478 retval
= target_read_u16(target
, F_SIZE
, &flash_size_in_kb
);
479 if (retval
!= ERROR_OK
) {
480 LOG_WARNING("failed reading flash size, default to max target family");
481 /* failed reading flash size, default to max target family */
482 flash_size_in_kb
= 0xffff;
485 /* some variants read 0 for flash size register
486 * use a max flash size as a default */
487 if (flash_size_in_kb
== 0)
488 flash_size_in_kb
= 0xffff;
490 if ((device_id
& 0xfff) == 0x416) {
491 /* check for early silicon */
492 if (flash_size_in_kb
== 0xffff) {
493 /* number of sectors may be incorrrect on early silicon */
494 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
495 flash_size_in_kb
= 128;
497 } else if ((device_id
& 0xfff) == 0x436) {
498 /* check for early silicon */
499 if (flash_size_in_kb
== 0xffff) {
500 /* number of sectors may be incorrrect on early silicon */
501 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 384k flash");
502 flash_size_in_kb
= 384;
505 LOG_WARNING("Cannot identify target as a STM32L family.");
509 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
510 * 16 pages for a protection area */
512 /* calculate numbers of sectors (4kB per sector) */
513 int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
514 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
518 bank
->sectors
= NULL
;
521 bank
->base
= FLASH_BANK0_ADDRESS
;
522 bank
->size
= flash_size_in_kb
* 1024;
523 bank
->num_sectors
= num_sectors
;
524 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
525 if (bank
->sectors
== NULL
) {
526 LOG_ERROR("failed to allocate bank sectors");
530 for (i
= 0; i
< num_sectors
; i
++) {
531 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
532 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
533 bank
->sectors
[i
].is_erased
= -1;
534 bank
->sectors
[i
].is_protected
= 1;
537 stm32lx_info
->probed
= 1;
542 static int stm32lx_auto_probe(struct flash_bank
*bank
)
544 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
546 if (stm32lx_info
->probed
)
549 return stm32lx_probe(bank
);
552 static int stm32lx_erase_check(struct flash_bank
*bank
)
554 struct target
*target
= bank
->target
;
555 const int buffer_size
= 4096;
558 int retval
= ERROR_OK
;
560 if (bank
->target
->state
!= TARGET_HALTED
) {
561 LOG_ERROR("Target not halted");
562 return ERROR_TARGET_NOT_HALTED
;
565 uint8_t *buffer
= malloc(buffer_size
);
566 if (buffer
== NULL
) {
567 LOG_ERROR("failed to allocate read buffer");
571 for (i
= 0; i
< bank
->num_sectors
; i
++) {
573 bank
->sectors
[i
].is_erased
= 1;
575 /* Loop chunk by chunk over the sector */
576 for (j
= 0; j
< bank
->sectors
[i
].size
; j
+= buffer_size
) {
579 if (chunk
> (j
- bank
->sectors
[i
].size
))
580 chunk
= (j
- bank
->sectors
[i
].size
);
582 retval
= target_read_memory(target
, bank
->base
583 + bank
->sectors
[i
].offset
+ j
, 4, chunk
/ 4, buffer
);
584 if (retval
!= ERROR_OK
)
587 for (nBytes
= 0; nBytes
< chunk
; nBytes
++) {
588 if (buffer
[nBytes
] != 0x00) {
589 bank
->sectors
[i
].is_erased
= 0;
594 if (retval
!= ERROR_OK
)
602 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
604 /* This method must return a string displaying information about the bank */
606 struct target
*target
= bank
->target
;
610 /* read stm32 device id register */
611 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
612 if (retval
!= ERROR_OK
)
615 if ((device_id
& 0xfff) == 0x416) {
616 printed
= snprintf(buf
, buf_size
, "stm32lx - Rev: ");
620 switch (device_id
>> 16) {
622 snprintf(buf
, buf_size
, "A");
626 snprintf(buf
, buf_size
, "Y");
630 snprintf(buf
, buf_size
, "X");
634 snprintf(buf
, buf_size
, "W");
638 snprintf(buf
, buf_size
, "V");
642 snprintf(buf
, buf_size
, "unknown");
645 } else if ((device_id
& 0xfff) == 0x436) {
646 printed
= snprintf(buf
, buf_size
, "stm32lx (HD) - Rev: ");
650 switch (device_id
>> 16) {
652 snprintf(buf
, buf_size
, "A");
656 snprintf(buf
, buf_size
, "Z");
660 snprintf(buf
, buf_size
, "unknown");
664 snprintf(buf
, buf_size
, "Cannot identify target as a stm32lx");
671 static const struct command_registration stm32lx_exec_command_handlers
[] = {
672 COMMAND_REGISTRATION_DONE
675 static const struct command_registration stm32lx_command_handlers
[] = {
679 .help
= "stm32lx flash command group",
681 .chain
= stm32lx_exec_command_handlers
,
683 COMMAND_REGISTRATION_DONE
686 struct flash_driver stm32lx_flash
= {
688 .commands
= stm32lx_command_handlers
,
689 .flash_bank_command
= stm32lx_flash_bank_command
,
690 .erase
= stm32lx_erase
,
691 .protect
= stm32lx_protect
,
692 .write
= stm32lx_write
,
693 .read
= default_flash_read
,
694 .probe
= stm32lx_probe
,
695 .auto_probe
= stm32lx_auto_probe
,
696 .erase_check
= stm32lx_erase_check
,
697 .protect_check
= stm32lx_protect_check
,
698 .info
= stm32lx_get_info
,
701 /* Static methods implementation */
702 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
704 struct target
*target
= bank
->target
;
709 * Unlocking the program memory is done by unlocking the PECR,
710 * then by writing the 2 PRGKEY to the PRGKEYR register
713 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
714 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY1
);
715 if (retval
!= ERROR_OK
)
718 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY2
);
719 if (retval
!= ERROR_OK
)
722 /* Make sure it worked */
723 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
724 if (retval
!= ERROR_OK
)
727 if (reg32
& FLASH_PECR__PELOCK
) {
728 LOG_ERROR("PELOCK is not cleared :(");
729 return ERROR_FLASH_OPERATION_FAILED
;
732 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY1
);
733 if (retval
!= ERROR_OK
)
735 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY2
);
736 if (retval
!= ERROR_OK
)
739 /* Make sure it worked */
740 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
741 if (retval
!= ERROR_OK
)
744 if (reg32
& FLASH_PECR__PRGLOCK
) {
745 LOG_ERROR("PRGLOCK is not cleared :(");
746 return ERROR_FLASH_OPERATION_FAILED
;
751 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
753 struct target
*target
= bank
->target
;
758 * Unlock the program memory, then set the FPRG bit in the PECR register.
760 retval
= stm32lx_unlock_program_memory(bank
);
761 if (retval
!= ERROR_OK
)
764 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
765 if (retval
!= ERROR_OK
)
768 reg32
|= FLASH_PECR__FPRG
;
769 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
770 if (retval
!= ERROR_OK
)
773 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
774 if (retval
!= ERROR_OK
)
777 reg32
|= FLASH_PECR__PROG
;
778 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
783 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
785 struct target
*target
= bank
->target
;
789 /* To lock the program memory, simply set the lock bit and lock PECR */
791 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
792 if (retval
!= ERROR_OK
)
795 reg32
|= FLASH_PECR__PRGLOCK
;
796 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
797 if (retval
!= ERROR_OK
)
800 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
801 if (retval
!= ERROR_OK
)
804 reg32
|= FLASH_PECR__PELOCK
;
805 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
806 if (retval
!= ERROR_OK
)
812 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
814 struct target
*target
= bank
->target
;
819 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
820 * first unlock the memory, loop over the pages of this sector
821 * and write 0x0 to its first word.
824 retval
= stm32lx_unlock_program_memory(bank
);
825 if (retval
!= ERROR_OK
)
828 for (int page
= 0; page
< FLASH_PAGES_PER_SECTOR
; page
++) {
829 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
830 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
831 if (retval
!= ERROR_OK
)
834 retval
= stm32lx_wait_until_bsy_clear(bank
);
835 if (retval
!= ERROR_OK
)
838 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
840 retval
= target_write_u32(target
, addr
, 0x0);
841 if (retval
!= ERROR_OK
)
844 retval
= stm32lx_wait_until_bsy_clear(bank
);
845 if (retval
!= ERROR_OK
)
849 retval
= stm32lx_lock_program_memory(bank
);
850 if (retval
!= ERROR_OK
)
856 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
858 struct target
*target
= bank
->target
;
860 int retval
= ERROR_OK
;
863 /* wait for busy to clear */
865 retval
= target_read_u32(target
, FLASH_SR
, &status
);
866 if (retval
!= ERROR_OK
)
869 if ((status
& FLASH_SR__BSY
) == 0)
871 if (timeout
-- <= 0) {
872 LOG_ERROR("timed out waiting for flash");
878 if (status
& FLASH_SR__WRPERR
) {
879 LOG_ERROR("access denied / write protected");
883 if (status
& FLASH_SR__PGAERR
) {
884 LOG_ERROR("invalid program address");