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ARM: rename some generic routines
[openocd.git] / src / target / arm920t.c
blob217c63c6a7443612e02b05f950175ca65984fe46
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include <helper/time_support.h>
26 #include "target_type.h"
27 #include "register.h"
28 #include "arm_opcodes.h"
29
30
31 /*
32 * For information about the ARM920T, see ARM DDI 0151C especially
33 * Chapter 9 about debug support, which shows how to manipulate each
34 * of the different scan chains:
35 *
36 * 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
37 * 1 ... debugging; watchpoint and breakpoint status, etc; also
38 * MMU and cache access in conjunction with scan chain 15
39 * 2 ... EmbeddedICE
40 * 3 ... external boundary scan (SoC-specific, unused here)
41 * 4 ... access to cache tag RAM
42 * 6 ... ETM9
43 * 15 ... access coprocessor 15, "physical" or "interpreted" modes
44 * "interpreted" works with a few actual MRC/MCR instructions
45 * "physical" provides register-like behaviors.
46 *
47 * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
48 */
49
50 #if 0
51 #define _DEBUG_INSTRUCTION_EXECUTION_
52 #endif
53
54 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
55
56 static int arm920t_read_cp15_physical(struct target *target,
57 int reg_addr, uint32_t *value)
58 {
59 struct arm920t_common *arm920t = target_to_arm920(target);
60 struct arm_jtag *jtag_info;
61 struct scan_field fields[4];
62 uint8_t access_type_buf = 1;
63 uint8_t reg_addr_buf = reg_addr & 0x3f;
64 uint8_t nr_w_buf = 0;
65
66 jtag_info = &arm920t->arm7_9_common.jtag_info;
67
68 jtag_set_end_state(TAP_IDLE);
69 arm_jtag_scann(jtag_info, 0xf);
70 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
71
72 fields[0].tap = jtag_info->tap;
73 fields[0].num_bits = 1;
74 fields[0].out_value = &access_type_buf;
75 fields[0].in_value = NULL;
76
77 fields[1].tap = jtag_info->tap;
78 fields[1].num_bits = 32;
79 fields[1].out_value = NULL;
80 fields[1].in_value = NULL;
81
82 fields[2].tap = jtag_info->tap;
83 fields[2].num_bits = 6;
84 fields[2].out_value = &reg_addr_buf;
85 fields[2].in_value = NULL;
86
87 fields[3].tap = jtag_info->tap;
88 fields[3].num_bits = 1;
89 fields[3].out_value = &nr_w_buf;
90 fields[3].in_value = NULL;
91
92 jtag_add_dr_scan(4, fields, jtag_get_end_state());
93
94 fields[1].in_value = (uint8_t *)value;
95
96 jtag_add_dr_scan(4, fields, jtag_get_end_state());
97
98 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
99
100 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
101 jtag_execute_queue();
102 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
103 #endif
104
105 return ERROR_OK;
106 }
107
108 static int arm920t_write_cp15_physical(struct target *target,
109 int reg_addr, uint32_t value)
110 {
111 struct arm920t_common *arm920t = target_to_arm920(target);
112 struct arm_jtag *jtag_info;
113 struct scan_field fields[4];
114 uint8_t access_type_buf = 1;
115 uint8_t reg_addr_buf = reg_addr & 0x3f;
116 uint8_t nr_w_buf = 1;
117 uint8_t value_buf[4];
118
119 jtag_info = &arm920t->arm7_9_common.jtag_info;
120
121 buf_set_u32(value_buf, 0, 32, value);
122
123 jtag_set_end_state(TAP_IDLE);
124 arm_jtag_scann(jtag_info, 0xf);
125 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
126
127 fields[0].tap = jtag_info->tap;
128 fields[0].num_bits = 1;
129 fields[0].out_value = &access_type_buf;
130 fields[0].in_value = NULL;
131
132 fields[1].tap = jtag_info->tap;
133 fields[1].num_bits = 32;
134 fields[1].out_value = value_buf;
135 fields[1].in_value = NULL;
136
137 fields[2].tap = jtag_info->tap;
138 fields[2].num_bits = 6;
139 fields[2].out_value = &reg_addr_buf;
140 fields[2].in_value = NULL;
141
142 fields[3].tap = jtag_info->tap;
143 fields[3].num_bits = 1;
144 fields[3].out_value = &nr_w_buf;
145 fields[3].in_value = NULL;
146
147 jtag_add_dr_scan(4, fields, jtag_get_end_state());
148
149 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
150 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
151 #endif
152
153 return ERROR_OK;
154 }
155
156 static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
157 uint32_t arm_opcode)
158 {
159 int retval;
160 struct arm920t_common *arm920t = target_to_arm920(target);
161 struct arm_jtag *jtag_info;
162 struct scan_field fields[4];
163 uint8_t access_type_buf = 0; /* interpreted access */
164 uint8_t reg_addr_buf = 0x0;
165 uint8_t nr_w_buf = 0;
166 uint8_t cp15_opcode_buf[4];
167
168 jtag_info = &arm920t->arm7_9_common.jtag_info;
169
170 jtag_set_end_state(TAP_IDLE);
171 arm_jtag_scann(jtag_info, 0xf);
172 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
173
174 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
175
176 fields[0].tap = jtag_info->tap;
177 fields[0].num_bits = 1;
178 fields[0].out_value = &access_type_buf;
179 fields[0].in_value = NULL;
180
181 fields[1].tap = jtag_info->tap;
182 fields[1].num_bits = 32;
183 fields[1].out_value = cp15_opcode_buf;
184 fields[1].in_value = NULL;
185
186 fields[2].tap = jtag_info->tap;
187 fields[2].num_bits = 6;
188 fields[2].out_value = &reg_addr_buf;
189 fields[2].in_value = NULL;
190
191 fields[3].tap = jtag_info->tap;
192 fields[3].num_bits = 1;
193 fields[3].out_value = &nr_w_buf;
194 fields[3].in_value = NULL;
195
196 jtag_add_dr_scan(4, fields, jtag_get_end_state());
197
198 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
199 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
200 retval = arm7_9_execute_sys_speed(target);
201 if (retval != ERROR_OK)
202 return retval;
203
204 if ((retval = jtag_execute_queue()) != ERROR_OK)
205 {
206 LOG_ERROR("failed executing JTAG queue");
207 return retval;
208 }
209
210 return ERROR_OK;
211 }
212
213 static int arm920t_read_cp15_interpreted(struct target *target,
214 uint32_t cp15_opcode, uint32_t address, uint32_t *value)
215 {
216 struct arm *armv4_5 = target_to_arm(target);
217 uint32_t* regs_p[1];
218 uint32_t regs[2];
219 uint32_t cp15c15 = 0x0;
220 struct reg *r = armv4_5->core_cache->reg_list;
221
222 /* load address into R1 */
223 regs[1] = address;
224 arm9tdmi_write_core_regs(target, 0x2, regs);
225
226 /* read-modify-write CP15 test state register
227 * to enable interpreted access mode */
228 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
229 jtag_execute_queue();
230 cp15c15 |= 1; /* set interpret mode */
231 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
232
233 /* execute CP15 instruction and ARM load (reading from coprocessor) */
234 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
235
236 /* disable interpreted access mode */
237 cp15c15 &= ~1U; /* clear interpret mode */
238 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
239
240 /* retrieve value from R0 */
241 regs_p[0] = value;
242 arm9tdmi_read_core_regs(target, 0x1, regs_p);
243 jtag_execute_queue();
244
245 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
246 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
247 #endif
248
249 if (!is_arm_mode(armv4_5->core_mode))
250 return ERROR_FAIL;
251
252 r[0].dirty = 1;
253 r[1].dirty = 1;
254
255 return ERROR_OK;
256 }
257
258 static
259 int arm920t_write_cp15_interpreted(struct target *target,
260 uint32_t cp15_opcode, uint32_t value, uint32_t address)
261 {
262 uint32_t cp15c15 = 0x0;
263 struct arm *armv4_5 = target_to_arm(target);
264 uint32_t regs[2];
265 struct reg *r = armv4_5->core_cache->reg_list;
266
267 /* load value, address into R0, R1 */
268 regs[0] = value;
269 regs[1] = address;
270 arm9tdmi_write_core_regs(target, 0x3, regs);
271
272 /* read-modify-write CP15 test state register
273 * to enable interpreted access mode */
274 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
275 jtag_execute_queue();
276 cp15c15 |= 1; /* set interpret mode */
277 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
278
279 /* execute CP15 instruction and ARM store (writing to coprocessor) */
280 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
281
282 /* disable interpreted access mode */
283 cp15c15 &= ~1U; /* set interpret mode */
284 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
285
286 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
287 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
288 #endif
289
290 if (!is_arm_mode(armv4_5->core_mode))
291 return ERROR_FAIL;
292
293 r[0].dirty = 1;
294 r[1].dirty = 1;
295
296 return ERROR_OK;
297 }
298
299 // EXPORTED to FA256
300 uint32_t arm920t_get_ttb(struct target *target)
301 {
302 int retval;
303 uint32_t ttb = 0x0;
304
305 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
306 return retval;
307
308 return ttb;
309 }
310
311 // EXPORTED to FA256
312 void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
313 {
314 uint32_t cp15_control;
315
316 /* read cp15 control register */
317 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
318 jtag_execute_queue();
319
320 if (mmu)
321 cp15_control &= ~0x1U;
322
323 if (d_u_cache)
324 cp15_control &= ~0x4U;
325
326 if (i_cache)
327 cp15_control &= ~0x1000U;
328
329 arm920t_write_cp15_physical(target, 0x2, cp15_control);
330 }
331
332 // EXPORTED to FA256
333 void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
334 {
335 uint32_t cp15_control;
336
337 /* read cp15 control register */
338 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
339 jtag_execute_queue();
340
341 if (mmu)
342 cp15_control |= 0x1U;
343
344 if (d_u_cache)
345 cp15_control |= 0x4U;
346
347 if (i_cache)
348 cp15_control |= 0x1000U;
349
350 arm920t_write_cp15_physical(target, 0x2, cp15_control);
351 }
352
353 // EXPORTED to FA256
354 void arm920t_post_debug_entry(struct target *target)
355 {
356 uint32_t cp15c15;
357 struct arm920t_common *arm920t = target_to_arm920(target);
358
359 /* examine cp15 control reg */
360 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
361 jtag_execute_queue();
362 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
363
364 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
365 {
366 uint32_t cache_type_reg;
367 /* identify caches */
368 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
369 jtag_execute_queue();
370 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
371 }
372
373 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
374 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
375 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
376
377 /* save i/d fault status and address register */
378 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
379 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
380 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
381 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
382
383 LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
384 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
385
386 if (arm920t->preserve_cache)
387 {
388 /* read-modify-write CP15 test state register
389 * to disable I/D-cache linefills */
390 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
391 jtag_execute_queue();
392 cp15c15 |= 0x600;
393 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
394 }
395 }
396
397 // EXPORTED to FA256
398 void arm920t_pre_restore_context(struct target *target)
399 {
400 uint32_t cp15c15;
401 struct arm920t_common *arm920t = target_to_arm920(target);
402
403 /* restore i/d fault status and address register */
404 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
405 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
406 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
407 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
408
409 /* read-modify-write CP15 test state register
410 * to reenable I/D-cache linefills */
411 if (arm920t->preserve_cache)
412 {
413 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
414 jtag_execute_queue();
415 cp15c15 &= ~0x600U;
416 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
417 }
418 }
419
420 static const char arm920_not[] = "target is not an ARM920";
421
422 static int arm920t_verify_pointer(struct command_context *cmd_ctx,
423 struct arm920t_common *arm920t)
424 {
425 if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
426 command_print(cmd_ctx, arm920_not);
427 return ERROR_TARGET_INVALID;
428 }
429
430 return ERROR_OK;
431 }
432
433 /** Logs summary of ARM920 state for a halted target. */
434 int arm920t_arch_state(struct target *target)
435 {
436 static const char *state[] =
437 {
438 "disabled", "enabled"
439 };
440
441 struct arm920t_common *arm920t = target_to_arm920(target);
442 struct arm *armv4_5;
443
444 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
445 {
446 LOG_ERROR("BUG: %s", arm920_not);
447 return ERROR_TARGET_INVALID;
448 }
449
450 armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
451
452 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
453 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
454 "MMU: %s, D-Cache: %s, I-Cache: %s",
455 arm_state_strings[armv4_5->core_state],
456 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
457 arm_mode_name(armv4_5->core_mode),
458 buf_get_u32(armv4_5->cpsr->value, 0, 32),
459 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
460 state[arm920t->armv4_5_mmu.mmu_enabled],
461 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
462 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
463
464 return ERROR_OK;
465 }
466
467 static int arm920_mmu(struct target *target, int *enabled)
468 {
469 if (target->state != TARGET_HALTED) {
470 LOG_ERROR("%s: target not halted", __func__);
471 return ERROR_TARGET_INVALID;
472 }
473
474 *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled;
475 return ERROR_OK;
476 }
477
478 static int arm920_virt2phys(struct target *target,
479 uint32_t virt, uint32_t *phys)
480 {
481 /** @todo Implement this! */
482 LOG_ERROR("%s: not implemented", __func__);
483 return ERROR_FAIL;
484 }
485
486 /** Reads a buffer, in the specified word size, with current MMU settings. */
487 int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
488 {
489 int retval;
490
491 retval = arm7_9_read_memory(target, address, size, count, buffer);
492
493 return retval;
494 }
495
496
497 static int arm920t_read_phys_memory(struct target *target,
498 uint32_t address, uint32_t size,
499 uint32_t count, uint8_t *buffer)
500 {
501 struct arm920t_common *arm920t = target_to_arm920(target);
502
503 return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu,
504 address, size, count, buffer);
505 }
506
507 static int arm920t_write_phys_memory(struct target *target,
508 uint32_t address, uint32_t size,
509 uint32_t count, uint8_t *buffer)
510 {
511 struct arm920t_common *arm920t = target_to_arm920(target);
512
513 return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
514 address, size, count, buffer);
515 }
516
517
518 /** Writes a buffer, in the specified word size, with current MMU settings. */
519 int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
520 {
521 int retval;
522
523 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
524 return retval;
525
526 /* This fn is used to write breakpoints, so we need to make sure
527 * that the data cache is flushed and the instruction cache is
528 * invalidated
529 */
530 if (((size == 4) || (size == 2)) && (count == 1))
531 {
532 struct arm920t_common *arm920t = target_to_arm920(target);
533
534 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
535 {
536 LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
537 /* MCR p15,0,Rd,c7,c10,2 */
538 retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
539 if (retval != ERROR_OK)
540 return retval;
541 }
542
543 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
544 {
545 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
546 retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
547 if (retval != ERROR_OK)
548 return retval;
549 }
550 }
551
552 return retval;
553 }
554
555 // EXPORTED to FA256
556 int arm920t_soft_reset_halt(struct target *target)
557 {
558 int retval = ERROR_OK;
559 struct arm920t_common *arm920t = target_to_arm920(target);
560 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
561 struct arm *armv4_5 = &arm7_9->armv4_5_common;
562 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
563
564 if ((retval = target_halt(target)) != ERROR_OK)
565 {
566 return retval;
567 }
568
569 long long then = timeval_ms();
570 int timeout;
571 while (!(timeout = ((timeval_ms()-then) > 1000)))
572 {
573 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
574 {
575 embeddedice_read_reg(dbg_stat);
576 if ((retval = jtag_execute_queue()) != ERROR_OK)
577 {
578 return retval;
579 }
580 } else
581 {
582 break;
583 }
584 if (debug_level >= 3)
585 {
586 /* do not eat all CPU, time out after 1 se*/
587 alive_sleep(100);
588 } else
589 {
590 keep_alive();
591 }
592 }
593 if (timeout)
594 {
595 LOG_ERROR("Failed to halt CPU after 1 sec");
596 return ERROR_TARGET_TIMEOUT;
597 }
598
599 target->state = TARGET_HALTED;
600
601 /* SVC, ARM state, IRQ and FIQ disabled */
602 uint32_t cpsr;
603
604 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
605 cpsr &= ~0xff;
606 cpsr |= 0xd3;
607 arm_set_cpsr(armv4_5, cpsr);
608 armv4_5->cpsr->dirty = 1;
609
610 /* start fetching from 0x0 */
611 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
612 armv4_5->core_cache->reg_list[15].dirty = 1;
613 armv4_5->core_cache->reg_list[15].valid = 1;
614
615 arm920t_disable_mmu_caches(target, 1, 1, 1);
616 arm920t->armv4_5_mmu.mmu_enabled = 0;
617 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
618 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
619
620 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
621 {
622 return retval;
623 }
624
625 return ERROR_OK;
626 }
627
628 /* FIXME remove forward decls */
629 static int arm920t_mrc(struct target *target, int cpnum,
630 uint32_t op1, uint32_t op2,
631 uint32_t CRn, uint32_t CRm,
632 uint32_t *value);
633 static int arm920t_mcr(struct target *target, int cpnum,
634 uint32_t op1, uint32_t op2,
635 uint32_t CRn, uint32_t CRm,
636 uint32_t value);
637
638 int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
639 {
640 struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
641
642 arm7_9->armv4_5_common.mrc = arm920t_mrc;
643 arm7_9->armv4_5_common.mcr = arm920t_mcr;
644
645 /* initialize arm7/arm9 specific info (including armv4_5) */
646 arm9tdmi_init_arch_info(target, arm7_9, tap);
647
648 arm920t->common_magic = ARM920T_COMMON_MAGIC;
649
650 arm7_9->post_debug_entry = arm920t_post_debug_entry;
651 arm7_9->pre_restore_context = arm920t_pre_restore_context;
652
653 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
654 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
655 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
656 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
657 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
658 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
659 arm920t->armv4_5_mmu.has_tiny_pages = 1;
660 arm920t->armv4_5_mmu.mmu_enabled = 0;
661
662 /* disabling linefills leads to lockups, so keep them enabled for now
663 * this doesn't affect correctness, but might affect timing issues, if
664 * important data is evicted from the cache during the debug session
665 * */
666 arm920t->preserve_cache = 0;
667
668 /* override hw single-step capability from ARM9TDMI */
669 arm7_9->has_single_step = 1;
670
671 return ERROR_OK;
672 }
673
674 static int arm920t_target_create(struct target *target, Jim_Interp *interp)
675 {
676 struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
677
678 return arm920t_init_arch_info(target, arm920t, target->tap);
679 }
680
681 COMMAND_HANDLER(arm920t_handle_read_cache_command)
682 {
683 int retval = ERROR_OK;
684 struct target *target = get_current_target(CMD_CTX);
685 struct arm920t_common *arm920t = target_to_arm920(target);
686 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
687 struct arm *armv4_5 = &arm7_9->armv4_5_common;
688 uint32_t cp15c15;
689 uint32_t cp15_ctrl, cp15_ctrl_saved;
690 uint32_t regs[16];
691 uint32_t *regs_p[16];
692 uint32_t C15_C_D_Ind, C15_C_I_Ind;
693 int i;
694 FILE *output;
695 struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
696 int segment, index;
697 struct reg *r;
698
699 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
700 if (retval != ERROR_OK)
701 return retval;
702
703 if (CMD_ARGC != 1)
704 {
705 command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
706 return ERROR_OK;
707 }
708
709 if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
710 {
711 LOG_DEBUG("error opening cache content file");
712 return ERROR_OK;
713 }
714
715 for (i = 0; i < 16; i++)
716 regs_p[i] = &regs[i];
717
718 /* disable MMU and Caches */
719 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
720 if ((retval = jtag_execute_queue()) != ERROR_OK)
721 {
722 return retval;
723 }
724 cp15_ctrl_saved = cp15_ctrl;
725 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
726 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
727
728 /* read CP15 test state register */
729 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
730 jtag_execute_queue();
731
732 /* read DCache content */
733 fprintf(output, "DCache:\n");
734
735 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
736 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
737 {
738 fprintf(output, "\nsegment: %i\n----------", segment);
739
740 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
741 regs[0] = 0x0 | (segment << 5);
742 arm9tdmi_write_core_regs(target, 0x1, regs);
743
744 /* set interpret mode */
745 cp15c15 |= 0x1;
746 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
747
748 /* D CAM Read, loads current victim into C15.C.D.Ind */
749 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
750
751 /* read current victim */
752 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
753
754 /* clear interpret mode */
755 cp15c15 &= ~0x1;
756 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
757
758 for (index = 0; index < 64; index++)
759 {
760 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
761 regs[0] = 0x0 | (segment << 5) | (index << 26);
762 arm9tdmi_write_core_regs(target, 0x1, regs);
763
764 /* set interpret mode */
765 cp15c15 |= 0x1;
766 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
767
768 /* Write DCache victim */
769 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
770
771 /* Read D RAM */
772 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
773
774 /* Read D CAM */
775 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
776
777 /* clear interpret mode */
778 cp15c15 &= ~0x1;
779 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
780
781 /* read D RAM and CAM content */
782 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
783 if ((retval = jtag_execute_queue()) != ERROR_OK)
784 {
785 return retval;
786 }
787
788 d_cache[segment][index].cam = regs[9];
789
790 /* mask LFSR[6] */
791 regs[9] &= 0xfffffffe;
792 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
793
794 for (i = 1; i < 9; i++)
795 {
796 d_cache[segment][index].data[i] = regs[i];
797 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
798 }
799
800 }
801
802 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
803 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
804 arm9tdmi_write_core_regs(target, 0x1, regs);
805
806 /* set interpret mode */
807 cp15c15 |= 0x1;
808 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
809
810 /* Write DCache victim */
811 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
812
813 /* clear interpret mode */
814 cp15c15 &= ~0x1;
815 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
816 }
817
818 /* read ICache content */
819 fprintf(output, "ICache:\n");
820
821 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
822 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
823 {
824 fprintf(output, "segment: %i\n----------", segment);
825
826 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
827 regs[0] = 0x0 | (segment << 5);
828 arm9tdmi_write_core_regs(target, 0x1, regs);
829
830 /* set interpret mode */
831 cp15c15 |= 0x1;
832 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
833
834 /* I CAM Read, loads current victim into C15.C.I.Ind */
835 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
836
837 /* read current victim */
838 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
839
840 /* clear interpret mode */
841 cp15c15 &= ~0x1;
842 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
843
844 for (index = 0; index < 64; index++)
845 {
846 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
847 regs[0] = 0x0 | (segment << 5) | (index << 26);
848 arm9tdmi_write_core_regs(target, 0x1, regs);
849
850 /* set interpret mode */
851 cp15c15 |= 0x1;
852 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
853
854 /* Write ICache victim */
855 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
856
857 /* Read I RAM */
858 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
859
860 /* Read I CAM */
861 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
862
863 /* clear interpret mode */
864 cp15c15 &= ~0x1;
865 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
866
867 /* read I RAM and CAM content */
868 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
869 if ((retval = jtag_execute_queue()) != ERROR_OK)
870 {
871 return retval;
872 }
873
874 i_cache[segment][index].cam = regs[9];
875
876 /* mask LFSR[6] */
877 regs[9] &= 0xfffffffe;
878 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
879
880 for (i = 1; i < 9; i++)
881 {
882 i_cache[segment][index].data[i] = regs[i];
883 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
884 }
885 }
886
887 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
888 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
889 arm9tdmi_write_core_regs(target, 0x1, regs);
890
891 /* set interpret mode */
892 cp15c15 |= 0x1;
893 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
894
895 /* Write ICache victim */
896 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
897
898 /* clear interpret mode */
899 cp15c15 &= ~0x1;
900 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
901 }
902
903 /* restore CP15 MMU and Cache settings */
904 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
905
906 command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
907
908 fclose(output);
909
910 if (!is_arm_mode(armv4_5->core_mode))
911 return ERROR_FAIL;
912
913 /* force writeback of the valid data */
914 r = armv4_5->core_cache->reg_list;
915 r[0].dirty = r[0].valid;
916 r[1].dirty = r[1].valid;
917 r[2].dirty = r[2].valid;
918 r[3].dirty = r[3].valid;
919 r[4].dirty = r[4].valid;
920 r[5].dirty = r[5].valid;
921 r[6].dirty = r[6].valid;
922 r[7].dirty = r[7].valid;
923
924 r = arm_reg_current(armv4_5, 8);
925 r->dirty = r->valid;
926
927 r = arm_reg_current(armv4_5, 9);
928 r->dirty = r->valid;
929
930 return ERROR_OK;
931 }
932
933 COMMAND_HANDLER(arm920t_handle_read_mmu_command)
934 {
935 int retval = ERROR_OK;
936 struct target *target = get_current_target(CMD_CTX);
937 struct arm920t_common *arm920t = target_to_arm920(target);
938 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
939 struct arm *armv4_5 = &arm7_9->armv4_5_common;
940 uint32_t cp15c15;
941 uint32_t cp15_ctrl, cp15_ctrl_saved;
942 uint32_t regs[16];
943 uint32_t *regs_p[16];
944 int i;
945 FILE *output;
946 uint32_t Dlockdown, Ilockdown;
947 struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
948 int victim;
949 struct reg *r;
950
951 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
952 if (retval != ERROR_OK)
953 return retval;
954
955 if (CMD_ARGC != 1)
956 {
957 command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
958 return ERROR_OK;
959 }
960
961 if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
962 {
963 LOG_DEBUG("error opening mmu content file");
964 return ERROR_OK;
965 }
966
967 for (i = 0; i < 16; i++)
968 regs_p[i] = &regs[i];
969
970 /* disable MMU and Caches */
971 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
972 if ((retval = jtag_execute_queue()) != ERROR_OK)
973 {
974 return retval;
975 }
976 cp15_ctrl_saved = cp15_ctrl;
977 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
978 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
979
980 /* read CP15 test state register */
981 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
982 if ((retval = jtag_execute_queue()) != ERROR_OK)
983 {
984 return retval;
985 }
986
987 /* prepare reading D TLB content
988 * */
989
990 /* set interpret mode */
991 cp15c15 |= 0x1;
992 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
993
994 /* Read D TLB lockdown */
995 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
996
997 /* clear interpret mode */
998 cp15c15 &= ~0x1;
999 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1000
1001 /* read D TLB lockdown stored to r1 */
1002 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1003 if ((retval = jtag_execute_queue()) != ERROR_OK)
1004 {
1005 return retval;
1006 }
1007 Dlockdown = regs[1];
1008
1009 for (victim = 0; victim < 64; victim += 8)
1010 {
1011 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1012 * base remains unchanged, victim goes through entries 0 to 63 */
1013 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1014 arm9tdmi_write_core_regs(target, 0x2, regs);
1015
1016 /* set interpret mode */
1017 cp15c15 |= 0x1;
1018 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1019
1020 /* Write D TLB lockdown */
1021 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1022
1023 /* Read D TLB CAM */
1024 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1025
1026 /* clear interpret mode */
1027 cp15c15 &= ~0x1;
1028 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1029
1030 /* read D TLB CAM content stored to r2-r9 */
1031 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1032 if ((retval = jtag_execute_queue()) != ERROR_OK)
1033 {
1034 return retval;
1035 }
1036
1037 for (i = 0; i < 8; i++)
1038 d_tlb[victim + i].cam = regs[i + 2];
1039 }
1040
1041 for (victim = 0; victim < 64; victim++)
1042 {
1043 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1044 * base remains unchanged, victim goes through entries 0 to 63 */
1045 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1046 arm9tdmi_write_core_regs(target, 0x2, regs);
1047
1048 /* set interpret mode */
1049 cp15c15 |= 0x1;
1050 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1051
1052 /* Write D TLB lockdown */
1053 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1054
1055 /* Read D TLB RAM1 */
1056 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1057
1058 /* Read D TLB RAM2 */
1059 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1060
1061 /* clear interpret mode */
1062 cp15c15 &= ~0x1;
1063 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1064
1065 /* read D TLB RAM content stored to r2 and r3 */
1066 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1067 if ((retval = jtag_execute_queue()) != ERROR_OK)
1068 {
1069 return retval;
1070 }
1071
1072 d_tlb[victim].ram1 = regs[2];
1073 d_tlb[victim].ram2 = regs[3];
1074 }
1075
1076 /* restore D TLB lockdown */
1077 regs[1] = Dlockdown;
1078 arm9tdmi_write_core_regs(target, 0x2, regs);
1079
1080 /* Write D TLB lockdown */
1081 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1082
1083 /* prepare reading I TLB content
1084 * */
1085
1086 /* set interpret mode */
1087 cp15c15 |= 0x1;
1088 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1089
1090 /* Read I TLB lockdown */
1091 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1092
1093 /* clear interpret mode */
1094 cp15c15 &= ~0x1;
1095 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1096
1097 /* read I TLB lockdown stored to r1 */
1098 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1099 if ((retval = jtag_execute_queue()) != ERROR_OK)
1100 {
1101 return retval;
1102 }
1103 Ilockdown = regs[1];
1104
1105 for (victim = 0; victim < 64; victim += 8)
1106 {
1107 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1108 * base remains unchanged, victim goes through entries 0 to 63 */
1109 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1110 arm9tdmi_write_core_regs(target, 0x2, regs);
1111
1112 /* set interpret mode */
1113 cp15c15 |= 0x1;
1114 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1115
1116 /* Write I TLB lockdown */
1117 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1118
1119 /* Read I TLB CAM */
1120 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1121
1122 /* clear interpret mode */
1123 cp15c15 &= ~0x1;
1124 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1125
1126 /* read I TLB CAM content stored to r2-r9 */
1127 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1128 if ((retval = jtag_execute_queue()) != ERROR_OK)
1129 {
1130 return retval;
1131 }
1132
1133 for (i = 0; i < 8; i++)
1134 i_tlb[i + victim].cam = regs[i + 2];
1135 }
1136
1137 for (victim = 0; victim < 64; victim++)
1138 {
1139 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1140 * base remains unchanged, victim goes through entries 0 to 63 */
1141 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1142 arm9tdmi_write_core_regs(target, 0x2, regs);
1143
1144 /* set interpret mode */
1145 cp15c15 |= 0x1;
1146 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1147
1148 /* Write I TLB lockdown */
1149 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1150
1151 /* Read I TLB RAM1 */
1152 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1153
1154 /* Read I TLB RAM2 */
1155 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1156
1157 /* clear interpret mode */
1158 cp15c15 &= ~0x1;
1159 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1160
1161 /* read I TLB RAM content stored to r2 and r3 */
1162 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1163 if ((retval = jtag_execute_queue()) != ERROR_OK)
1164 {
1165 return retval;
1166 }
1167
1168 i_tlb[victim].ram1 = regs[2];
1169 i_tlb[victim].ram2 = regs[3];
1170 }
1171
1172 /* restore I TLB lockdown */
1173 regs[1] = Ilockdown;
1174 arm9tdmi_write_core_regs(target, 0x2, regs);
1175
1176 /* Write I TLB lockdown */
1177 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1178
1179 /* restore CP15 MMU and Cache settings */
1180 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1181
1182 /* output data to file */
1183 fprintf(output, "D TLB content:\n");
1184 for (i = 0; i < 64; i++)
1185 {
1186 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1187 }
1188
1189 fprintf(output, "\n\nI TLB content:\n");
1190 for (i = 0; i < 64; i++)
1191 {
1192 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1193 }
1194
1195 command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
1196
1197 fclose(output);
1198
1199 if (!is_arm_mode(armv4_5->core_mode))
1200 return ERROR_FAIL;
1201
1202 /* force writeback of the valid data */
1203 r = armv4_5->core_cache->reg_list;
1204 r[0].dirty = r[0].valid;
1205 r[1].dirty = r[1].valid;
1206 r[2].dirty = r[2].valid;
1207 r[3].dirty = r[3].valid;
1208 r[4].dirty = r[4].valid;
1209 r[5].dirty = r[5].valid;
1210 r[6].dirty = r[6].valid;
1211 r[7].dirty = r[7].valid;
1212
1213 r = arm_reg_current(armv4_5, 8);
1214 r->dirty = r->valid;
1215
1216 r = arm_reg_current(armv4_5, 9);
1217 r->dirty = r->valid;
1218
1219 return ERROR_OK;
1220 }
1221
1222 COMMAND_HANDLER(arm920t_handle_cp15_command)
1223 {
1224 int retval;
1225 struct target *target = get_current_target(CMD_CTX);
1226 struct arm920t_common *arm920t = target_to_arm920(target);
1227
1228 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1229 if (retval != ERROR_OK)
1230 return retval;
1231
1232 if (target->state != TARGET_HALTED)
1233 {
1234 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1235 return ERROR_OK;
1236 }
1237
1238 /* one or more argument, access a single register (write if second argument is given */
1239 if (CMD_ARGC >= 1)
1240 {
1241 int address;
1242 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
1243
1244 if (CMD_ARGC == 1)
1245 {
1246 uint32_t value;
1247 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1248 {
1249 command_print(CMD_CTX, "couldn't access reg %i", address);
1250 return ERROR_OK;
1251 }
1252 if ((retval = jtag_execute_queue()) != ERROR_OK)
1253 {
1254 return retval;
1255 }
1256
1257 command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1258 }
1259 else if (CMD_ARGC == 2)
1260 {
1261 uint32_t value;
1262 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1263 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1264 {
1265 command_print(CMD_CTX, "couldn't access reg %i", address);
1266 return ERROR_OK;
1267 }
1268 command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1269 }
1270 }
1271
1272 return ERROR_OK;
1273 }
1274
1275 COMMAND_HANDLER(arm920t_handle_cp15i_command)
1276 {
1277 int retval;
1278 struct target *target = get_current_target(CMD_CTX);
1279 struct arm920t_common *arm920t = target_to_arm920(target);
1280
1281 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1282 if (retval != ERROR_OK)
1283 return retval;
1284
1285
1286 if (target->state != TARGET_HALTED)
1287 {
1288 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1289 return ERROR_OK;
1290 }
1291
1292 /* one or more argument, access a single register (write if second argument is given */
1293 if (CMD_ARGC >= 1)
1294 {
1295 uint32_t opcode;
1296 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
1297
1298 if (CMD_ARGC == 1)
1299 {
1300 uint32_t value;
1301 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1302 {
1303 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1304 return ERROR_OK;
1305 }
1306
1307 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1308 }
1309 else if (CMD_ARGC == 2)
1310 {
1311 uint32_t value;
1312 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1313 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1314 {
1315 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1316 return ERROR_OK;
1317 }
1318 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1319 }
1320 else if (CMD_ARGC == 3)
1321 {
1322 uint32_t value;
1323 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1324 uint32_t address;
1325 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
1326 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1327 {
1328 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1329 return ERROR_OK;
1330 }
1331 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
1332 }
1333 }
1334 else
1335 {
1336 command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
1337 }
1338
1339 return ERROR_OK;
1340 }
1341
1342 COMMAND_HANDLER(arm920t_handle_cache_info_command)
1343 {
1344 int retval;
1345 struct target *target = get_current_target(CMD_CTX);
1346 struct arm920t_common *arm920t = target_to_arm920(target);
1347
1348 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1349 if (retval != ERROR_OK)
1350 return retval;
1351
1352 return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
1353 }
1354
1355
1356 static int arm920t_mrc(struct target *target, int cpnum,
1357 uint32_t op1, uint32_t op2,
1358 uint32_t CRn, uint32_t CRm,
1359 uint32_t *value)
1360 {
1361 if (cpnum!=15)
1362 {
1363 LOG_ERROR("Only cp15 is supported");
1364 return ERROR_FAIL;
1365 }
1366
1367 /* read "to" r0 */
1368 return arm920t_read_cp15_interpreted(target,
1369 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
1370 0, value);
1371 }
1372
1373 static int arm920t_mcr(struct target *target, int cpnum,
1374 uint32_t op1, uint32_t op2,
1375 uint32_t CRn, uint32_t CRm,
1376 uint32_t value)
1377 {
1378 if (cpnum!=15)
1379 {
1380 LOG_ERROR("Only cp15 is supported");
1381 return ERROR_FAIL;
1382 }
1383
1384 /* write "from" r0 */
1385 return arm920t_write_cp15_interpreted(target,
1386 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
1387 0, value);
1388 }
1389
1390 static const struct command_registration arm920t_exec_command_handlers[] = {
1391 {
1392 .name = "cp15",
1393 .handler = &arm920t_handle_cp15_command,
1394 .mode = COMMAND_EXEC,
1395 .help = "display/modify cp15 register",
1396 .usage = "<num> [value]",
1397 },
1398 {
1399 .name = "cp15i",
1400 .handler = &arm920t_handle_cp15i_command,
1401 .mode = COMMAND_EXEC,
1402 .help = "display/modify cp15 (interpreted access)",
1403 .usage = "<opcode> [value] [address]",
1404 },
1405 {
1406 .name = "cache_info",
1407 .handler = &arm920t_handle_cache_info_command,
1408 .mode = COMMAND_EXEC,
1409 .help = "display information about target caches",
1410 },
1411 {
1412 .name = "read_cache",
1413 .handler = &arm920t_handle_read_cache_command,
1414 .mode = COMMAND_EXEC,
1415 .help = "display I/D cache content",
1416 },
1417 {
1418 .name = "read_mmu",
1419 .handler = &arm920t_handle_read_mmu_command,
1420 .mode = COMMAND_EXEC,
1421 .help = "display I/D mmu content",
1422 },
1423 COMMAND_REGISTRATION_DONE
1424 };
1425 const struct command_registration arm920t_command_handlers[] = {
1426 {
1427 .chain = arm9tdmi_command_handlers,
1428 },
1429 {
1430 .name = "arm920t",
1431 .mode = COMMAND_ANY,
1432 .help = "arm920t command group",
1433 .chain = arm920t_exec_command_handlers,
1434 },
1435 COMMAND_REGISTRATION_DONE
1436 };
1437
1438 /** Holds methods for ARM920 targets. */
1439 struct target_type arm920t_target =
1440 {
1441 .name = "arm920t",
1442
1443 .poll = arm7_9_poll,
1444 .arch_state = arm920t_arch_state,
1445
1446 .target_request_data = arm7_9_target_request_data,
1447
1448 .halt = arm7_9_halt,
1449 .resume = arm7_9_resume,
1450 .step = arm7_9_step,
1451
1452 .assert_reset = arm7_9_assert_reset,
1453 .deassert_reset = arm7_9_deassert_reset,
1454 .soft_reset_halt = arm920t_soft_reset_halt,
1455
1456 .get_gdb_reg_list = arm_get_gdb_reg_list,
1457
1458 .read_memory = arm920t_read_memory,
1459 .write_memory = arm920t_write_memory,
1460 .read_phys_memory = arm920t_read_phys_memory,
1461 .write_phys_memory = arm920t_write_phys_memory,
1462 .mmu = arm920_mmu,
1463 .virt2phys = arm920_virt2phys,
1464
1465 .bulk_write_memory = arm7_9_bulk_write_memory,
1466
1467 .checksum_memory = arm_checksum_memory,
1468 .blank_check_memory = arm_blank_check_memory,
1469
1470 .run_algorithm = armv4_5_run_algorithm,
1471
1472 .add_breakpoint = arm7_9_add_breakpoint,
1473 .remove_breakpoint = arm7_9_remove_breakpoint,
1474 .add_watchpoint = arm7_9_add_watchpoint,
1475 .remove_watchpoint = arm7_9_remove_watchpoint,
1476
1477 .commands = arm920t_command_handlers,
1478 .target_create = arm920t_target_create,
1479 .init_target = arm9tdmi_init_target,
1480 .examine = arm7_9_examine,
1481 };
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