1 /***************************************************************************
2 * Copyright (C) 2009-2011 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "target_type.h"
30 #include "dsp563xx_once.h"
32 #define ASM_REG_W_R0 0x60F400
33 #define ASM_REG_W_R1 0x61F400
34 #define ASM_REG_W_R2 0x62F400
35 #define ASM_REG_W_R3 0x63F400
36 #define ASM_REG_W_R4 0x64F400
37 #define ASM_REG_W_R5 0x65F400
38 #define ASM_REG_W_R6 0x66F400
39 #define ASM_REG_W_R7 0x67F400
41 #define ASM_REG_W_N0 0x70F400
42 #define ASM_REG_W_N1 0x71F400
43 #define ASM_REG_W_N2 0x72F400
44 #define ASM_REG_W_N3 0x73F400
45 #define ASM_REG_W_N4 0x74F400
46 #define ASM_REG_W_N5 0x75F400
47 #define ASM_REG_W_N6 0x76F400
48 #define ASM_REG_W_N7 0x77F400
50 #define ASM_REG_W_M0 0x05F420
51 #define ASM_REG_W_M1 0x05F421
52 #define ASM_REG_W_M2 0x05F422
53 #define ASM_REG_W_M3 0x05F423
54 #define ASM_REG_W_M4 0x05F424
55 #define ASM_REG_W_M5 0x05F425
56 #define ASM_REG_W_M6 0x05F426
57 #define ASM_REG_W_M7 0x05F427
59 #define ASM_REG_W_X0 0x44F400
60 #define ASM_REG_W_X1 0x45F400
62 #define ASM_REG_W_Y0 0x46F400
63 #define ASM_REG_W_Y1 0x47F400
65 #define ASM_REG_W_A0 0x50F400
66 #define ASM_REG_W_A1 0x54F400
67 #define ASM_REG_W_A2 0x52F400
69 #define ASM_REG_W_B0 0x51F400
70 #define ASM_REG_W_B1 0x55F400
71 #define ASM_REG_W_B2 0x53F400
73 #define ASM_REG_W_VBA 0x05F430
74 #define ASM_REG_W_OMR 0x05F43A
75 #define ASM_REG_W_EP 0x05F42A
76 #define ASM_REG_W_SC 0x05F431
77 #define ASM_REG_W_SZ 0x05F438
78 #define ASM_REG_W_SR 0x05F439
79 #define ASM_REG_W_SP 0x05F43B
80 #define ASM_REG_W_SSH 0x05F43C
81 #define ASM_REG_W_SSL 0x05F43D
82 #define ASM_REG_W_LA 0x05F43E
83 #define ASM_REG_W_LC 0x05F43F
84 #define ASM_REG_W_PC 0x000000
85 #define ASM_REG_W_IPRC 0xFFFFFF
86 #define ASM_REG_W_IPRP 0xFFFFFE
88 #define ASM_REG_W_BCR 0xFFFFFB
89 #define ASM_REG_W_DCR 0xFFFFFA
90 #define ASM_REG_W_AAR0 0xFFFFF9
91 #define ASM_REG_W_AAR1 0xFFFFF8
92 #define ASM_REG_W_AAR2 0xFFFFF7
93 #define ASM_REG_W_AAR3 0xFFFFF6
100 ONCE_REG_IDX_OMLR1
=4,
101 ONCE_REG_IDX_OGDBR
=5,
102 ONCE_REG_IDX_OPDBR
=6,
103 ONCE_REG_IDX_OPILR
=7,
106 ONCE_REG_IDX_OPABFR
=10,
107 ONCE_REG_IDX_OPABDR
=11,
108 ONCE_REG_IDX_OPABEX
=12,
109 ONCE_REG_IDX_OPABF0
=13,
110 ONCE_REG_IDX_OPABF1
=14,
111 ONCE_REG_IDX_OPABF2
=15,
112 ONCE_REG_IDX_OPABF3
=16,
113 ONCE_REG_IDX_OPABF4
=17,
114 ONCE_REG_IDX_OPABF5
=18,
115 ONCE_REG_IDX_OPABF6
=19,
116 ONCE_REG_IDX_OPABF7
=20,
117 ONCE_REG_IDX_OPABF8
=21,
118 ONCE_REG_IDX_OPABF9
=22,
119 ONCE_REG_IDX_OPABF10
=23,
120 ONCE_REG_IDX_OPABF11
=24,
123 static struct once_reg once_regs
[] = {
124 {ONCE_REG_IDX_OSCR
, DSP563XX_ONCE_OSCR
, 24, "OSCR", 0},
125 {ONCE_REG_IDX_OMBC
, DSP563XX_ONCE_OMBC
, 24, "OMBC", 0},
126 {ONCE_REG_IDX_OBCR
, DSP563XX_ONCE_OBCR
, 24, "OBCR", 0},
127 {ONCE_REG_IDX_OMLR0
, DSP563XX_ONCE_OMLR0
, 24, "OMLR0", 0},
128 {ONCE_REG_IDX_OMLR1
, DSP563XX_ONCE_OMLR1
, 24, "OMLR1", 0},
129 {ONCE_REG_IDX_OGDBR
, DSP563XX_ONCE_OGDBR
, 24, "OGDBR", 0},
130 {ONCE_REG_IDX_OPDBR
, DSP563XX_ONCE_OPDBR
, 24, "OPDBR", 0},
131 {ONCE_REG_IDX_OPILR
, DSP563XX_ONCE_OPILR
, 24, "OPILR", 0},
132 {ONCE_REG_IDX_PDB
, DSP563XX_ONCE_PDBGOTO
, 24, "PDB", 0},
133 {ONCE_REG_IDX_OTC
, DSP563XX_ONCE_OTC
, 24, "OTC", 0},
134 {ONCE_REG_IDX_OPABFR
, DSP563XX_ONCE_OPABFR
, 24, "OPABFR", 0},
135 {ONCE_REG_IDX_OPABDR
, DSP563XX_ONCE_OPABDR
, 24, "OPABDR", 0},
136 {ONCE_REG_IDX_OPABEX
, DSP563XX_ONCE_OPABEX
, 24, "OPABEX", 0},
137 {ONCE_REG_IDX_OPABF0
, DSP563XX_ONCE_OPABF11
, 25, "OPABF0", 0},
138 {ONCE_REG_IDX_OPABF1
, DSP563XX_ONCE_OPABF11
, 25, "OPABF1", 0},
139 {ONCE_REG_IDX_OPABF2
, DSP563XX_ONCE_OPABF11
, 25, "OPABF2", 0},
140 {ONCE_REG_IDX_OPABF3
, DSP563XX_ONCE_OPABF11
, 25, "OPABF3", 0},
141 {ONCE_REG_IDX_OPABF4
, DSP563XX_ONCE_OPABF11
, 25, "OPABF4", 0},
142 {ONCE_REG_IDX_OPABF5
, DSP563XX_ONCE_OPABF11
, 25, "OPABF5", 0},
143 {ONCE_REG_IDX_OPABF6
, DSP563XX_ONCE_OPABF11
, 25, "OPABF6", 0},
144 {ONCE_REG_IDX_OPABF7
, DSP563XX_ONCE_OPABF11
, 25, "OPABF7", 0},
145 {ONCE_REG_IDX_OPABF8
, DSP563XX_ONCE_OPABF11
, 25, "OPABF8", 0},
146 {ONCE_REG_IDX_OPABF9
, DSP563XX_ONCE_OPABF11
, 25, "OPABF9", 0},
147 {ONCE_REG_IDX_OPABF10
, DSP563XX_ONCE_OPABF11
, 25, "OPABF10", 0},
148 {ONCE_REG_IDX_OPABF11
, DSP563XX_ONCE_OPABF11
, 25, "OPABF11", 0},
149 // {25,0x1f,24,"NRSEL",0},
157 /* effective addressing mode encoding */
163 /* address registers */
164 { 0, "r0", 24, 0x10, ASM_REG_W_R0
},
165 { 1, "r1", 24, 0x11, ASM_REG_W_R1
},
166 { 2, "r2", 24, 0x12, ASM_REG_W_R2
},
167 { 3, "r3", 24, 0x13, ASM_REG_W_R3
},
168 { 4, "r4", 24, 0x14, ASM_REG_W_R4
},
169 { 5, "r5", 24, 0x15, ASM_REG_W_R5
},
170 { 6, "r6", 24, 0x16, ASM_REG_W_R6
},
171 { 7, "r7", 24, 0x17, ASM_REG_W_R7
},
172 /* offset registers */
173 { 8, "n0", 24, 0x18, ASM_REG_W_N0
},
174 { 9, "n1", 24, 0x19, ASM_REG_W_N1
},
175 {10, "n2", 24, 0x1a, ASM_REG_W_N2
},
176 {11, "n3", 24, 0x1b, ASM_REG_W_N3
},
177 {12, "n4", 24, 0x1c, ASM_REG_W_N4
},
178 {13, "n5", 24, 0x1d, ASM_REG_W_N5
},
179 {14, "n6", 24, 0x1e, ASM_REG_W_N6
},
180 {15, "n7", 24, 0x1f, ASM_REG_W_N7
},
181 /* modifier registers */
182 {16, "m0", 24, 0x20, ASM_REG_W_M0
},
183 {17, "m1", 24, 0x21, ASM_REG_W_M1
},
184 {18, "m2", 24, 0x22, ASM_REG_W_M2
},
185 {19, "m3", 24, 0x23, ASM_REG_W_M3
},
186 {20, "m4", 24, 0x24, ASM_REG_W_M4
},
187 {21, "m5", 24, 0x25, ASM_REG_W_M5
},
188 {22, "m6", 24, 0x26, ASM_REG_W_M6
},
189 {23, "m7", 24, 0x27, ASM_REG_W_M7
},
190 /* data alu input register */
191 {24, "x0", 24, 0x04, ASM_REG_W_X0
},
192 {25, "x1", 24, 0x05, ASM_REG_W_X1
},
193 {26, "y0", 24, 0x06, ASM_REG_W_Y0
},
194 {27, "y1", 24, 0x07, ASM_REG_W_Y1
},
195 /* data alu accumulator register */
196 {28, "a0", 24, 0x08, ASM_REG_W_A0
},
197 {29, "a1", 24, 0x0c, ASM_REG_W_A1
},
198 {30, "a2", 8, 0x0a, ASM_REG_W_A2
},
199 {31, "b0", 24, 0x09, ASM_REG_W_B0
},
200 {32, "b1", 24, 0x0d, ASM_REG_W_B1
},
201 {33, "b2", 8, 0x0b, ASM_REG_W_B2
},
203 {34, "ssh",24, 0x3c, ASM_REG_W_SSH
},
204 {35, "ssl",24, 0x3d, ASM_REG_W_SSL
},
205 {36, "sp", 24, 0x3b, ASM_REG_W_SP
},
206 {37, "ep", 24, 0x2a, ASM_REG_W_EP
},
207 {38, "sz", 24, 0x38, ASM_REG_W_SZ
},
208 {39, "sc", 24, 0x31, ASM_REG_W_SC
},
210 {40, "pc", 24, 0x00, ASM_REG_W_PC
},
211 {41, "sr", 24, 0x39, ASM_REG_W_SR
},
212 {42, "omr",24, 0x3a, ASM_REG_W_OMR
},
213 {43, "la", 24, 0x3e, ASM_REG_W_LA
},
214 {44, "lc", 24, 0x3f, ASM_REG_W_LC
},
216 {45, "vba", 24, 0x30, ASM_REG_W_VBA
},
217 {46, "iprc",24, 0x00, ASM_REG_W_IPRC
},
218 {47, "iprp",24, 0x00, ASM_REG_W_IPRP
},
220 {48, "bcr", 24, 0x00, ASM_REG_W_BCR
},
221 {49, "dcr", 24, 0x00, ASM_REG_W_DCR
},
222 {50, "aar0",24, 0x00, ASM_REG_W_AAR0
},
223 {51, "aar1",24, 0x00, ASM_REG_W_AAR1
},
224 {52, "aar2",24, 0x00, ASM_REG_W_AAR2
},
225 {53, "aar3",24, 0x00, ASM_REG_W_AAR3
},
233 #define REG_NUM_M0 16
234 #define REG_NUM_M1 17
235 #define REG_NUM_SSH 34
236 #define REG_NUM_SSL 35
237 #define REG_NUM_SP 36
238 #define REG_NUM_EP 37
239 #define REG_NUM_SC 39
240 #define REG_NUM_PC 40
241 #define REG_NUM_SR 41
242 #define REG_NUM_IPRC 46
243 #define REG_NUM_IPRP 47
244 #define REG_NUM_BCR 48
245 #define REG_NUM_DCR 49
246 #define REG_NUM_AAR0 50
247 #define REG_NUM_AAR1 51
248 #define REG_NUM_AAR2 52
249 #define REG_NUM_AAR3 53
258 #define INSTR_JUMP 0x0AF080
259 /* Effective Addressing Mode Encoding */
261 /* instrcution encoder */
263 * s - peripheral space X/Y (X=0,Y=1)
265 * d - source/destination register
266 * p - IO short address
268 #define INSTR_MOVEP_REG_HIO(s,w,d,p) (0x084000 | ((s & 1)<<16) | ((w&1)<<15) | ((d & 0x3f)<<8) | (p & 0x3f))
270 static int dsp563xx_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
273 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
275 if (target
->state
!= TARGET_HALTED
)
277 return ERROR_TARGET_NOT_HALTED
;
280 *reg_list_size
= DSP563XX_NUMCOREREGS
;
281 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
284 return ERROR_INVALID_ARGUMENTS
;
286 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
288 (*reg_list
)[i
] = &dsp563xx
->core_cache
->reg_list
[i
];
295 static int dsp563xx_read_core_reg(struct target
*target
, int num
)
298 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
299 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
301 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
302 return ERROR_INVALID_ARGUMENTS
;
304 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
305 reg_value
= dsp563xx
->core_regs
[num
];
306 buf_set_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
307 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
308 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
313 static int dsp563xx_write_core_reg(struct target
*target
, int num
)
316 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
317 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
319 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
320 return ERROR_INVALID_ARGUMENTS
;
322 reg_value
= buf_get_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32);
323 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
324 dsp563xx
->core_regs
[num
] = reg_value
;
325 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
326 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
331 static int dsp563xx_get_core_reg(struct reg
*reg
)
333 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
334 struct target
*target
= dsp563xx_reg
->target
;
335 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
337 LOG_DEBUG("%s", __FUNCTION__
);
339 if (target
->state
!= TARGET_HALTED
)
341 return ERROR_TARGET_NOT_HALTED
;
344 return dsp563xx
->read_core_reg(target
, dsp563xx_reg
->num
);
347 static int dsp563xx_set_core_reg(struct reg
*reg
, uint8_t * buf
)
349 LOG_DEBUG("%s", __FUNCTION__
);
351 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
352 struct target
*target
= dsp563xx_reg
->target
;
353 uint32_t value
= buf_get_u32(buf
, 0, 32);
355 if (target
->state
!= TARGET_HALTED
)
357 return ERROR_TARGET_NOT_HALTED
;
360 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
367 static const struct reg_arch_type dsp563xx_reg_type
= {
368 .get
= dsp563xx_get_core_reg
,
369 .set
= dsp563xx_set_core_reg
,
372 static void dsp563xx_build_reg_cache(struct target
*target
)
374 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
376 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
377 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
378 struct reg
*reg_list
= malloc(sizeof(struct reg
) * DSP563XX_NUMCOREREGS
);
379 struct dsp563xx_core_reg
*arch_info
= malloc(sizeof(struct dsp563xx_core_reg
) * DSP563XX_NUMCOREREGS
);
382 /* Build the process context cache */
383 cache
->name
= "dsp563xx registers";
385 cache
->reg_list
= reg_list
;
386 cache
->num_regs
= DSP563XX_NUMCOREREGS
;
388 dsp563xx
->core_cache
= cache
;
390 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
392 arch_info
[i
].num
= dsp563xx_regs
[i
].id
;
393 arch_info
[i
].name
= dsp563xx_regs
[i
].name
;
394 arch_info
[i
].size
= dsp563xx_regs
[i
].bits
;
395 arch_info
[i
].eame
= dsp563xx_regs
[i
].eame
;
396 arch_info
[i
].instr_mask
= dsp563xx_regs
[i
].instr_mask
;
397 arch_info
[i
].target
= target
;
398 arch_info
[i
].dsp563xx_common
= dsp563xx
;
399 reg_list
[i
].name
= dsp563xx_regs
[i
].name
;
400 reg_list
[i
].size
= dsp563xx_regs
[i
].bits
;
401 reg_list
[i
].value
= calloc(1, 4);
402 reg_list
[i
].dirty
= 0;
403 reg_list
[i
].valid
= 0;
404 reg_list
[i
].type
= &dsp563xx_reg_type
;
405 reg_list
[i
].arch_info
= &arch_info
[i
];
409 static int dsp563xx_read_register(struct target
*target
, int num
, int force
);
410 static int dsp563xx_write_register(struct target
*target
, int num
, int force
);
412 static int dsp563xx_reg_read_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t * data
)
416 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
418 /* we use r0 to store temporary data */
419 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
420 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
422 /* move source memory to r0 */
423 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 0, EAME_R0
, instr_mask
);
424 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, instr
)) != ERROR_OK
)
426 /* move r0 to debug register */
427 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, 0xfffffc);
428 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 1, instr
)) != ERROR_OK
)
430 /* read debug register */
431 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OGDBR
, data
)) != ERROR_OK
)
433 /* r0 is no longer valid on target */
434 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
439 static int dsp563xx_reg_write_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
443 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
445 /* we use r0 to store temporary data */
446 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
447 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
449 /* move data to r0 */
450 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0, 0x60F400, data
)) != ERROR_OK
)
452 /* move r0 to destination memory */
453 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, instr_mask
);
454 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 1, instr
)) != ERROR_OK
)
457 /* r0 is no longer valid on target */
458 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
463 static int dsp563xx_reg_read(struct target
*target
, uint32_t eame
, uint32_t * data
)
468 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, eame
, 0xfffffc);
469 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, instr
)) != ERROR_OK
)
472 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 1, 0x000000)) != ERROR_OK
)
474 /* read debug register */
475 return dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OGDBR
, data
);
478 static int dsp563xx_reg_write(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
482 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0, instr_mask
, data
)) != ERROR_OK
)
485 return dsp563xx_once_execute_sw_ir(target
->tap
, 1, 0x000000);
488 static int dsp563xx_reg_pc_read(struct target
*target
)
490 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
492 /* pc was changed, nothing todo */
493 if (dsp563xx
->core_cache
->reg_list
[REG_NUM_PC
].dirty
)
496 /* conditional branch check */
497 if ( once_regs
[ONCE_REG_IDX_OPABDR
].reg
== once_regs
[ONCE_REG_IDX_OPABEX
].reg
)
499 if ( (once_regs
[ONCE_REG_IDX_OPABF11
].reg
& 1) == 0 )
501 LOG_DEBUG("%s conditional branch not supported yet", __FUNCTION__
);
503 /* TODO: use disassembly to set correct pc offset */
504 dsp563xx
->core_regs
[REG_NUM_PC
] = (once_regs
[ONCE_REG_IDX_OPABF11
].reg
>> 1) & 0x00FFFFFF;
508 if ( once_regs
[ONCE_REG_IDX_OPABEX
].reg
== once_regs
[ONCE_REG_IDX_OPABFR
].reg
)
510 dsp563xx
->core_regs
[REG_NUM_PC
] = once_regs
[ONCE_REG_IDX_OPABEX
].reg
;
514 dsp563xx
->core_regs
[REG_NUM_PC
] = once_regs
[ONCE_REG_IDX_OPABEX
].reg
- 1;
520 dsp563xx
->core_regs
[REG_NUM_PC
] = once_regs
[ONCE_REG_IDX_OPABEX
].reg
;
523 dsp563xx
->read_core_reg(target
, REG_NUM_PC
);
528 static int dsp563xx_reg_ssh_read(struct target
*target
)
532 struct dsp563xx_core_reg
*arch_info
;
533 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
535 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].arch_info
;
537 /* get a valid stack pointer */
538 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
540 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
541 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
544 /* get a valid stack count */
545 if ((err
= dsp563xx_read_register(target
, REG_NUM_SC
, 0)) != ERROR_OK
)
547 sc
= dsp563xx
->core_regs
[REG_NUM_SC
];
548 if ((err
= dsp563xx_write_register(target
, REG_NUM_SC
, 0)) != ERROR_OK
)
551 /* get a valid extended pointer */
552 if ((err
= dsp563xx_read_register(target
, REG_NUM_EP
, 0)) != ERROR_OK
)
554 ep
= dsp563xx
->core_regs
[REG_NUM_EP
];
555 if ((err
= dsp563xx_write_register(target
, REG_NUM_EP
, 0)) != ERROR_OK
)
564 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
567 if ((err
= dsp563xx_write_register(target
, REG_NUM_SC
, 1)) != ERROR_OK
)
569 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
571 if ((err
= dsp563xx_write_register(target
, REG_NUM_EP
, 1)) != ERROR_OK
)
575 dsp563xx
->core_regs
[REG_NUM_SSH
] = sp
;
576 dsp563xx
->read_core_reg(target
, REG_NUM_SSH
);
581 static int dsp563xx_reg_ssh_write(struct target
*target
)
585 struct dsp563xx_core_reg
*arch_info
;
586 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
588 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].arch_info
;
590 /* get a valid stack pointer */
591 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
593 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
598 /* write new stackpointer */
599 dsp563xx
->core_regs
[REG_NUM_SP
] = sp
;
600 if ((err
= dsp563xx
->read_core_reg(target
, REG_NUM_SP
)) != ERROR_OK
)
602 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
605 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[REG_NUM_SSH
])) != ERROR_OK
)
608 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
610 if ((err
= dsp563xx_read_register(target
, REG_NUM_SSH
, 1)) != ERROR_OK
)
617 static int dsp563xx_reg_ssl_read(struct target
*target
)
621 struct dsp563xx_core_reg
*arch_info
;
622 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
624 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSL
].arch_info
;
626 /* get a valid stack pointer */
627 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
629 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
637 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
641 dsp563xx
->core_regs
[REG_NUM_SSL
] = sp
;
642 dsp563xx
->read_core_reg(target
, REG_NUM_SSL
);
647 static int dsp563xx_read_register(struct target
*target
, int num
, int force
)
651 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
652 struct dsp563xx_core_reg
*arch_info
;
655 dsp563xx
->core_cache
->reg_list
[num
].valid
= 0;
657 if (!dsp563xx
->core_cache
->reg_list
[num
].valid
)
659 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
661 switch (arch_info
->num
)
664 err
= dsp563xx_reg_ssh_read(target
);
667 err
= dsp563xx_reg_ssl_read(target
);
670 err
= dsp563xx_reg_pc_read(target
);
680 err
= dsp563xx_reg_read_high_io(target
, arch_info
->instr_mask
, &data
);
683 dsp563xx
->core_regs
[num
] = data
;
684 dsp563xx
->read_core_reg(target
, num
);
688 err
= dsp563xx_reg_read(target
, arch_info
->eame
, &data
);
691 dsp563xx
->core_regs
[num
] = data
;
692 dsp563xx
->read_core_reg(target
, num
);
702 static int dsp563xx_write_register(struct target
*target
, int num
, int force
)
705 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
706 struct dsp563xx_core_reg
*arch_info
;
709 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 1;
711 if (dsp563xx
->core_cache
->reg_list
[num
].dirty
)
713 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
715 dsp563xx
->write_core_reg(target
, num
);
717 switch (arch_info
->num
)
720 err
= dsp563xx_reg_ssh_write(target
);
723 /* pc is updated on resume, no need to write it here */
733 err
= dsp563xx_reg_write_high_io(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
736 err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
738 if ((err
== ERROR_OK
) && (arch_info
->num
== REG_NUM_SP
))
740 dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].valid
= 0;
741 dsp563xx
->core_cache
->reg_list
[REG_NUM_SSL
].valid
= 0;
751 static int dsp563xx_save_context(struct target
*target
)
753 int i
, err
= ERROR_OK
;
755 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
757 if ((err
= dsp563xx_read_register(target
, i
, 0)) != ERROR_OK
)
764 static int dsp563xx_restore_context(struct target
*target
)
766 int i
, err
= ERROR_OK
;
768 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
770 if ((err
= dsp563xx_write_register(target
, i
, 0)) != ERROR_OK
)
777 static void dsp563xx_invalidate_x_context(struct target
*target
, uint32_t addr_start
, uint32_t addr_end
)
780 struct dsp563xx_core_reg
*arch_info
;
781 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
783 if ( addr_start
> ASM_REG_W_IPRC
)
785 if ( addr_start
< ASM_REG_W_AAR3
)
788 for (i
= REG_NUM_IPRC
; i
< DSP563XX_NUMCOREREGS
; i
++)
790 arch_info
= dsp563xx
->core_cache
->reg_list
[i
].arch_info
;
792 if ( (arch_info
->instr_mask
>= addr_start
) &&
793 (arch_info
->instr_mask
<= addr_end
))
795 dsp563xx
->core_cache
->reg_list
[i
].valid
= 0;
796 dsp563xx
->core_cache
->reg_list
[i
].dirty
= 0;
801 static int dsp563xx_target_create(struct target
*target
, Jim_Interp
* interp
)
803 struct dsp563xx_common
*dsp563xx
= calloc(1, sizeof(struct dsp563xx_common
));
806 return ERROR_INVALID_ARGUMENTS
;
808 dsp563xx
->jtag_info
.tap
= target
->tap
;
809 target
->arch_info
= dsp563xx
;
810 dsp563xx
->read_core_reg
= dsp563xx_read_core_reg
;
811 dsp563xx
->write_core_reg
= dsp563xx_write_core_reg
;
816 static int dsp563xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
818 LOG_DEBUG("%s", __FUNCTION__
);
820 dsp563xx_build_reg_cache(target
);
825 static int dsp563xx_examine(struct target
*target
)
829 if (target
->tap
->hasidcode
== false)
831 LOG_ERROR("no IDCODE present on device");
833 return ERROR_INVALID_ARGUMENTS
;
836 if (!target_was_examined(target
))
838 target_set_examined(target
);
840 /* examine core and chip derivate number */
841 chip
= (target
->tap
->idcode
>>12)&0x3ff;
842 /* core number 0 means DSP563XX */
843 if ( ((chip
>>5)&0x1f) == 0 )
846 LOG_INFO("DSP56%03d device found",chip
);
852 static int dsp563xx_arch_state(struct target
*target
)
854 LOG_DEBUG("%s", __FUNCTION__
);
858 #define DSP563XX_SR_SA (1<<17)
859 #define DSP563XX_SR_SC (1<<13)
861 static int dsp563xx_debug_once_init(struct target
*target
)
863 return dsp563xx_once_read_register(target
->tap
, 1, once_regs
, DSP563XX_NUMONCEREGS
);
866 static int dsp563xx_debug_init(struct target
*target
)
870 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
871 struct dsp563xx_core_reg
*arch_info
;
873 if ((err
= dsp563xx_debug_once_init(target
)) != ERROR_OK
)
876 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SR
].arch_info
;
878 /* check 24bit mode */
879 if ((err
= dsp563xx_read_register(target
, REG_NUM_SR
, 0)) != ERROR_OK
)
882 sr
= dsp563xx
->core_regs
[REG_NUM_SR
];
884 if (sr
& (DSP563XX_SR_SA
| DSP563XX_SR_SC
))
886 sr
&= ~(DSP563XX_SR_SA
| DSP563XX_SR_SC
);
888 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 1, arch_info
->instr_mask
, sr
)) != ERROR_OK
)
890 dsp563xx
->core_cache
->reg_list
[REG_NUM_SR
].dirty
= 1;
893 if ((err
= dsp563xx_read_register(target
, REG_NUM_N0
, 0)) != ERROR_OK
)
895 if ((err
= dsp563xx_read_register(target
, REG_NUM_N1
, 0)) != ERROR_OK
)
897 if ((err
= dsp563xx_read_register(target
, REG_NUM_M0
, 0)) != ERROR_OK
)
899 if ((err
= dsp563xx_read_register(target
, REG_NUM_M1
, 0)) != ERROR_OK
)
902 if (dsp563xx
->core_regs
[REG_NUM_N0
] != 0x000000)
904 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_N0
].arch_info
;
905 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
908 dsp563xx
->core_cache
->reg_list
[REG_NUM_N0
].dirty
= 1;
910 if (dsp563xx
->core_regs
[REG_NUM_N1
] != 0x000000)
912 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_N1
].arch_info
;
913 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
916 dsp563xx
->core_cache
->reg_list
[REG_NUM_N1
].dirty
= 1;
918 if (dsp563xx
->core_regs
[REG_NUM_M0
] != 0xffffff)
920 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_M0
].arch_info
;
921 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
924 dsp563xx
->core_cache
->reg_list
[REG_NUM_M0
].dirty
= 1;
926 if (dsp563xx
->core_regs
[REG_NUM_M1
] != 0xffffff)
928 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_M1
].arch_info
;
929 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
932 dsp563xx
->core_cache
->reg_list
[REG_NUM_M1
].dirty
= 1;
934 if ((err
= dsp563xx_save_context(target
)) != ERROR_OK
)
940 static int dsp563xx_jtag_debug_request(struct target
*target
)
942 return dsp563xx_once_request_debug(target
->tap
, target
->state
== TARGET_RESET
);
945 static int dsp563xx_poll(struct target
*target
)
948 uint32_t once_status
;
951 state
= dsp563xx_once_target_status(target
->tap
);
953 if (state
== TARGET_UNKNOWN
)
955 target
->state
= state
;
956 LOG_ERROR("jtag status contains invalid mode value - communication failure");
957 return ERROR_TARGET_FAILURE
;
960 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
963 if ((once_status
& DSP563XX_ONCE_OSCR_DEBUG_M
) == DSP563XX_ONCE_OSCR_DEBUG_M
)
965 if (target
->state
!= TARGET_HALTED
)
967 target
->state
= TARGET_HALTED
;
968 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
971 LOG_DEBUG("target->state: %s (%x)", target_state_name(target
),once_status
);
978 static int dsp563xx_halt(struct target
*target
)
982 if (target
->state
== TARGET_HALTED
)
984 LOG_DEBUG("target was already halted");
988 if (target
->state
== TARGET_UNKNOWN
)
990 LOG_WARNING("target was in unknown state when halt was requested");
993 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
996 LOG_DEBUG("%s", __FUNCTION__
);
1001 static int dsp563xx_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
1004 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1006 LOG_DEBUG("%s", __FUNCTION__
);
1008 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
1010 register_cache_invalidate(dsp563xx
->core_cache
);
1014 /* restore pipeline registers and go */
1015 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, once_regs
[ONCE_REG_IDX_OPILR
].reg
)) != ERROR_OK
)
1018 dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
1019 once_regs
[ONCE_REG_IDX_OPDBR
].reg
)) != ERROR_OK
)
1024 /* set to go register and jump */
1025 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
1027 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
1031 target
->state
= TARGET_RUNNING
;
1036 static int dsp563xx_step_ex(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int steps
)
1039 uint32_t once_status
;
1040 uint32_t dr_in
, cnt
;
1041 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1043 if (target
->state
!= TARGET_HALTED
)
1045 LOG_DEBUG("target was not halted");
1049 LOG_DEBUG("%s %08X %08X", __FUNCTION__
, current
, (unsigned) address
);
1051 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
1053 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
1056 /* reset trace mode */
1057 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
1059 /* enable trace mode */
1060 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OSCR
, DSP563XX_ONCE_OSCR_TME
)) != ERROR_OK
)
1065 /* on JUMP we need one extra cycle */
1069 /* load step counter with N-1 */
1070 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OTC
, cnt
)) != ERROR_OK
)
1075 /* restore pipeline registers and go */
1076 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, once_regs
[ONCE_REG_IDX_OPILR
].reg
)) != ERROR_OK
)
1079 dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
1080 once_regs
[ONCE_REG_IDX_OPDBR
].reg
)) != ERROR_OK
)
1085 /* set to go register and jump */
1086 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
1088 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
1094 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
1097 if (once_status
& DSP563XX_ONCE_OSCR_TO
)
1099 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OPABFR
, &dr_in
)) != ERROR_OK
)
1101 LOG_DEBUG("fetch: %08X", (unsigned) dr_in
&0x00ffffff);
1102 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OPABDR
, &dr_in
)) != ERROR_OK
)
1104 LOG_DEBUG("decode: %08X", (unsigned) dr_in
&0x00ffffff);
1105 if ((err
= dsp563xx_once_reg_read(target
->tap
, 1, DSP563XX_ONCE_OPABEX
, &dr_in
)) != ERROR_OK
)
1107 LOG_DEBUG("execute: %08X", (unsigned) dr_in
&0x00ffffff);
1109 /* reset trace mode */
1110 if ((err
= dsp563xx_once_reg_write(target
->tap
, 1, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
1113 register_cache_invalidate(dsp563xx
->core_cache
);
1114 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
1124 static int dsp563xx_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
1126 return dsp563xx_step_ex(target
, current
, address
, handle_breakpoints
, 0);
1129 static int dsp563xx_assert_reset(struct target
*target
)
1132 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1133 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1135 if (jtag_reset_config
& RESET_HAS_SRST
)
1137 /* default to asserting srst */
1138 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1140 jtag_add_reset(1, 1);
1144 jtag_add_reset(0, 1);
1148 target
->state
= TARGET_RESET
;
1149 jtag_add_sleep(5000);
1151 /* registers are now invalid */
1152 register_cache_invalidate(dsp563xx
->core_cache
);
1154 if (target
->reset_halt
)
1156 if ((retval
= target_halt(target
)) != ERROR_OK
)
1160 LOG_DEBUG("%s", __FUNCTION__
);
1164 static int dsp563xx_deassert_reset(struct target
*target
)
1168 /* deassert reset lines */
1169 jtag_add_reset(0, 0);
1171 if ((err
= dsp563xx_poll(target
)) != ERROR_OK
)
1174 if (target
->reset_halt
)
1176 if (target
->state
== TARGET_HALTED
)
1178 /* after a reset the cpu jmp to the
1179 * reset vector and need 2 cycles to fill
1180 * the cache (fetch,decode,excecute)
1182 if ((err
= dsp563xx_step_ex(target
, 1, 0, 1, 1)) != ERROR_OK
)
1187 // target->state = TARGET_RUNNING;
1189 LOG_DEBUG("%s", __FUNCTION__
);
1193 static int dsp563xx_soft_reset_halt(struct target
*target
)
1195 LOG_DEBUG("%s", __FUNCTION__
);
1199 static int dsp563xx_read_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1202 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1204 uint32_t data
, move_cmd
;
1207 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1209 if (target
->state
!= TARGET_HALTED
)
1211 LOG_WARNING("target not halted");
1212 return ERROR_TARGET_NOT_HALTED
;
1215 /* we only support 4 byte aligned data */
1216 if ( (size
!= 4) || (!count
) )
1218 return ERROR_INVALID_ARGUMENTS
;
1224 /* TODO: mark effected queued registers */
1225 move_cmd
= 0x61d800;
1228 move_cmd
= 0x69d800;
1231 move_cmd
= 0x07d891;
1234 return ERROR_INVALID_ARGUMENTS
;
1237 /* we use r0 to store temporary data */
1238 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
1239 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
1240 /* we use r1 to store temporary data */
1241 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].valid
)
1242 dsp563xx
->read_core_reg(target
, REG_NUM_R1
);
1244 /* r0 is no longer valid on target */
1245 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
1246 /* r1 is no longer valid on target */
1247 dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].dirty
= 1;
1252 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 1, 0x60F400, address
)) != ERROR_OK
)
1255 for (i
= 0; i
< x
; i
++)
1257 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, move_cmd
)) != ERROR_OK
)
1259 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, 0x08D13C)) != ERROR_OK
)
1261 if ((err
= dsp563xx_once_reg_read(target
->tap
, 0, DSP563XX_ONCE_OGDBR
, (uint32_t*)b
)) != ERROR_OK
)
1266 /* flush the jtag queue */
1267 if ((err
= jtag_execute_queue()) != ERROR_OK
)
1272 /* walk over the buffer and fix target endianness */
1275 for (i
= 0; i
< x
; i
++)
1277 data
= *((uint32_t*)b
) & 0x00FFFFFF;
1278 // LOG_DEBUG("R: %08X", *((uint32_t*)b));
1279 target_buffer_set_u32(target
, b
, data
);
1286 static int dsp563xx_read_memory_p(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1288 return dsp563xx_read_memory(target
, MEM_P
, address
, size
, count
, buffer
);
1291 static int dsp563xx_write_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1294 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1296 uint32_t data
, move_cmd
;
1299 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
1301 if (target
->state
!= TARGET_HALTED
)
1303 LOG_WARNING("target not halted");
1304 return ERROR_TARGET_NOT_HALTED
;
1307 /* we only support 4 byte aligned data */
1308 if ( (size
!= 4) || (!count
) )
1310 return ERROR_INVALID_ARGUMENTS
;
1316 /* invalidate affected x registers */
1317 dsp563xx_invalidate_x_context(target
,address
,address
+count
-1);
1318 move_cmd
= 0x615800;
1321 move_cmd
= 0x695800;
1324 move_cmd
= 0x075891;
1327 return ERROR_INVALID_ARGUMENTS
;
1330 /* we use r0 to store temporary data */
1331 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
1332 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
1333 /* we use r1 to store temporary data */
1334 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].valid
)
1335 dsp563xx
->read_core_reg(target
, REG_NUM_R1
);
1337 /* r0 is no longer valid on target */
1338 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
1339 /* r1 is no longer valid on target */
1340 dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].dirty
= 1;
1345 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 1, 0x60F400, address
)) != ERROR_OK
)
1348 for (i
= 0; i
< x
; i
++)
1350 data
= target_buffer_get_u32(target
, b
);
1352 // LOG_DEBUG("W: %08X", data);
1356 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0, 0x61F400, data
)) != ERROR_OK
)
1358 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0, move_cmd
)) != ERROR_OK
)
1363 /* flush the jtag queue */
1364 if ((err
= jtag_execute_queue()) != ERROR_OK
)
1372 static int dsp563xx_write_memory_p(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1374 return dsp563xx_write_memory(target
, MEM_P
, address
, size
, count
, buffer
);
1377 static int dsp563xx_bulk_write_memory_p(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
1379 return dsp563xx_write_memory(target
, MEM_P
, address
, 4, count
, buffer
);
1382 static void handle_md_output(struct command_context
*cmd_ctx
, struct target
*target
, uint32_t address
, unsigned size
, unsigned count
, const uint8_t * buffer
)
1384 const unsigned line_bytecnt
= 32;
1385 unsigned line_modulo
= line_bytecnt
/ size
;
1387 char output
[line_bytecnt
* 4 + 1];
1388 unsigned output_len
= 0;
1390 const char *value_fmt
;
1394 value_fmt
= "%8.8x ";
1397 value_fmt
= "%4.4x ";
1400 value_fmt
= "%2.2x ";
1403 /* "can't happen", caller checked */
1404 LOG_ERROR("invalid memory read size: %u", size
);
1408 for (unsigned i
= 0; i
< count
; i
++)
1410 if (i
% line_modulo
== 0)
1412 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, "0x%8.8x: ", (unsigned) (address
+ (i
* size
)));
1416 const uint8_t *value_ptr
= buffer
+ i
* size
;
1420 value
= target_buffer_get_u32(target
, value_ptr
);
1423 value
= target_buffer_get_u16(target
, value_ptr
);
1428 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, value_fmt
, value
);
1430 if ((i
% line_modulo
== line_modulo
- 1) || (i
== count
- 1))
1432 command_print(cmd_ctx
, "%s", output
);
1438 COMMAND_HANDLER(dsp563xx_mem_command
)
1440 struct target
*target
= get_current_target(CMD_CTX
);
1443 uint32_t address
= 0;
1444 uint32_t count
= 1, i
;
1445 uint32_t pattern
= 0;
1447 uint8_t *buffer
, *b
;
1449 switch (CMD_NAME
[1])
1458 return ERROR_COMMAND_SYNTAX_ERROR
;
1461 switch (CMD_NAME
[3])
1473 return ERROR_COMMAND_SYNTAX_ERROR
;
1478 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1485 return ERROR_COMMAND_SYNTAX_ERROR
;
1489 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], pattern
);
1493 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], count
);
1501 return ERROR_COMMAND_SYNTAX_ERROR
;
1505 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], count
);
1509 buffer
= calloc(count
, sizeof(uint32_t));
1513 if ((err
= dsp563xx_read_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
)) == ERROR_OK
)
1514 handle_md_output(CMD_CTX
, target
, address
, sizeof(uint32_t), count
, buffer
);
1520 for (i
= 0; i
< count
; i
++)
1522 target_buffer_set_u32(target
, b
, pattern
);
1526 err
= dsp563xx_write_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
);
1534 static const struct command_registration dsp563xx_command_handlers
[] = {
1537 .handler
= dsp563xx_mem_command
,
1538 .mode
= COMMAND_EXEC
,
1539 .help
= "write x memory words",
1540 .usage
= "mwwx address value [count]",
1544 .handler
= dsp563xx_mem_command
,
1545 .mode
= COMMAND_EXEC
,
1546 .help
= "write y memory words",
1547 .usage
= "mwwy address value [count]",
1551 .handler
= dsp563xx_mem_command
,
1552 .mode
= COMMAND_EXEC
,
1553 .help
= "write p memory words",
1554 .usage
= "mwwp address value [count]",
1558 .handler
= dsp563xx_mem_command
,
1559 .mode
= COMMAND_EXEC
,
1560 .help
= "display x memory words",
1561 .usage
= "mdwx address [count]",
1565 .handler
= dsp563xx_mem_command
,
1566 .mode
= COMMAND_EXEC
,
1567 .help
= "display y memory words",
1568 .usage
= "mdwy address [count]",
1572 .handler
= dsp563xx_mem_command
,
1573 .mode
= COMMAND_EXEC
,
1574 .help
= "display p memory words",
1575 .usage
= "mdwp address [count]",
1577 COMMAND_REGISTRATION_DONE
1580 /** Holds methods for DSP563XX targets. */
1581 struct target_type dsp563xx_target
= {
1584 .poll
= dsp563xx_poll
,
1585 .arch_state
= dsp563xx_arch_state
,
1587 .target_request_data
= NULL
,
1589 .get_gdb_reg_list
= dsp563xx_get_gdb_reg_list
,
1591 .halt
= dsp563xx_halt
,
1592 .resume
= dsp563xx_resume
,
1593 .step
= dsp563xx_step
,
1595 .assert_reset
= dsp563xx_assert_reset
,
1596 .deassert_reset
= dsp563xx_deassert_reset
,
1597 .soft_reset_halt
= dsp563xx_soft_reset_halt
,
1599 .read_memory
= dsp563xx_read_memory_p
,
1600 .write_memory
= dsp563xx_write_memory_p
,
1601 .bulk_write_memory
= dsp563xx_bulk_write_memory_p
,
1603 .commands
= dsp563xx_command_handlers
,
1604 .target_create
= dsp563xx_target_create
,
1605 .init_target
= dsp563xx_init_target
,
1606 .examine
= dsp563xx_examine
,