gcc/config/spu/spu.h

   1 /* Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   2
   3    This file is free software; you can redistribute it and/or modify it under
   4    the terms of the GNU General Public License as published by the Free
   5    Software Foundation; either version 3 of the License, or (at your option)
   6    any later version.
   7
   8    This file is distributed in the hope that it will be useful, but WITHOUT
   9    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  11    for more details.
  12
  13    You should have received a copy of the GNU General Public License
  14    along with GCC; see the file COPYING3.  If not see
  15    <http://www.gnu.org/licenses/>.  */
  16
  17 \f
  18 /* Run-time Target */
  19 #define TARGET_CPU_CPP_BUILTINS()       spu_cpu_cpp_builtins(pfile)
  20
  21 #define TARGET_VERSION fprintf (stderr, " (spu %s)", __DATE__);
  22
  23 #define C_COMMON_OVERRIDE_OPTIONS spu_c_common_override_options()
  24
  25 #define INIT_EXPANDERS spu_init_expanders()
  26
  27 /* Which processor to generate code or schedule for.  */
  28 enum processor_type
  29 {
  30   PROCESSOR_CELL,
  31   PROCESSOR_CELLEDP
  32 };
  33
  34 extern GTY(()) int spu_arch;
  35 extern GTY(()) int spu_tune;
  36
  37 /* Support for a compile-time default architecture and tuning.  The rules are:
  38    --with-arch is ignored if -march is specified.
  39    --with-tune is ignored if -mtune is specified.  */
  40 #define OPTION_DEFAULT_SPECS \
  41   {"arch", "%{!march=*:-march=%(VALUE)}" }, \
  42   {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }
  43
  44 /* Default target_flags if no switches specified.  */
  45 #ifndef TARGET_DEFAULT
  46 #define TARGET_DEFAULT (MASK_ERROR_RELOC | MASK_SAFE_DMA | MASK_BRANCH_HINTS \
  47                         | MASK_SAFE_HINTS | MASK_ADDRESS_SPACE_CONVERSION)
  48 #endif
  49
  50 \f
  51 /* Storage Layout */
  52
  53 #define BITS_BIG_ENDIAN 1
  54
  55 #define BYTES_BIG_ENDIAN 1
  56
  57 #define WORDS_BIG_ENDIAN 1
  58
  59 #define BITS_PER_UNIT 8
  60
  61 /* GCC uses word_mode in many places, assuming that it is the fastest
  62    integer mode.  That is not the case for SPU though.  We can't use
  63    32 here because (of some reason I can't remember.) */
  64 #define BITS_PER_WORD 128
  65
  66 #define UNITS_PER_WORD (BITS_PER_WORD/BITS_PER_UNIT)
  67
  68 /* When building libgcc, we need to assume 4 words per units even
  69    though UNITS_PER_WORD is 16, because the SPU has basically a 32-bit
  70    instruction set although register size is 128 bits.  In particular,
  71    this causes libgcc to contain __divdi3 instead of __divti3 etc.
  72    However, we allow this default to be re-defined on the command
  73    line, so that we can use the LIB2_SIDITI_CONV_FUNCS mechanism
  74    to get (in addition) TImode versions of some routines.  */
  75 #ifndef LIBGCC2_UNITS_PER_WORD
  76 #define LIBGCC2_UNITS_PER_WORD 4
  77 #endif
  78
  79 #define POINTER_SIZE 32
  80
  81 #define PARM_BOUNDARY 128
  82
  83 #define STACK_BOUNDARY 128
  84
  85 /* We want it 8-byte aligned so we can properly use dual-issue
  86    instructions, which can only happen on an 8-byte aligned address. */
  87 #define FUNCTION_BOUNDARY 64
  88
  89 /* We would like to allow a larger alignment for data objects (for DMA)
  90    but the aligned attribute is limited by BIGGEST_ALIGNMENT.  We don't
  91    define BIGGEST_ALIGNMENT as larger because it is used in other places
  92    and would end up wasting space.  (Is this still true?)  */
  93 #define BIGGEST_ALIGNMENT 128
  94
  95 #define MINIMUM_ATOMIC_ALIGNMENT 128
  96
  97 /* Make all static objects 16-byte aligned.  This allows us to assume
  98    they are also padded to 16-bytes, which means we can use a single
  99    load or store instruction to access them.  Do the same for objects
 100    on the stack.  (Except a bug (?) allows some stack objects to be
 101    unaligned.)  */
 102 #define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
 103 #define CONSTANT_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
 104 #define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
 105
 106 #define EMPTY_FIELD_BOUNDARY 32
 107
 108 #define STRICT_ALIGNMENT 1
 109
 110 /* symbol_ref's of functions are not aligned to 16 byte boundary. */
 111 #define ALIGNED_SYMBOL_REF_P(X) \
 112         (GET_CODE (X) == SYMBOL_REF \
 113           && (SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1) == 0 \
 114           && (! SYMBOL_REF_FUNCTION_P (X) \
 115               || align_functions >= 16))
 116
 117 #define PCC_BITFIELD_TYPE_MATTERS 1
 118
 119 #define MAX_FIXED_MODE_SIZE 128
 120
 121 #define STACK_SAVEAREA_MODE(save_level) \
 122   (save_level == SAVE_FUNCTION ? VOIDmode \
 123     : save_level == SAVE_NONLOCAL ? SImode \
 124       : Pmode)
 125
 126 #define STACK_SIZE_MODE SImode
 127
 128 \f
 129 /* Type Layout */
 130
 131 #define INT_TYPE_SIZE 32
 132
 133 #define LONG_TYPE_SIZE 32
 134
 135 #define LONG_LONG_TYPE_SIZE 64
 136
 137 #define FLOAT_TYPE_SIZE 32
 138
 139 #define DOUBLE_TYPE_SIZE 64
 140
 141 #define LONG_DOUBLE_TYPE_SIZE 64
 142
 143 #define DEFAULT_SIGNED_CHAR 0
 144
 145 #define STDINT_LONG32 0
 146
 147 \f
 148 /* Register Basics */
 149
 150 /* 128-130 are special registers that never appear in assembly code. */
 151 #define FIRST_PSEUDO_REGISTER 131
 152
 153 #define FIXED_REGISTERS {                           \
 154     1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 155     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 156     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 157     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 158     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 159     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 160     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 161     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 162     1, 1, 1 \
 163 }
 164
 165 #define CALL_USED_REGISTERS {                       \
 166     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
 167     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
 168     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
 169     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
 170     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
 171     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 172     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 173     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 174     1, 1, 1 \
 175 }
 176
 177 \f
 178 /* Values in Registers */
 179
 180 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 181     ((GET_MODE_BITSIZE(MODE)+MAX_FIXED_MODE_SIZE-1)/MAX_FIXED_MODE_SIZE)
 182
 183 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
 184
 185 #define MODES_TIEABLE_P(MODE1, MODE2) \
 186   (GET_MODE_BITSIZE (MODE1) <= MAX_FIXED_MODE_SIZE \
 187    && GET_MODE_BITSIZE (MODE2) <= MAX_FIXED_MODE_SIZE)
 188
 189 \f
 190 /* Register Classes */
 191
 192 enum reg_class {
 193    NO_REGS,
 194    GENERAL_REGS,
 195    ALL_REGS,
 196    LIM_REG_CLASSES
 197 };
 198
 199 /* SPU is simple, it really only has one class of registers.  */
 200 #define IRA_COVER_CLASSES { GENERAL_REGS, LIM_REG_CLASSES }
 201
 202 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 203
 204 #define REG_CLASS_NAMES \
 205 {  "NO_REGS", \
 206    "GENERAL_REGS", \
 207    "ALL_REGS" \
 208 }
 209
 210 #define REG_CLASS_CONTENTS { \
 211     {0, 0, 0, 0, 0}, /* no regs */ \
 212     {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}, /* general regs */ \
 213     {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}} /* all regs */
 214
 215 #define REGNO_REG_CLASS(REGNO) (GENERAL_REGS)
 216
 217 #define BASE_REG_CLASS GENERAL_REGS
 218
 219 #define INDEX_REG_CLASS GENERAL_REGS
 220
 221 #define REGNO_OK_FOR_BASE_P(regno) \
 222    ((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0))
 223
 224 #define REGNO_OK_FOR_INDEX_P(regno)  \
 225    ((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0))
 226
 227 #define INT_REG_OK_FOR_INDEX_P(X,STRICT) \
 228         ((!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
 229 #define INT_REG_OK_FOR_BASE_P(X,STRICT) \
 230         ((!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
 231
 232 #define CLASS_MAX_NREGS(CLASS, MODE)    \
 233         ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 234
 235 /* GCC assumes that modes are in the lowpart of a register, which is
 236    only true for SPU. */
 237 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
 238         ((GET_MODE_SIZE (FROM) > 4 || GET_MODE_SIZE (TO) > 4) \
 239          && (GET_MODE_SIZE (FROM) < 16 || GET_MODE_SIZE (TO) < 16) \
 240          && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
 241
 242 #define REGISTER_TARGET_PRAGMAS() do {                                  \
 243 c_register_addr_space ("__ea", ADDR_SPACE_EA);                          \
 244 targetm.resolve_overloaded_builtin = spu_resolve_overloaded_builtin;    \
 245 }while (0);
 246
 247 \f
 248 /* Frame Layout */
 249
 250 #define STACK_GROWS_DOWNWARD
 251
 252 #define FRAME_GROWS_DOWNWARD 1
 253
 254 #define STARTING_FRAME_OFFSET (0)
 255
 256 #define STACK_POINTER_OFFSET 32
 257
 258 #define FIRST_PARM_OFFSET(FNDECL) (0)
 259
 260 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant ((FP), -16)
 261
 262 #define RETURN_ADDR_RTX(COUNT,FP) (spu_return_addr (COUNT, FP))
 263
 264 /* Should this be defined?  Would it simplify our implementation. */
 265 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
 266
 267 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG(Pmode, LINK_REGISTER_REGNUM)
 268
 269 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
 270
 271 #define ARG_POINTER_CFA_OFFSET(FNDECL) \
 272   (crtl->args.pretend_args_size - STACK_POINTER_OFFSET)
 273
 274 \f
 275 /* Stack Checking */
 276
 277 /* We store the Available Stack Size in the second slot of the stack
 278    register.   We emit stack checking code during the prologue.  */
 279 #define STACK_CHECK_BUILTIN 1
 280
 281 \f
 282 /* Frame Registers, and other registers */
 283
 284 #define STACK_POINTER_REGNUM 1
 285
 286 /* Will be eliminated. */
 287 #define FRAME_POINTER_REGNUM 128
 288
 289 /* This is not specified in any ABI, so could be set to anything. */
 290 #define HARD_FRAME_POINTER_REGNUM 127
 291
 292 /* Will be eliminated. */
 293 #define ARG_POINTER_REGNUM 129
 294
 295 #define STATIC_CHAIN_REGNUM 2
 296
 297 #define LINK_REGISTER_REGNUM 0
 298
 299 /* Used to keep track of instructions that have clobbered the hint
 300  * buffer.  Users can also specify it in inline asm. */
 301 #define HBR_REGNUM 130
 302
 303 #define MAX_REGISTER_ARGS    72
 304 #define FIRST_ARG_REGNUM     3
 305 #define LAST_ARG_REGNUM      (FIRST_ARG_REGNUM + MAX_REGISTER_ARGS - 1)
 306
 307 #define MAX_REGISTER_RETURN  72
 308 #define FIRST_RETURN_REGNUM  3
 309 #define LAST_RETURN_REGNUM   (FIRST_RETURN_REGNUM + MAX_REGISTER_RETURN - 1)
 310
 311 \f
 312 /* Elimination */
 313
 314 #define ELIMINABLE_REGS  \
 315   {{ARG_POINTER_REGNUM,  STACK_POINTER_REGNUM},                         \
 316   {ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 317   {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 318   {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 319
 320 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 321   ((OFFSET) = spu_initial_elimination_offset((FROM),(TO)))
 322
 323 \f
 324 /* Stack Arguments */
 325
 326 #define ACCUMULATE_OUTGOING_ARGS 1
 327
 328 #define REG_PARM_STACK_SPACE(FNDECL) 0
 329
 330 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 331
 332 \f
 333 /* Register Arguments */
 334
 335 #define CUMULATIVE_ARGS int
 336
 337 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 338                 ((CUM) = 0)
 339
 340 /* The SPU ABI wants 32/64-bit types at offset 0 in the quad-word on the
 341    stack.  8/16-bit types should be at offsets 3/2 respectively.  */
 342 #define FUNCTION_ARG_OFFSET(MODE, TYPE)                                 \
 343 (((TYPE) && INTEGRAL_TYPE_P (TYPE) && GET_MODE_SIZE (MODE) < 4)         \
 344  ? (4 - GET_MODE_SIZE (MODE))                                           \
 345  : 0)
 346
 347 #define FUNCTION_ARG_PADDING(MODE,TYPE) upward
 348
 349 #define PAD_VARARGS_DOWN 0
 350
 351 #define FUNCTION_ARG_REGNO_P(N) ((N) >= (FIRST_ARG_REGNUM) && (N) <= (LAST_ARG_REGNUM))
 352 \f
 353 /* Scalar Return */
 354
 355 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 356         (spu_function_value((VALTYPE),(FUNC)))
 357
 358 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RETURN_REGNUM)
 359
 360 #define FUNCTION_VALUE_REGNO_P(N) ((N) >= (FIRST_RETURN_REGNUM) && (N) <= (LAST_RETURN_REGNUM))
 361
 362 \f
 363 /* Machine-specific symbol_ref flags.  */
 364 #define SYMBOL_FLAG_ALIGN1      (SYMBOL_FLAG_MACH_DEP << 0)
 365 \f
 366 /* Aggregate Return */
 367
 368 #define DEFAULT_PCC_STRUCT_RETURN 0
 369
 370 \f
 371 /* Function Entry */
 372
 373 #define EXIT_IGNORE_STACK 0
 374
 375 #define EPILOGUE_USES(REGNO) ((REGNO)==1 ? 1 : 0)
 376
 377 \f
 378 /* Profiling */
 379
 380 #define FUNCTION_PROFILER(FILE, LABELNO)  \
 381   spu_function_profiler ((FILE), (LABELNO));
 382
 383 #define NO_PROFILE_COUNTERS 1
 384
 385 #define PROFILE_BEFORE_PROLOGUE 1
 386
 387 \f
 388 /* Trampolines */
 389
 390 #define TRAMPOLINE_SIZE (TARGET_LARGE_MEM ? 20 : 16)
 391
 392 #define TRAMPOLINE_ALIGNMENT 128
 393 \f
 394 /* Addressing Modes */
 395
 396 #define CONSTANT_ADDRESS_P(X)   spu_constant_address_p(X)
 397
 398 #define MAX_REGS_PER_ADDRESS 2
 399
 400 #define LEGITIMATE_CONSTANT_P(X) spu_legitimate_constant_p(X)
 401
 402 \f
 403 /* Costs */
 404
 405 #define BRANCH_COST(speed_p, predictable_p) spu_branch_cost
 406
 407 #define SLOW_BYTE_ACCESS 0
 408
 409 #define MOVE_RATIO(speed) 32
 410
 411 #define NO_FUNCTION_CSE
 412
 413 \f
 414 /* Sections */
 415
 416 #define TEXT_SECTION_ASM_OP ".text"
 417
 418 #define DATA_SECTION_ASM_OP ".data"
 419
 420 #define JUMP_TABLES_IN_TEXT_SECTION 1
 421
 422 \f
 423 /* PIC */
 424 #define PIC_OFFSET_TABLE_REGNUM 126
 425
 426 \f
 427 /* File Framework */
 428
 429 #define ASM_APP_ON ""
 430
 431 #define ASM_APP_OFF ""
 432
 433 \f
 434 /* Uninitialized Data */
 435 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
 436 ( fputs (".comm ", (FILE)),                     \
 437   assemble_name ((FILE), (NAME)),               \
 438   fprintf ((FILE), ",%d\n", (ROUNDED)))
 439
 440 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
 441 ( fputs (".lcomm ", (FILE)),                    \
 442   assemble_name ((FILE), (NAME)),               \
 443   fprintf ((FILE), ",%d\n", (ROUNDED)))
 444
 445 \f
 446 /* Label Output */
 447 #define ASM_OUTPUT_LABEL(FILE,NAME)     \
 448   do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
 449
 450 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
 451   asm_fprintf (FILE, "%U%s", default_strip_name_encoding (NAME))
 452
 453 #define ASM_OUTPUT_SYMBOL_REF(FILE, X) \
 454   do                                                    \
 455     {                                                   \
 456       tree decl;                                        \
 457       assemble_name (FILE, XSTR ((X), 0));              \
 458       if ((decl = SYMBOL_REF_DECL ((X))) != 0           \
 459           && TREE_CODE (decl) == VAR_DECL               \
 460           && TYPE_ADDR_SPACE (TREE_TYPE (decl)))        \
 461         fputs ("@ppu", FILE);                           \
 462     } while (0)
 463
 464 \f
 465 /* Instruction Output */
 466 #define REGISTER_NAMES \
 467 {"$lr", "$sp", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
 468  "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", \
 469  "$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39", "$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47", \
 470  "$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55", "$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63", \
 471  "$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71", "$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79", \
 472  "$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87", "$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95", \
 473  "$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103", "$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111", \
 474  "$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119", "$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127", \
 475  "$vfp", "$vap", "hbr" \
 476 }
 477
 478 #define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE, X, CODE)
 479
 480 #define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
 481  print_operand_address (FILE, ADDR)
 482
 483 #define LOCAL_LABEL_PREFIX "."
 484
 485 #define USER_LABEL_PREFIX ""
 486
 487 \f
 488 /* Dispatch Tables */
 489
 490 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
 491   fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
 492
 493 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
 494   fprintf (FILE, "\t.word .L%d\n", VALUE)
 495
 496 \f
 497 /* Alignment Output */
 498
 499 #define ASM_OUTPUT_ALIGN(FILE,LOG)  \
 500   do { if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); } while (0)
 501
 502 \f
 503 /* Misc */
 504
 505 #define CASE_VECTOR_MODE SImode
 506
 507 #define MOVE_MAX 16
 508
 509 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) ((INPREC) <= 32 && (OUTPREC) <= (INPREC))
 510
 511 #define STORE_FLAG_VALUE -1
 512
 513 #define Pmode SImode
 514
 515 #define FUNCTION_MODE QImode
 516
 517 #define NO_IMPLICIT_EXTERN_C 1
 518
 519 /* Canonicalize a comparison from one we don't have to one we do have.  */
 520 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
 521   do {                                                                    \
 522     if (((CODE) == LE || (CODE) == LT || (CODE) == LEU || (CODE) == LTU)) \
 523       {                                                                   \
 524         rtx tem = (OP0);                                                  \
 525         (OP0) = (OP1);                                                    \
 526         (OP1) = tem;                                                      \
 527         (CODE) = swap_condition (CODE);                                   \
 528       }                                                                   \
 529   } while (0)
 530
 531
 532 /* Address spaces.  */
 533 #define ADDR_SPACE_EA   1
 534
 535
 536 /* Builtins.  */
 537
 538 enum spu_builtin_type
 539 {
 540   B_INSN,
 541   B_JUMP,
 542   B_BISLED,
 543   B_CALL,
 544   B_HINT,
 545   B_OVERLOAD,
 546   B_INTERNAL
 547 };
 548
 549 struct spu_builtin_description
 550 {
 551   int fcode;
 552   int icode;
 553   const char *name;
 554   enum spu_builtin_type type;
 555
 556   /* The first element of parm is always the return type.  The rest
 557      are a zero terminated list of parameters.  */
 558   int parm[5];
 559 };
 560
 561 extern struct spu_builtin_description spu_builtins[];
 562