gcc/config/m32c/m32c.h

   1 /* Target Definitions for R8C/M16C/M32C
   2    Copyright (C) 2005, 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_M32C_H
  23 #define GCC_M32C_H
  24
  25 /* Controlling the Compilation Driver, `gcc'.  */
  26
  27 #undef  STARTFILE_SPEC
  28 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
  29
  30 #undef  ENDFILE_SPEC
  31 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  32
  33 #undef  LINK_SPEC
  34 #define LINK_SPEC "%{h*} %{v:-V} \
  35                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  36
  37 /* There are four CPU series we support, but they basically break down
  38    into two families - the R8C/M16C families, with 16-bit address
  39    registers and one set of opcodes, and the M32CM/M32C group, with
  40    24-bit address registers and a different set of opcodes.  The
  41    assembler doesn't care except for which opcode set is needed; the
  42    big difference is in the memory maps, which we cover in
  43    LIB_SPEC.  */
  44
  45 #undef  ASM_SPEC
  46 #define ASM_SPEC "\
  47 %{mcpu=r8c:--m16c} \
  48 %{mcpu=m16c:--m16c} \
  49 %{mcpu=m32cm:--m32c} \
  50 %{mcpu=m32c:--m32c} "
  51
  52 /* The default is R8C hardware.  We support a simulator, which has its
  53    own libgloss and link map, plus one default link map for each chip
  54    family.  Most of the logic here is making sure we do the right
  55    thing when no CPU is specified, which defaults to R8C.  */
  56 #undef  LIB_SPEC
  57 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
  58 %{msim*:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
  59         %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
  60 %{!T*:%{!msim*: %{mcpu=m16c:%Tm16c.ld} \
  61                 %{mcpu=m32cm:%Tm32cm.ld} \
  62                 %{mcpu=m32c:%Tm32c.ld} \
  63                 %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
  64 "
  65
  66 /* Run-time Target Specification */
  67
  68 /* Nothing unusual here.  */
  69 #define TARGET_CPU_CPP_BUILTINS() \
  70   { \
  71     builtin_assert ("cpu=m32c"); \
  72     builtin_assert ("machine=m32c"); \
  73     builtin_define ("__m32c__=1"); \
  74     if (TARGET_R8C) \
  75       builtin_define ("__r8c_cpu__=1"); \
  76     if (TARGET_M16C) \
  77       builtin_define ("__m16c_cpu__=1"); \
  78     if (TARGET_M32CM) \
  79       builtin_define ("__m32cm_cpu__=1"); \
  80     if (TARGET_M32C) \
  81       builtin_define ("__m32c_cpu__=1"); \
  82   }
  83
  84 /* The pragma handlers need to know if we've started processing
  85    functions yet, as the memregs pragma should only be given at the
  86    beginning of the file.  This variable starts off TRUE and later
  87    becomes FALSE.  */
  88 extern int ok_to_change_target_memregs;
  89 extern int target_memregs;
  90
  91 /* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
  92    use enums or defines for this, this and m32c.opt are the only
  93    places that know (or care) what values are being used.  */
  94 #define TARGET_R8C      (target_cpu == 'r')
  95 #define TARGET_M16C     (target_cpu == '6')
  96 #define TARGET_M32CM    (target_cpu == 'm')
  97 #define TARGET_M32C     (target_cpu == '3')
  98
  99 /* Address register sizes.  Warning: these are used all over the place
 100    to select between the two CPU families in general.  */
 101 #define TARGET_A16      (TARGET_R8C || TARGET_M16C)
 102 #define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
 103
 104 #define TARGET_VERSION fprintf (stderr, " (m32c)");
 105
 106 /* Defining data structures for per-function information */
 107
 108 typedef struct GTY (()) machine_function
 109 {
 110   /* How much we adjust the stack when returning from an exception
 111      handler.  */
 112   rtx eh_stack_adjust;
 113
 114   /* TRUE if the current function is an interrupt handler.  */
 115   int is_interrupt;
 116
 117   /* TRUE if the current function is a leaf function.  Currently, this
 118      only affects saving $a0 in interrupt functions.  */
 119   int is_leaf;
 120
 121   /* Bitmask that keeps track of which registers are used in an
 122      interrupt function, so we know which ones need to be saved and
 123      restored.  */
 124   int intr_pushm;
 125   /* Likewise, one element for each memreg that needs to be saved.  */
 126   char intr_pushmem[16];
 127
 128   /* TRUE if the current function can use a simple RTS to return, instead
 129      of the longer ENTER/EXIT pair.  */
 130   int use_rts;
 131 }
 132 machine_function;
 133
 134 #define INIT_EXPANDERS m32c_init_expanders ()
 135
 136 /* Storage Layout */
 137
 138 #define BITS_BIG_ENDIAN 0
 139 #define BYTES_BIG_ENDIAN 0
 140 #define WORDS_BIG_ENDIAN 0
 141
 142 /* We can do QI, HI, and SI operations pretty much equally well, but
 143    GCC expects us to have a "native" format, so we pick the one that
 144    matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
 145    is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
 146    24-bit pointers are stored in 32-bit words.  */
 147 #define BITS_PER_UNIT 8
 148 #define UNITS_PER_WORD 2
 149 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
 150 #define POINTERS_EXTEND_UNSIGNED 1
 151 /* We have a problem with libgcc2.  It only defines two versions of
 152    each function, one for "int" and one for "long long".  Ie it assumes
 153    that "sizeof (int) == sizeof (long)".  For the M32C this is not true
 154    and we need a third set of functions.  We explicitly define
 155    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
 156    to get the SI and DI versions from the libgcc2.c sources, and we
 157    provide our own set of HI functions in m32c-lib2.c, which is why this
 158    definition is surrounded by #ifndef..#endif.  */
 159 #ifndef LIBGCC2_UNITS_PER_WORD
 160 #define LIBGCC2_UNITS_PER_WORD 4
 161 #endif
 162
 163 /* These match the alignment enforced by the two types of stack operations.  */
 164 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
 165 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
 166
 167 /* We do this because we care more about space than about speed.  For
 168    the chips with 16-bit busses, we could set these to 16 if
 169    desired.  */
 170 #define FUNCTION_BOUNDARY 8
 171 #define BIGGEST_ALIGNMENT 8
 172
 173 /* Since we have a maximum structure alignment of 8 there
 174    is no need to enforce any alignment of bitfield types.  */
 175 #undef  PCC_BITFIELD_TYPE_MATTERS
 176 #define PCC_BITFIELD_TYPE_MATTERS 0
 177
 178 #define STRICT_ALIGNMENT 0
 179 #define SLOW_BYTE_ACCESS 1
 180
 181 /* Layout of Source Language Data Types */
 182
 183 #define INT_TYPE_SIZE 16
 184 #define SHORT_TYPE_SIZE 16
 185 #define LONG_TYPE_SIZE 32
 186 #define LONG_LONG_TYPE_SIZE 64
 187
 188 #define FLOAT_TYPE_SIZE 32
 189 #define DOUBLE_TYPE_SIZE 64
 190 #define LONG_DOUBLE_TYPE_SIZE 64
 191
 192 #define DEFAULT_SIGNED_CHAR 1
 193
 194 #undef PTRDIFF_TYPE
 195 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
 196
 197 #undef UINTPTR_TYPE
 198 #define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
 199
 200 #undef  SIZE_TYPE
 201 #define SIZE_TYPE "unsigned int"
 202
 203 #undef  PTRDIFF_TYPE
 204 #define PTRDIFF_TYPE "int"
 205
 206 #undef  WCHAR_TYPE
 207 #define WCHAR_TYPE "long int"
 208
 209 #undef  WCHAR_TYPE_SIZE
 210 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 211
 212 /* REGISTER USAGE */
 213
 214 /* Register Basics */
 215
 216 /* Register layout:
 217
 218         [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
 219         [--------]  $r2  (16 bits)
 220         [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
 221         [--------]  $r3  (16 bits)
 222    [---][--------]  $a0  (might be 24 bits)
 223    [---][--------]  $a1  (might be 24 bits)
 224    [---][--------]  $sb  (might be 24 bits)
 225    [---][--------]  $fb  (might be 24 bits)
 226    [---][--------]  $sp  (might be 24 bits)
 227    [-------------]  $pc  (20 or 24 bits)
 228              [---]  $flg (CPU flags)
 229    [---][--------]  $argp (virtual)
 230         [--------]  $mem0 (all 16 bits)
 231           . . .
 232         [--------]  $mem14
 233 */
 234
 235 #define FIRST_PSEUDO_REGISTER   20
 236
 237 /* Note that these two tables are modified based on which CPU family
 238    you select; see m32c_conditional_register_usage for details.  */
 239
 240 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
 241 #define FIXED_REGISTERS     { 0, 0, 0, 0, \
 242                               0, 0, 1, 0, \
 243                               1, 1, 0, 1, \
 244                               0, 0, 0, 0, 0, 0, 0, 0 }
 245 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
 246                               1, 1, 1, 0, \
 247                               1, 1, 1, 1, \
 248                               1, 1, 1, 1, 1, 1, 1, 1 }
 249
 250 /* The *_REGNO theme matches m32c.md and most register number
 251    arguments; the PC_REGNUM is the odd one out.  */
 252 #ifndef PC_REGNO
 253 #define PC_REGNO 9
 254 #endif
 255 #define PC_REGNUM PC_REGNO
 256
 257 /* Order of Allocation of Registers */
 258
 259 #define REG_ALLOC_ORDER { \
 260         0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
 261         12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */        \
 262         6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
 263
 264 /* How Values Fit in Registers */
 265
 266 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
 267 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
 268 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
 269 #define AVOID_CCMODE_COPIES
 270
 271 /* Register Classes */
 272
 273 /* Most registers are special purpose in some form or another, so this
 274    table is pretty big.  Class names are used for constraints also;
 275    for example the HL_REGS class (HL below) is "Rhl" in the md files.
 276    See m32c_reg_class_from_constraint for the mapping.  There's some
 277    duplication so that we can better isolate the reason for using
 278    constraints in the md files from the actual registers used; for
 279    example we may want to exclude a1a0 from SI_REGS in the future,
 280    without precluding their use as HImode registers.  */
 281
 282 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
 283 /*       mmPAR */
 284 #define REG_CLASS_CONTENTS \
 285 { { 0x00000000 }, /* NO */\
 286   { 0x00000100 }, /* SP  - sp */\
 287   { 0x00000080 }, /* FB  - fb */\
 288   { 0x00000040 }, /* SB  - sb */\
 289   { 0x000001c0 }, /* CR  - sb fb sp */\
 290   { 0x00000001 }, /* R0  - r0 */\
 291   { 0x00000004 }, /* R1  - r1 */\
 292   { 0x00000002 }, /* R2  - r2 */\
 293   { 0x00000008 }, /* R3  - r3 */\
 294   { 0x00000003 }, /* R02 - r0r2 */\
 295   { 0x0000000c }, /* R13 - r1r3 */\
 296   { 0x00000005 }, /* HL  - r0 r1 */\
 297   { 0x00000005 }, /* QI  - r0 r1 */\
 298   { 0x0000000a }, /* R23 - r2 r3 */\
 299   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
 300   { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
 301   { 0x00000010 }, /* A0  - a0 */\
 302   { 0x00000020 }, /* A1  - a1 */\
 303   { 0x00000030 }, /* A   - a0 a1 */\
 304   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
 305   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
 306   { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
 307   { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
 308   { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
 309   { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
 310   { 0x0000007f }, /* GENERAL */\
 311   { 0x00000400 }, /* FLG */\
 312   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
 313   { 0x000ff000 }, /* MEM */\
 314   { 0x000ff003 }, /* R02_A_MEM */\
 315   { 0x000ff005 }, /* A_HL_MEM */\
 316   { 0x000ff00c }, /* R1_R3_A_MEM */\
 317   { 0x000ff00f }, /* R03_MEM */\
 318   { 0x000ff03f }, /* A_HI_MEM */\
 319   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
 320   { 0x000ff1ff }, /* ALL */\
 321 }
 322
 323 enum reg_class
 324 {
 325   NO_REGS,
 326   SP_REGS,
 327   FB_REGS,
 328   SB_REGS,
 329   CR_REGS,
 330   R0_REGS,
 331   R1_REGS,
 332   R2_REGS,
 333   R3_REGS,
 334   R02_REGS,
 335   R13_REGS,
 336   HL_REGS,
 337   QI_REGS,
 338   R23_REGS,
 339   R03_REGS,
 340   DI_REGS,
 341   A0_REGS,
 342   A1_REGS,
 343   A_REGS,
 344   AD_REGS,
 345   PS_REGS,
 346   SI_REGS,
 347   HI_REGS,
 348   R02A_REGS,
 349   RA_REGS,
 350   GENERAL_REGS,
 351   FLG_REGS,
 352   HC_REGS,
 353   MEM_REGS,
 354   R02_A_MEM_REGS,
 355   A_HL_MEM_REGS,
 356   R1_R3_A_MEM_REGS,
 357   R03_MEM_REGS,
 358   A_HI_MEM_REGS,
 359   A_AD_CR_MEM_SI_REGS,
 360   ALL_REGS,
 361   LIM_REG_CLASSES
 362 };
 363
 364 #define N_REG_CLASSES LIM_REG_CLASSES
 365
 366 #define REG_CLASS_NAMES {\
 367 "NO_REGS", \
 368 "SP_REGS", \
 369 "FB_REGS", \
 370 "SB_REGS", \
 371 "CR_REGS", \
 372 "R0_REGS", \
 373 "R1_REGS", \
 374 "R2_REGS", \
 375 "R3_REGS", \
 376 "R02_REGS", \
 377 "R13_REGS", \
 378 "HL_REGS", \
 379 "QI_REGS", \
 380 "R23_REGS", \
 381 "R03_REGS", \
 382 "DI_REGS", \
 383 "A0_REGS", \
 384 "A1_REGS", \
 385 "A_REGS", \
 386 "AD_REGS", \
 387 "PS_REGS", \
 388 "SI_REGS", \
 389 "HI_REGS", \
 390 "R02A_REGS", \
 391 "RA_REGS", \
 392 "GENERAL_REGS", \
 393 "FLG_REGS", \
 394 "HC_REGS", \
 395 "MEM_REGS", \
 396 "R02_A_MEM_REGS", \
 397 "A_HL_MEM_REGS", \
 398 "R1_R3_A_MEM_REGS", \
 399 "R03_MEM_REGS", \
 400 "A_HI_MEM_REGS", \
 401 "A_AD_CR_MEM_SI_REGS", \
 402 "ALL_REGS", \
 403 }
 404
 405 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
 406
 407 /* We support simple displacements off address registers, nothing else.  */
 408 #define BASE_REG_CLASS A_REGS
 409 #define INDEX_REG_CLASS NO_REGS
 410
 411 /* We primarily use the new "long" constraint names, with the initial
 412    letter classifying the constraint type and following letters
 413    specifying which.  The types are:
 414
 415    I - integer values
 416    R - register classes
 417    S - memory references (M was used)
 418    A - addresses (currently unused)
 419 */
 420
 421 #define CONSTRAINT_LEN(CHAR,STR) \
 422         ((CHAR) == 'I' ? 3 \
 423          : (CHAR) == 'R' ? 3 \
 424          : (CHAR) == 'S' ? 2 \
 425          : (CHAR) == 'A' ? 2 \
 426          : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
 427 #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
 428         (enum reg_class) m32c_reg_class_from_constraint (CHAR, STR)
 429
 430 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
 431 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 432
 433 #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
 434 #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
 435 #define LIMIT_RELOAD_CLASS(MODE,CLASS) \
 436   (enum reg_class) m32c_limit_reload_class (MODE, CLASS)
 437
 438 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
 439   (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)
 440
 441 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 442
 443 #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
 444
 445 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
 446
 447 #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
 448         m32c_const_ok_for_constraint_p (VALUE, C, STR)
 449 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
 450 #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
 451         m32c_extra_constraint_p (VALUE, C, STR)
 452 #define EXTRA_MEMORY_CONSTRAINT(C,STR) \
 453         m32c_extra_memory_constraint (C, STR)
 454 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
 455         m32c_extra_address_constraint (C, STR)
 456
 457 /* STACK AND CALLING */
 458
 459 /* Frame Layout */
 460
 461 /* Standard push/pop stack, no surprises here.  */
 462
 463 #define STACK_GROWS_DOWNWARD 1
 464 #define STACK_PUSH_CODE PRE_DEC
 465 #define FRAME_GROWS_DOWNWARD 1
 466
 467 #define STARTING_FRAME_OFFSET 0
 468 #define FIRST_PARM_OFFSET(F) 0
 469
 470 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
 471
 472 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
 473 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
 474
 475 /* Exception Handling Support */
 476
 477 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
 478 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
 479
 480 /* Registers That Address the Stack Frame */
 481
 482 #ifndef FP_REGNO
 483 #define FP_REGNO 7
 484 #endif
 485 #ifndef SP_REGNO
 486 #define SP_REGNO 8
 487 #endif
 488 #define AP_REGNO 11
 489
 490 #define STACK_POINTER_REGNUM    SP_REGNO
 491 #define FRAME_POINTER_REGNUM    FP_REGNO
 492 #define ARG_POINTER_REGNUM      AP_REGNO
 493
 494 /* The static chain must be pointer-capable.  */
 495 #define STATIC_CHAIN_REGNUM A0_REGNO
 496
 497 #define DWARF_FRAME_REGISTERS 20
 498 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
 499 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
 500
 501 #undef ASM_PREFERRED_EH_DATA_FORMAT
 502 /* This is the same as the default in practice, except that by making
 503    it explicit we tell binutils what size pointers to use.  */
 504 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 505   (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
 506
 507 /* Eliminating Frame Pointer and Arg Pointer */
 508
 509 #define ELIMINABLE_REGS \
 510   {{AP_REGNO, SP_REGNO}, \
 511    {AP_REGNO, FB_REGNO}, \
 512    {FB_REGNO, SP_REGNO}}
 513
 514 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
 515         (VAR) = m32c_initial_elimination_offset(FROM,TO)
 516
 517 /* Passing Function Arguments on the Stack */
 518
 519 #define PUSH_ARGS 1
 520 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
 521 #define CALL_POPS_ARGS(C) 0
 522
 523 /* Passing Arguments in Registers */
 524
 525 typedef struct m32c_cumulative_args
 526 {
 527   /* For address of return value buffer (structures are returned by
 528      passing the address of a buffer as an invisible first argument.
 529      This identifies it).  If set, the current parameter will be put
 530      on the stack, regardless of type.  */
 531   int force_mem;
 532   /* First parm is 1, parm 0 is hidden pointer for returning
 533      aggregates.  */
 534   int parm_num;
 535 } m32c_cumulative_args;
 536
 537 #define CUMULATIVE_ARGS m32c_cumulative_args
 538 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 539         m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
 540 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
 541
 542 /* How Large Values Are Returned */
 543
 544 #define DEFAULT_PCC_STRUCT_RETURN 1
 545
 546 /* Function Entry and Exit */
 547
 548 #define EXIT_IGNORE_STACK 0
 549 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
 550 #define EH_USES(REGNO) 0        /* FIXME */
 551
 552 /* Generating Code for Profiling */
 553
 554 #define FUNCTION_PROFILER(FILE,LABELNO)
 555
 556 /* Implementing the Varargs Macros */
 557
 558 /* Trampolines for Nested Functions */
 559
 560 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
 561 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
 562
 563 /* Addressing Modes */
 564
 565 #define HAVE_PRE_DECREMENT 1
 566 #define HAVE_POST_INCREMENT 1
 567 #define MAX_REGS_PER_ADDRESS 1
 568
 569 /* This is passed to the macros below, so that they can be implemented
 570    in m32c.c.  */
 571 #ifdef REG_OK_STRICT
 572 #define REG_OK_STRICT_V 1
 573 #else
 574 #define REG_OK_STRICT_V 0
 575 #endif
 576
 577 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
 578 #define REG_OK_FOR_INDEX_P(X) 0
 579
 580 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
 581
 582 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
 583         if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
 584           goto WIN;
 585
 586 #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
 587
 588 /* Address spaces.  */
 589 #define ADDR_SPACE_FAR  1
 590
 591
 592 /* Condition Code Status */
 593
 594 #define REVERSIBLE_CC_MODE(MODE) 1
 595
 596 /* Dividing the Output into Sections (Texts, Data, ...) */
 597
 598 #define TEXT_SECTION_ASM_OP ".text"
 599 #define DATA_SECTION_ASM_OP ".data"
 600 #define BSS_SECTION_ASM_OP ".bss"
 601
 602 #define CTOR_LIST_BEGIN
 603 #define CTOR_LIST_END
 604 #define DTOR_LIST_BEGIN
 605 #define DTOR_LIST_END
 606 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 607 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 608 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 609 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 610
 611 /* The Overall Framework of an Assembler File */
 612
 613 #define ASM_COMMENT_START ";"
 614 #define ASM_APP_ON ""
 615 #define ASM_APP_OFF ""
 616
 617 /* Output and Generation of Labels */
 618
 619 #define GLOBAL_ASM_OP "\t.global\t"
 620
 621 /* Output of Assembler Instructions */
 622
 623 #define REGISTER_NAMES {        \
 624   "r0", "r2", "r1", "r3", \
 625   "a0", "a1", "sb", "fb", "sp", \
 626   "pc", "flg", "argp", \
 627   "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
 628 }
 629
 630 #define ADDITIONAL_REGISTER_NAMES { \
 631   {"r0l", 0}, \
 632   {"r1l", 2}, \
 633   {"r0r2", 0}, \
 634   {"r1r3", 2}, \
 635   {"a0a1", 4}, \
 636   {"r0r2r1r3", 0} }
 637
 638 #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
 639 #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
 640 #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
 641
 642 #undef USER_LABEL_PREFIX
 643 #define USER_LABEL_PREFIX "_"
 644
 645 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
 646 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
 647
 648 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 649         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
 650
 651 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 652         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
 653
 654
 655 /* Output of Dispatch Tables */
 656
 657 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
 658         fprintf (S, "\t.word L%d\n", V)
 659
 660 /* Assembler Commands for Exception Regions */
 661
 662 #define DWARF_CIE_DATA_ALIGNMENT -1
 663
 664 /* Assembler Commands for Alignment */
 665
 666 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 667         fprintf (STREAM, "\t.p2align\t%d\n", POWER);
 668
 669 /* Controlling Debugging Information Format */
 670
 671 #define DWARF2_ADDR_SIZE        4
 672
 673 /* Miscellaneous Parameters */
 674
 675 #define HAS_LONG_COND_BRANCH false
 676 #define HAS_LONG_UNCOND_BRANCH true
 677 #define CASE_VECTOR_MODE SImode
 678 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
 679
 680 #define MOVE_MAX 4
 681 #define TRULY_NOOP_TRUNCATION(op,ip) 1
 682
 683 #define STORE_FLAG_VALUE 1
 684
 685 /* 16- or 24-bit pointers */
 686 #define Pmode (TARGET_A16 ? HImode : PSImode)
 687 #define FUNCTION_MODE QImode
 688
 689 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
 690
 691 #endif