Merge from mainline (165734:167278).
[official-gcc/graphite-test-results.git] / gcc / config / stormy16 / stormy16.h
blob1781bc3adea05ee6a20fef6033a2081c0dde081d
1 /* Xstormy16 cpu description.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007,
3 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Red Hat, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Driver configuration. */
25 #undef ASM_SPEC
26 #define ASM_SPEC ""
28 /* For xstormy16:
29 - If -msim is specified, everything is built and linked as for the sim.
30 - If -T is specified, that linker script is used, and it should provide
31 appropriate libraries.
32 - If neither is specified, everything is built as for the sim, but no
33 I/O support is assumed. */
34 #undef LIB_SPEC
35 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)"
37 #undef STARTFILE_SPEC
38 #define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
40 #undef ENDFILE_SPEC
41 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
44 /* Run-time target specifications. */
46 #define TARGET_CPU_CPP_BUILTINS() \
47 do \
48 { \
49 builtin_define_std ("xstormy16"); \
50 builtin_assert ("machine=xstormy16"); \
51 builtin_assert ("cpu=xstormy16"); \
52 } \
53 while (0)
55 #define TARGET_VERSION fprintf (stderr, " (xstormy16 cpu core)");
57 /* Storage Layout. */
59 #define BITS_BIG_ENDIAN 1
61 #define BYTES_BIG_ENDIAN 0
63 #define WORDS_BIG_ENDIAN 0
65 #define UNITS_PER_WORD 2
67 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
68 do \
69 { \
70 if (GET_MODE_CLASS (MODE) == MODE_INT \
71 && GET_MODE_SIZE (MODE) < 2) \
72 (MODE) = HImode; \
73 } \
74 while (0)
76 #define PARM_BOUNDARY 16
78 #define STACK_BOUNDARY 16
80 #define FUNCTION_BOUNDARY 16
82 #define BIGGEST_ALIGNMENT 16
84 #define DATA_ALIGNMENT(TYPE, ALIGN) \
85 (TREE_CODE (TYPE) == ARRAY_TYPE \
86 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
87 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
89 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
90 (TREE_CODE (EXP) == STRING_CST \
91 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
93 #define STRICT_ALIGNMENT 1
95 #define PCC_BITFIELD_TYPE_MATTERS 1
97 /* Layout of Source Language Data Types. */
99 #define INT_TYPE_SIZE 16
101 #define SHORT_TYPE_SIZE 16
103 #define LONG_TYPE_SIZE 32
105 #define LONG_LONG_TYPE_SIZE 64
107 #define FLOAT_TYPE_SIZE 32
109 #define DOUBLE_TYPE_SIZE 64
111 #define LONG_DOUBLE_TYPE_SIZE 64
113 #define DEFAULT_SIGNED_CHAR 0
115 #define SIZE_TYPE "unsigned int"
117 #define PTRDIFF_TYPE "int"
119 #undef WCHAR_TYPE_SIZE
120 #define WCHAR_TYPE_SIZE 32
123 /* Register Basics. */
125 #define FIRST_PSEUDO_REGISTER 19
127 #define FIXED_REGISTERS \
128 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 }
130 #define CALL_USED_REGISTERS \
131 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 }
134 /* Order of allocation of registers. */
136 #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 }
139 /* How Values Fit in Registers. */
141 #define HARD_REGNO_NREGS(REGNO, MODE) \
142 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
144 #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode)
146 /* A C expression that is nonzero if it is desirable to choose register
147 allocation so as to avoid move instructions between a value of mode MODE1
148 and a value of mode MODE2.
150 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
151 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
152 zero. */
153 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode)
156 /* Register Classes. */
158 enum reg_class
160 NO_REGS,
161 R0_REGS,
162 R1_REGS,
163 TWO_REGS,
164 R2_REGS,
165 EIGHT_REGS,
166 R8_REGS,
167 ICALL_REGS,
168 GENERAL_REGS,
169 ALL_REGS,
170 LIM_REG_CLASSES
173 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
175 #define IRA_COVER_CLASSES \
177 GENERAL_REGS, LIM_REG_CLASSES \
180 #define REG_CLASS_NAMES \
182 "NO_REGS", \
183 "R0_REGS", \
184 "R1_REGS", \
185 "TWO_REGS", \
186 "R2_REGS", \
187 "EIGHT_REGS", \
188 "R8_REGS", \
189 "ICALL_REGS", \
190 "GENERAL_REGS", \
191 "ALL_REGS" \
194 #define REG_CLASS_CONTENTS \
196 { 0x00000 }, \
197 { 0x00001 }, \
198 { 0x00002 }, \
199 { 0x00003 }, \
200 { 0x00004 }, \
201 { 0x000FF }, \
202 { 0x00100 }, \
203 { 0x00300 }, \
204 { 0x6FFFF }, \
205 { (1 << FIRST_PSEUDO_REGISTER) - 1 } \
208 #define REGNO_REG_CLASS(REGNO) \
209 ( (REGNO) == 0 ? R0_REGS \
210 : (REGNO) == 1 ? R1_REGS \
211 : (REGNO) == 2 ? R2_REGS \
212 : (REGNO) < 8 ? EIGHT_REGS \
213 : (REGNO) == 8 ? R8_REGS \
214 : (REGNO) <= 18 ? GENERAL_REGS \
215 : ALL_REGS)
217 #define BASE_REG_CLASS GENERAL_REGS
219 #define INDEX_REG_CLASS GENERAL_REGS
221 /* The following letters are unavailable, due to being used as
222 constraints:
223 '0'..'9'
224 '<', '>'
225 'E', 'F', 'G', 'H'
226 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
227 'Q', 'R', 'S', 'T', 'U'
228 'V', 'X'
229 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's'. */
231 #define REG_CLASS_FROM_LETTER(CHAR) \
232 ( (CHAR) == 'a' ? R0_REGS \
233 : (CHAR) == 'b' ? R1_REGS \
234 : (CHAR) == 'c' ? R2_REGS \
235 : (CHAR) == 'd' ? R8_REGS \
236 : (CHAR) == 'e' ? EIGHT_REGS \
237 : (CHAR) == 't' ? TWO_REGS \
238 : (CHAR) == 'z' ? ICALL_REGS \
239 : NO_REGS)
241 #define REGNO_OK_FOR_BASE_P(NUM) 1
243 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
245 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
246 xstormy16_preferred_reload_class (X, CLASS)
248 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
249 xstormy16_preferred_reload_class (X, CLASS)
251 /* This chip has the interesting property that only the first eight
252 registers can be moved to/from memory. */
253 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
254 xstormy16_secondary_reload_class (CLASS, MODE, X)
256 #define CLASS_MAX_NREGS(CLASS, MODE) \
257 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
259 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
260 ( (C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 3 \
261 : (C) == 'J' ? exact_log2 (VALUE) != -1 \
262 : (C) == 'K' ? exact_log2 (~(VALUE)) != -1 \
263 : (C) == 'L' ? (VALUE) >= 0 && (VALUE) <= 255 \
264 : (C) == 'M' ? (VALUE) >= -255 && (VALUE) <= 0 \
265 : (C) == 'N' ? (VALUE) >= -3 && (VALUE) <= 0 \
266 : (C) == 'O' ? (VALUE) >= 1 && (VALUE) <= 4 \
267 : (C) == 'P' ? (VALUE) >= -4 && (VALUE) <= -1 \
268 : 0 )
270 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
272 #define EXTRA_CONSTRAINT(VALUE, C) \
273 xstormy16_extra_constraint_p (VALUE, C)
276 /* Basic Stack Layout. */
278 /* We want to use post-increment instructions to push things on the stack,
279 because we don't have any pre-increment ones. */
280 #define STACK_PUSH_CODE POST_INC
282 #define FRAME_GROWS_DOWNWARD 0
284 #define ARGS_GROW_DOWNWARD 1
286 #define STARTING_FRAME_OFFSET 0
288 #define FIRST_PARM_OFFSET(FUNDECL) 0
290 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
291 ((COUNT) == 0 \
292 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
293 : NULL_RTX)
295 #define INCOMING_RETURN_ADDR_RTX \
296 gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4)))
298 #define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4)
301 /* Register That Address the Stack Frame. */
303 #define STATIC_CHAIN_REGNUM 1
304 #define HARD_FRAME_POINTER_REGNUM 13
305 #define STACK_POINTER_REGNUM 15
306 #define CARRY_REGNUM 16
307 #define FRAME_POINTER_REGNUM 17
308 #define ARG_POINTER_REGNUM 18
311 /* Eliminating the Frame Pointer and the Arg Pointer. */
313 #define ELIMINABLE_REGS \
315 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
316 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
317 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
318 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
321 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
322 (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO)
325 /* Passing Function Arguments on the Stack. */
327 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
330 /* Function Arguments in Registers. */
332 #define NUM_ARGUMENT_REGISTERS 6
333 #define FIRST_ARGUMENT_REGISTER 2
335 #define XSTORMY16_WORD_SIZE(TYPE, MODE) \
336 ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
337 + 1) \
338 / 2)
340 /* For this platform, the value of CUMULATIVE_ARGS is the number of words
341 of arguments that have been passed in registers so far. */
342 #define CUMULATIVE_ARGS int
344 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
345 (CUM) = 0
347 #define FUNCTION_ARG_REGNO_P(REGNO) \
348 ((REGNO) >= FIRST_ARGUMENT_REGISTER \
349 && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS)
352 /* How Scalar Function Values are Returned. */
354 /* The number of the hard register that is used to return a scalar value from a
355 function call. */
356 #define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER
358 #define FUNCTION_VALUE(VALTYPE, FUNC) \
359 xstormy16_function_value (VALTYPE, FUNC)
361 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RETURN_VALUE_REGNUM)
363 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RETURN_VALUE_REGNUM)
366 /* Function Entry and Exit. */
368 #define EPILOGUE_USES(REGNO) \
369 xstormy16_epilogue_uses (REGNO)
372 /* Generating Code for Profiling. */
374 /* This declaration must be present, but it can be an abort if profiling is
375 not implemented. */
377 #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler ()
380 /* Trampolines for Nested Functions. */
382 #define TRAMPOLINE_SIZE 8
383 #define TRAMPOLINE_ALIGNMENT 16
386 /* Addressing Modes. */
388 #define HAVE_POST_INCREMENT 1
390 #define HAVE_PRE_DECREMENT 1
392 #define MAX_REGS_PER_ADDRESS 1
394 #ifdef REG_OK_STRICT
395 #define REG_OK_FOR_BASE_P(X) \
396 (REGNO_OK_FOR_BASE_P (REGNO (X)) && (REGNO (X) < FIRST_PSEUDO_REGISTER))
397 #else
398 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
399 #endif
401 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
403 /* On this chip, this is true if the address is valid with an offset
404 of 0 but not of 6, because in that case it cannot be used as an
405 address for DImode or DFmode, or if the address is a post-increment
406 or pre-decrement address. */
407 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
408 if (xstormy16_mode_dependent_address_p (ADDR)) \
409 goto LABEL
411 #define LEGITIMATE_CONSTANT_P(X) 1
414 /* Describing Relative Costs of Operations. */
416 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
418 #define MEMORY_MOVE_COST(M,C,I) (5 + memory_move_secondary_cost (M, C, I))
420 #define BRANCH_COST(speed_p, predictable_p) 5
422 #define SLOW_BYTE_ACCESS 0
424 #define NO_FUNCTION_CSE
427 /* Dividing the output into sections. */
429 #define TEXT_SECTION_ASM_OP ".text"
431 #define DATA_SECTION_ASM_OP ".data"
433 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
435 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
436 There are no shared libraries on this target so these sections need
437 not be writable.
439 Defined in elfos.h. */
441 #undef CTORS_SECTION_ASM_OP
442 #undef DTORS_SECTION_ASM_OP
443 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
444 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
446 #define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections
448 #define JUMP_TABLES_IN_TEXT_SECTION 1
450 /* The Overall Framework of an Assembler File. */
452 #define ASM_COMMENT_START ";"
454 #define ASM_APP_ON "#APP\n"
456 #define ASM_APP_OFF "#NO_APP\n"
458 /* Output of Data. */
460 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|')
462 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
463 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
464 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
465 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
468 /* Output and Generation of Labels. */
469 #define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0)
471 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \
472 do \
474 const char *rn = XSTR (SYMBOL, 0); \
476 if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \
477 ASM_OUTPUT_LABEL_REF ((STREAM), rn); \
478 else \
479 assemble_name (STREAM, rn); \
481 while (0)
483 #define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \
484 do \
486 fputs ("@fptr(", STREAM); \
487 assemble_name (STREAM, NAME); \
488 fputc (')', STREAM); \
490 while (0)
492 /* Globalizing directive for a label. */
493 #define GLOBAL_ASM_OP "\t.globl "
496 /* Output of Assembler Instructions. */
498 #define REGISTER_NAMES \
499 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
500 "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" }
502 #define ADDITIONAL_REGISTER_NAMES \
503 { { "r14", 14 }, \
504 { "r15", 15 } }
506 #define PRINT_OPERAND(STREAM, X, CODE) xstormy16_print_operand (STREAM, X, CODE)
508 #define PRINT_OPERAND_ADDRESS(STREAM, X) xstormy16_print_operand_address (STREAM, X)
510 /* USER_LABEL_PREFIX is defined in svr4.h. */
511 #define REGISTER_PREFIX ""
512 #define LOCAL_LABEL_PREFIX "."
513 #define USER_LABEL_PREFIX ""
514 #define IMMEDIATE_PREFIX "#"
516 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
517 fprintf (STREAM, "\tpush %d\n", REGNO)
519 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
520 fprintf (STREAM, "\tpop %d\n", REGNO)
523 /* Output of dispatch tables. */
525 /* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because
526 this could cause label alignment to appear between the 'br' and the table,
527 which would be bad. Instead, it controls the output of the table
528 itself. */
529 #define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \
530 xstormy16_output_addr_vec (file, LABEL, BODY)
532 /* Alignment for ADDR_VECs is the same as for code. */
533 #define ADDR_VEC_ALIGN(ADDR_VEC) 1
536 /* Assembler Commands for Exception Regions. */
538 #define DWARF2_UNWIND_INFO 0
539 #define DWARF_CIE_DATA_ALIGNMENT 1
541 #undef DONT_USE_BUILTIN_SETJMP
542 #define JMP_BUF_SIZE 8
544 /* Assembler Commands for Alignment. */
546 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
547 fprintf ((STREAM), "\t.p2align %d\n", (POWER))
550 /* Macros Affecting all Debug Formats. */
552 /* Defined in svr4.h. */
553 #undef PREFERRED_DEBUGGING_TYPE
554 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
557 /* Macros for SDB and Dwarf Output. */
559 /* Define this macro if addresses in Dwarf 2 debugging info should not
560 be the same size as pointers on the target architecture. The
561 macro's value should be the size, in bytes, to use for addresses in
562 the debugging info.
564 Some architectures use word addresses to refer to code locations,
565 but Dwarf 2 info always uses byte addresses. On such machines,
566 Dwarf 2 addresses need to be larger than the architecture's
567 pointers. */
568 #define DWARF2_ADDR_SIZE 4
571 /* Miscellaneous Parameters. */
573 #define CASE_VECTOR_MODE SImode
575 #define WORD_REGISTER_OPERATIONS
577 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
579 #define MOVE_MAX 2
581 #define SHIFT_COUNT_TRUNCATED 1
583 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
585 #define Pmode HImode
587 #define FUNCTION_MODE HImode
589 #define NO_IMPLICIT_EXTERN_C