1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Bit-wise operations (and, ior, xor, shift)
24 ; On the R8C and M16C, "address" for bit instructions is usually (but
25 ; not always!) the *bit* address, not the *byte* address. This
26 ; confuses gcc, so we avoid cases where gcc would produce the wrong
27 ; code. We're left with absolute addresses and registers, and the odd
28 ; case of shifting a bit by a variable.
30 ; On the M32C, "address" for bit instructions is a regular address,
31 ; and the bit number is stored in a separate field. Thus, we can let
32 ; gcc do more interesting things. However, the M32C cannot set all
33 ; the bits in a 16-bit register, which the R8C/M16C can do.
35 ; However, it all means that we end up with two sets of patterns, one
38 ;;----------------------------------------------------------------------
40 ;; First off, all the ways we can set one bit, other than plain IOR.
42 (define_insn "bset_qi"
43 [(set (match_operand:QI 0 "memsym_operand" "+Si")
44 (ior:QI (subreg:QI (ashift:HI (const_int 1)
45 (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
46 (match_operand:QI 2 "memsym_operand" "0")))]
49 [(set_attr "flags" "n")]
52 (define_insn "bset_hi"
53 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
55 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
59 [(set_attr "flags" "n")]
62 ;;----------------------------------------------------------------------
64 ;; Now all the ways we can clear one bit, other than plain AND.
66 ; This is odd because the shift patterns use QI counts, but we can't
67 ; easily put QI in $aN without causing problems elsewhere.
68 (define_insn "bclr_qi"
69 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
71 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
75 [(set_attr "flags" "n")]
79 ;;----------------------------------------------------------------------
81 ;; Now the generic patterns.
83 (define_insn "andqi3_16"
84 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
85 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
86 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
95 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
98 (define_insn "andhi3_16"
99 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
100 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
101 (match_operand:HI 2 "mrai_operand" "ImB,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
112 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
115 (define_insn "andsi3"
116 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
117 (and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
118 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
121 switch (which_alternative)
124 output_asm_insn (\"and.w %X2,%h0\",operands);
125 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
126 return \"and.w %X2,%H0\";
128 return \"and.w %h2,%h0\;and.w %H2,%H0\";
130 output_asm_insn (\"and.w %X2,%h0\",operands);
131 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
132 return \"and.w %X2,%H0\";
134 return \"and.w %h2,%h0\;and.w %H2,%H0\";
136 return \"and.w %h2,%h0\;and.w %H2,%H0\";
138 return \"and.w %h2,%h0\;and.w %H2,%H0\";
142 [(set_attr "flags" "x,x,x,x,x,x")]
146 (define_insn "iorqi3_16"
147 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
148 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
149 (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
158 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
161 (define_insn "iorhi3_16"
162 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
163 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
164 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
174 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
177 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
179 (define_insn "andqi3_24"
180 [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
181 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
182 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
191 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
194 (define_insn "andhi3_24"
195 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm")
196 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
197 (match_operand:HI 2 "mrai_operand" "ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
208 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
213 (define_insn "iorqi3_24"
214 [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
215 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
216 (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
224 [(set_attr "flags" "n,sz,sz,sz,sz")]
227 (define_insn "iorhi3_24"
228 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm")
229 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
230 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
241 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
245 ; ----------------------------------------------------------------------
247 (define_expand "andqi3"
248 [(set (match_operand:QI 0 "mra_operand" "")
249 (and:QI (match_operand:QI 1 "mra_operand" "")
250 (match_operand:QI 2 "mrai_operand" "")))]
253 emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
255 emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
259 (define_expand "andhi3"
260 [(set (match_operand:HI 0 "mra_operand" "")
261 (and:HI (match_operand:HI 1 "mra_operand" "")
262 (match_operand:HI 2 "mrai_operand" "")))]
265 emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
267 emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
271 (define_expand "iorqi3"
272 [(set (match_operand:QI 0 "mra_operand" "")
273 (ior:QI (match_operand:QI 1 "mra_operand" "")
274 (match_operand:QI 2 "mrai_operand" "")))]
277 emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
279 emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
283 (define_expand "iorhi3"
284 [(set (match_operand:HI 0 "mra_operand" "")
285 (ior:HI (match_operand:HI 1 "mra_operand" "")
286 (match_operand:HI 2 "mrai_operand" "")))]
289 emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
291 emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
295 (define_insn "iorsi3"
296 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
297 (ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
298 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
301 switch (which_alternative)
304 output_asm_insn (\"or.w %X2,%h0\",operands);
305 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
306 return \"or.w %X2,%H0\";
308 return \"or.w %h2,%h0\;or.w %H2,%H0\";
310 output_asm_insn (\"or.w %X2,%h0\",operands);
311 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
312 return \"or.w %X2,%H0\";
314 return \"or.w %h2,%h0\;or.w %H2,%H0\";
316 return \"or.w %h2,%h0\;or.w %H2,%H0\";
318 return \"or.w %h2,%h0\;or.w %H2,%H0\";
322 [(set_attr "flags" "x,x,x,x,x,x")]
325 (define_insn "xorqi3"
326 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
327 (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
328 (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
331 [(set_attr "flags" "sz,sz,sz,sz")]
334 (define_insn "xorhi3"
335 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
336 (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
337 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
340 [(set_attr "flags" "sz,sz,sz,sz")]
343 (define_insn "xorsi3"
344 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
345 (xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
346 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
349 switch (which_alternative)
352 output_asm_insn (\"xor.w %X2,%h0\",operands);
353 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
354 return \"xor.w %X2,%H0\";
356 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
358 output_asm_insn (\"xor.w %X2,%h0\",operands);
359 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
360 return \"xor.w %X2,%H0\";
362 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
364 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
366 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
370 [(set_attr "flags" "x,x,x,x,x,x")]
373 (define_insn "one_cmplqi2"
374 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
375 (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
378 [(set_attr "flags" "sz,sz")]
381 (define_insn "one_cmplhi2"
382 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
383 (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
386 [(set_attr "flags" "sz,sz")]
389 ; Optimizations using bit opcodes
391 ; We need this because combine only looks at three insns at a time,
392 ; and the bclr_qi pattern uses four - mov, shift, not, and. GCC
393 ; should never expand this pattern, because it only shifts a constant
394 ; by a constant, so gcc should do that itself.
395 (define_insn "shift1_qi"
396 [(set (match_operand:QI 0 "mra_operand" "=Rqi")
397 (ashift:QI (const_int 1)
398 (match_operand 1 "const_int_operand" "In4")))]
400 "mov.b\t#1,%0\n\tshl.b\t%1,%0"
402 (define_insn "shift1_hi"
403 [(set (match_operand:HI 0 "mra_operand" "=Rhi")
404 (ashift:HI (const_int 1)
405 (match_operand 1 "const_int_operand" "In4")))]
407 "mov.w\t#1,%0\n\tshl.w\t%1,%0"
410 ; Generic insert-bit expander, needed so that we can use the bit
411 ; opcodes for volatile bitfields.
413 (define_expand "insv"
414 [(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
415 (match_operand 1 "const_int_operand" "")
416 (match_operand 2 "const_int_operand" ""))
417 (match_operand:HI 3 "const_int_operand" ""))]
419 "if (m32c_expand_insv (operands))