gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 /* Driver configuration.  */
  23
  24 /* The svr4.h LIB_SPEC with -leval and --*group tacked on */
  25 #undef  LIB_SPEC
  26 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  27
  28 #undef STARTFILE_SPEC
  29 #undef ENDFILE_SPEC
  30
  31 \f
  32 /* Run-time target specifications.  */
  33
  34 #define TARGET_CPU_CPP_BUILTINS()               \
  35   do                                            \
  36     {                                           \
  37       builtin_define ("__iq2000__");            \
  38       builtin_assert ("cpu=iq2000");            \
  39       builtin_assert ("machine=iq2000");        \
  40     }                                           \
  41   while (0)
  42
  43 /* Macros used in the machine description to test the flags.  */
  44
  45 #define TARGET_STATS            0
  46
  47 #define TARGET_DEBUG_MODE       0
  48 #define TARGET_DEBUG_A_MODE     0
  49 #define TARGET_DEBUG_B_MODE     0
  50 #define TARGET_DEBUG_C_MODE     0
  51 #define TARGET_DEBUG_D_MODE     0
  52
  53 #ifndef IQ2000_ISA_DEFAULT
  54 #define IQ2000_ISA_DEFAULT 1
  55 #endif
  56
  57 #define IQ2000_VERSION "[1.0]"
  58
  59 #ifndef MACHINE_TYPE
  60 #define MACHINE_TYPE "IQ2000"
  61 #endif
  62
  63 #ifndef TARGET_VERSION_INTERNAL
  64 #define TARGET_VERSION_INTERNAL(STREAM)                                 \
  65   fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
  66 #endif
  67
  68 #ifndef TARGET_VERSION
  69 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
  70 #endif
  71 \f
  72 /* Storage Layout.  */
  73
  74 #define BITS_BIG_ENDIAN                 0
  75 #define BYTES_BIG_ENDIAN                1
  76 #define WORDS_BIG_ENDIAN                1
  77 #define BITS_PER_WORD                   32
  78 #define MAX_BITS_PER_WORD               64
  79 #define UNITS_PER_WORD                  4
  80 #define MIN_UNITS_PER_WORD              4
  81 #define POINTER_SIZE                    32
  82
  83 /* Define this macro if it is advisable to hold scalars in registers
  84    in a wider mode than that declared by the program.  In such cases,
  85    the value is constrained to be within the bounds of the declared
  86    type, but kept valid in the wider mode.  The signedness of the
  87    extension may differ from that of the type.
  88
  89    We promote any value smaller than SImode up to SImode.  */
  90
  91 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  92   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  93       && GET_MODE_SIZE (MODE) < 4)              \
  94     (MODE) = SImode;
  95
  96 #define PARM_BOUNDARY 32
  97
  98 #define STACK_BOUNDARY 64
  99
 100 #define FUNCTION_BOUNDARY 32
 101
 102 #define BIGGEST_ALIGNMENT 64
 103
 104 #undef  DATA_ALIGNMENT
 105 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 106   ((((ALIGN) < BITS_PER_WORD)                                           \
 107     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 108         || TREE_CODE (TYPE) == UNION_TYPE                               \
 109         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 110
 111 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 112   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 113    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 114
 115 #define EMPTY_FIELD_BOUNDARY 32
 116
 117 #define STRUCTURE_SIZE_BOUNDARY 8
 118
 119 #define STRICT_ALIGNMENT 1
 120
 121 #define PCC_BITFIELD_TYPE_MATTERS 1
 122
 123 \f
 124 /* Layout of Source Language Data Types.  */
 125
 126 #define INT_TYPE_SIZE           32
 127 #define SHORT_TYPE_SIZE         16
 128 #define LONG_TYPE_SIZE          32
 129 #define LONG_LONG_TYPE_SIZE     64
 130 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 131 #define FLOAT_TYPE_SIZE         32
 132 #define DOUBLE_TYPE_SIZE        64
 133 #define LONG_DOUBLE_TYPE_SIZE   64
 134 #define DEFAULT_SIGNED_CHAR     1
 135
 136 \f
 137 /* Register Basics.  */
 138
 139 /* On the IQ2000, we have 32 integer registers.  */
 140 #define FIRST_PSEUDO_REGISTER 33
 141
 142 #define FIXED_REGISTERS                                                 \
 143 {                                                                       \
 144   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 145   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 146 }
 147
 148 #define CALL_USED_REGISTERS                                             \
 149 {                                                                       \
 150   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 151   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 152 }
 153
 154 \f
 155 /* Order of allocation of registers.  */
 156
 157 #define REG_ALLOC_ORDER                                                 \
 158 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 159   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 160 }
 161
 162 \f
 163 /* How Values Fit in Registers.  */
 164
 165 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 166   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 167
 168 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 169  ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
 170   ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4             \
 171   : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 172
 173 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 174   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 175     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 176    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 177        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 178
 179 #define AVOID_CCMODE_COPIES
 180
 181 \f
 182 /* Register Classes.  */
 183
 184 enum reg_class
 185 {
 186   NO_REGS,                      /* No registers in set.  */
 187   GR_REGS,                      /* Integer registers.  */
 188   ALL_REGS,                     /* All registers.  */
 189   LIM_REG_CLASSES               /* Max value + 1.  */
 190 };
 191
 192 #define GENERAL_REGS GR_REGS
 193
 194 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 195
 196 #define IRA_COVER_CLASSES       \
 197 {                               \
 198   GR_REGS, LIM_REG_CLASSES      \
 199 }
 200
 201 #define REG_CLASS_NAMES                                         \
 202 {                                                               \
 203   "NO_REGS",                                                    \
 204   "GR_REGS",                                                    \
 205   "ALL_REGS"                                                    \
 206 }
 207
 208 #define REG_CLASS_CONTENTS                                      \
 209 {                                                               \
 210   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 211   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 212   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 213 }
 214
 215 #define REGNO_REG_CLASS(REGNO) \
 216 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 217
 218 #define BASE_REG_CLASS  (GR_REGS)
 219
 220 #define INDEX_REG_CLASS NO_REGS
 221
 222 #define REG_CLASS_FROM_LETTER(C) \
 223   ((C) == 'd' ? GR_REGS :        \
 224    (C) == 'b' ? ALL_REGS :       \
 225    (C) == 'y' ? GR_REGS :        \
 226    NO_REGS)
 227
 228 #define REGNO_OK_FOR_INDEX_P(regno)     0
 229
 230 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 231   ((CLASS) != ALL_REGS                                          \
 232    ? (CLASS)                                                    \
 233    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 234        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 235       ? (GR_REGS)                                               \
 236       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 237           || GET_MODE (X) == VOIDmode)                          \
 238          ? (GR_REGS)                                            \
 239          : (CLASS))))
 240
 241 #define CLASS_MAX_NREGS(CLASS, MODE)    \
 242   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 243
 244 /* For IQ2000:
 245
 246    `I'  is used for the range of constants an arithmetic insn can
 247         actually contain (16-bits signed integers).
 248
 249    `J'  is used for the range which is just zero (i.e., $r0).
 250
 251    `K'  is used for the range of constants a logical insn can actually
 252         contain (16-bit zero-extended integers).
 253
 254    `L'  is used for the range of constants that be loaded with lui
 255         (i.e., the bottom 16 bits are zero).
 256
 257    `M'  is used for the range of constants that take two words to load
 258         (i.e., not matched by `I', `K', and `L').
 259
 260    `N'  is used for constants 0xffffnnnn or 0xnnnnffff
 261
 262    `O'  is a 5-bit zero-extended integer.  */
 263
 264 #define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
 265   ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
 266    : (C) == 'J' ? ((VALUE) == 0)                                        \
 267    : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)          \
 268    : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0                          \
 269                    && (((VALUE) & ~2147483647) == 0                     \
 270                        || ((VALUE) & ~2147483647) == ~2147483647))      \
 271    : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)                       \
 272                    && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)          \
 273                    && (((VALUE) & 0x0000ffff) != 0                      \
 274                        || (((VALUE) & ~2147483647) != 0                 \
 275                            && ((VALUE) & ~2147483647) != ~2147483647))) \
 276    : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff)                       \
 277                    || (((VALUE) & 0xffff0000) == 0xffff0000))           \
 278    : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40)    \
 279    : 0)
 280
 281 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
 282   ((C) == 'G'                                                           \
 283    && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
 284
 285 /* `R' is for memory references which take 1 word for the instruction.  */
 286
 287 #define EXTRA_CONSTRAINT(OP,CODE)                                       \
 288   (((CODE) == 'R')        ? simple_memory_operand (OP, GET_MODE (OP))   \
 289    : FALSE)
 290
 291 \f
 292 /* Basic Stack Layout.  */
 293
 294 #define STACK_GROWS_DOWNWARD
 295
 296 #define FRAME_GROWS_DOWNWARD 0
 297
 298 #define STARTING_FRAME_OFFSET                                           \
 299   (crtl->outgoing_args_size)
 300
 301 /* Use the default value zero.  */
 302 /* #define STACK_POINTER_OFFSET 0 */
 303
 304 #define FIRST_PARM_OFFSET(FNDECL) 0
 305
 306 /* The return address for the current frame is in r31 if this is a leaf
 307    function.  Otherwise, it is on the stack.  It is at a variable offset
 308    from sp/fp/ap, so we define a fake hard register rap which is a
 309    pointer to the return address on the stack.  This always gets eliminated
 310    during reload to be either the frame pointer or the stack pointer plus
 311    an offset.  */
 312
 313 #define RETURN_ADDR_RTX(count, frame)                                   \
 314   (((count) == 0)                                                       \
 315    ? (leaf_function_p ()                                                \
 316       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 317       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 318                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 319     : (rtx) 0)
 320
 321 /* Before the prologue, RA lives in r31.  */
 322 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 323
 324 \f
 325 /* Register That Address the Stack Frame.  */
 326
 327 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 328 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 329 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 330 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 331 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 332 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 333
 334 \f
 335 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 336
 337 #define ELIMINABLE_REGS                                                 \
 338 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 339  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 340  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 341  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 342  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 343  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 344  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 345
 346 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 347         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 348 \f
 349 /* Passing Function Arguments on the Stack.  */
 350
 351 /* #define PUSH_ROUNDING(BYTES) 0 */
 352
 353 #define ACCUMULATE_OUTGOING_ARGS 1
 354
 355 #define REG_PARM_STACK_SPACE(FNDECL) 0
 356
 357 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 358
 359 \f
 360 /* Function Arguments in Registers.  */
 361
 362 #define MAX_ARGS_IN_REGISTERS 8
 363
 364 typedef struct iq2000_args
 365 {
 366   int gp_reg_found;             /* Whether a gp register was found yet.  */
 367   unsigned int arg_number;      /* Argument number.  */
 368   unsigned int arg_words;       /* # total words the arguments take.  */
 369   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 370   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 371   int fp_code;                  /* Mode of FP arguments.  */
 372   unsigned int num_adjusts;     /* Number of adjustments made.  */
 373                                 /* Adjustments made to args pass in regs.  */
 374   struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
 375 } CUMULATIVE_ARGS;
 376
 377 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 378    for a call to a function whose data type is FNTYPE.
 379    For a library call, FNTYPE is 0.  */
 380 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 381   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 382
 383 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 384   (! BYTES_BIG_ENDIAN                                                   \
 385    ? upward                                                             \
 386    : (((MODE) == BLKmode                                                \
 387        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 388           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 389        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 390           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 391       ? downward : upward))
 392
 393 #define FUNCTION_ARG_REGNO_P(N)                                         \
 394   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 395
 396 \f
 397 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 398
 399 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N)
 400
 401 \f
 402 /* How Large Values are Returned.  */
 403
 404 #define DEFAULT_PCC_STRUCT_RETURN 0
 405 \f
 406 /* Function Entry and Exit.  */
 407
 408 #define EXIT_IGNORE_STACK 1
 409
 410 \f
 411 /* Generating Code for Profiling.  */
 412
 413 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 414 {                                                                       \
 415   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 416   fprintf (FILE, "\t.set\tnoat\n");                                     \
 417   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 418            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 419   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 420   fprintf (FILE,                                                        \
 421            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 422            "subu",                                                      \
 423            reg_names[STACK_POINTER_REGNUM],                             \
 424            reg_names[STACK_POINTER_REGNUM],                             \
 425            Pmode == DImode ? 16 : 8);                                   \
 426   fprintf (FILE, "\t.set\treorder\n");                                  \
 427   fprintf (FILE, "\t.set\tat\n");                                       \
 428 }
 429
 430 \f
 431 /* Trampolines for Nested Functions.  */
 432
 433 #define TRAMPOLINE_CODE_SIZE  (8*4)
 434 #define TRAMPOLINE_SIZE       (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode))
 435 #define TRAMPOLINE_ALIGNMENT  GET_MODE_ALIGNMENT (Pmode)
 436
 437 \f
 438 /* Addressing Modes.  */
 439
 440 #define CONSTANT_ADDRESS_P(X)                                           \
 441   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 442     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 443     || (GET_CODE (X) == CONST)))
 444
 445 #define MAX_REGS_PER_ADDRESS 1
 446
 447 #define REG_OK_FOR_INDEX_P(X) 0
 448
 449 #define LEGITIMATE_CONSTANT_P(X) (1)
 450
 451 \f
 452 /* Describing Relative Costs of Operations.  */
 453
 454 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 455
 456 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 457   (TO_P ? 2 : 16)
 458
 459 #define BRANCH_COST(speed_p, predictable_p) 2
 460
 461 #define SLOW_BYTE_ACCESS 1
 462
 463 #define NO_FUNCTION_CSE 1
 464
 465 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 466   if (REG_NOTE_KIND (LINK) != 0)                                        \
 467     (COST) = 0; /* Anti or output dependence.  */
 468
 469 \f
 470 /* Dividing the output into sections.  */
 471
 472 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 473
 474 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 475
 476 \f
 477 /* The Overall Framework of an Assembler File.  */
 478
 479 #define ASM_COMMENT_START " #"
 480
 481 #define ASM_APP_ON "#APP\n"
 482
 483 #define ASM_APP_OFF "#NO_APP\n"
 484
 485 \f
 486 /* Output and Generation of Labels.  */
 487
 488 #undef ASM_GENERATE_INTERNAL_LABEL
 489 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 490   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 491
 492 #define GLOBAL_ASM_OP "\t.globl\t"
 493
 494 \f
 495 /* Output of Assembler Instructions.  */
 496
 497 #define REGISTER_NAMES                                                  \
 498 {                                                                       \
 499  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 500  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 501  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 502  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 503 }
 504
 505 #define ADDITIONAL_REGISTER_NAMES                                       \
 506 {                                                                       \
 507   { "%0",        0 + GP_REG_FIRST },                                    \
 508   { "%1",        1 + GP_REG_FIRST },                                    \
 509   { "%2",        2 + GP_REG_FIRST },                                    \
 510   { "%3",        3 + GP_REG_FIRST },                                    \
 511   { "%4",        4 + GP_REG_FIRST },                                    \
 512   { "%5",        5 + GP_REG_FIRST },                                    \
 513   { "%6",        6 + GP_REG_FIRST },                                    \
 514   { "%7",        7 + GP_REG_FIRST },                                    \
 515   { "%8",        8 + GP_REG_FIRST },                                    \
 516   { "%9",        9 + GP_REG_FIRST },                                    \
 517   { "%10",      10 + GP_REG_FIRST },                                    \
 518   { "%11",      11 + GP_REG_FIRST },                                    \
 519   { "%12",      12 + GP_REG_FIRST },                                    \
 520   { "%13",      13 + GP_REG_FIRST },                                    \
 521   { "%14",      14 + GP_REG_FIRST },                                    \
 522   { "%15",      15 + GP_REG_FIRST },                                    \
 523   { "%16",      16 + GP_REG_FIRST },                                    \
 524   { "%17",      17 + GP_REG_FIRST },                                    \
 525   { "%18",      18 + GP_REG_FIRST },                                    \
 526   { "%19",      19 + GP_REG_FIRST },                                    \
 527   { "%20",      20 + GP_REG_FIRST },                                    \
 528   { "%21",      21 + GP_REG_FIRST },                                    \
 529   { "%22",      22 + GP_REG_FIRST },                                    \
 530   { "%23",      23 + GP_REG_FIRST },                                    \
 531   { "%24",      24 + GP_REG_FIRST },                                    \
 532   { "%25",      25 + GP_REG_FIRST },                                    \
 533   { "%26",      26 + GP_REG_FIRST },                                    \
 534   { "%27",      27 + GP_REG_FIRST },                                    \
 535   { "%28",      28 + GP_REG_FIRST },                                    \
 536   { "%29",      29 + GP_REG_FIRST },                                    \
 537   { "%30",      27 + GP_REG_FIRST },                                    \
 538   { "%31",      31 + GP_REG_FIRST },                                    \
 539   { "%rap",     32 + GP_REG_FIRST },                                    \
 540 }
 541
 542 /* Check if the current insn needs a nop in front of it
 543    because of load delays, and also update the delay slot statistics.  */
 544
 545 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 546   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 547
 548 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 549 do                                                                      \
 550   {                                                                     \
 551     fputs ("\n", STREAM);                                               \
 552   }                                                                     \
 553 while (0)
 554
 555 #define LOCAL_LABEL_PREFIX      "$"
 556
 557 #define USER_LABEL_PREFIX       ""
 558
 559 \f
 560 /* Output of dispatch tables.  */
 561
 562 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 563   do                                                                    \
 564     {                                                                   \
 565       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 566                Pmode == DImode ? ".dword" : ".word",                    \
 567                LOCAL_LABEL_PREFIX, VALUE);                              \
 568     }                                                                   \
 569   while (0)
 570
 571 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 572   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 573            Pmode == DImode ? ".dword" : ".word",                        \
 574            LOCAL_LABEL_PREFIX,                                          \
 575            VALUE)
 576
 577 \f
 578 /* Assembler Commands for Alignment.  */
 579
 580 #undef ASM_OUTPUT_SKIP
 581 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 582   fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",      \
 583            (unsigned HOST_WIDE_INT)(SIZE))
 584
 585 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 586   if ((LOG) != 0)                                                       \
 587     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 588
 589 \f
 590 /* Macros Affecting all Debug Formats.  */
 591
 592 #define DEBUGGER_AUTO_OFFSET(X)  \
 593   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 594
 595 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 596   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 597
 598 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 599
 600 #define DWARF2_DEBUGGING_INFO 1
 601
 602 \f
 603 /* Miscellaneous Parameters.  */
 604
 605 #define CASE_VECTOR_MODE SImode
 606
 607 #define WORD_REGISTER_OPERATIONS
 608
 609 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 610
 611 #define MOVE_MAX 4
 612
 613 #define MAX_MOVE_MAX 8
 614
 615 #define SHIFT_COUNT_TRUNCATED 1
 616
 617 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 618
 619 #define STORE_FLAG_VALUE 1
 620
 621 #define Pmode SImode
 622
 623 #define FUNCTION_MODE SImode
 624
 625 /* Standard GCC variables that we reference.  */
 626
 627 extern char     call_used_regs[];
 628
 629 /* IQ2000 external variables defined in iq2000.c.  */
 630
 631 /* Comparison type.  */
 632 enum cmp_type
 633 {
 634   CMP_SI,                               /* Compare four byte integers.  */
 635   CMP_DI,                               /* Compare eight byte integers.  */
 636   CMP_SF,                               /* Compare single precision floats.  */
 637   CMP_DF,                               /* Compare double precision floats.  */
 638   CMP_MAX                               /* Max comparison type.  */
 639 };
 640
 641 /* Types of delay slot.  */
 642 enum delay_type
 643 {
 644   DELAY_NONE,                           /* No delay slot.  */
 645   DELAY_LOAD,                           /* Load from memory delay.  */
 646   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 647 };
 648
 649 /* Which processor to schedule for.  */
 650
 651 enum processor_type
 652 {
 653   PROCESSOR_DEFAULT,
 654   PROCESSOR_IQ2000,
 655   PROCESSOR_IQ10
 656 };
 657
 658 /* Recast the cpu class to be the cpu attribute.  */
 659 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 660
 661 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 662 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 663
 664 \f
 665 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 666
 667 /* Macros to decide whether certain features are available or not,
 668    depending on the instruction set architecture level.  */
 669
 670 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 671
 672 /* ISA has branch likely instructions.  */
 673 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 674
 675 \f
 676 #undef ASM_SPEC
 677
 678 \f
 679 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 680 #define DWARF_FRAME_REGNUM(REG)        (REG)
 681
 682 /* The DWARF 2 CFA column which tracks the return address.  */
 683 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
 684
 685 /* Describe how we implement __builtin_eh_return.  */
 686 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 687
 688 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 689    location used to store the amount to adjust the stack.  This is
 690    usually a register that is available from end of the function's body
 691    to the end of the epilogue. Thus, this cannot be a register used as a
 692    temporary by the epilogue.
 693
 694    This must be an integer register.  */
 695 #define EH_RETURN_STACKADJ_REGNO        3
 696 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 697
 698 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 699    location used to store the address the processor should jump to
 700    catch exception.  This is usually a registers that is available from
 701    end of the function's body to the end of the epilogue. Thus, this
 702    cannot be a register used as a temporary by the epilogue.
 703
 704    This must be an address register.  */
 705 #define EH_RETURN_HANDLER_REGNO         26
 706 #define EH_RETURN_HANDLER_RTX           \
 707         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 708
 709 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 710 #define DWARF_CIE_DATA_ALIGNMENT 4
 711
 712 /* For IQ2000, width of a floating point register.  */
 713 #define UNITS_PER_FPREG 4
 714
 715 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 716
 717 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 718
 719 /* Internal macros to classify a register number as to whether it's a
 720    general purpose register, a floating point register, a
 721    multiply/divide register, or a status register.  */
 722
 723 #define GP_REG_FIRST 0
 724 #define GP_REG_LAST  31
 725 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 726
 727 #define RAP_REG_NUM   32
 728 #define AT_REGNUM       (GP_REG_FIRST + 1)
 729
 730 #define GP_REG_P(REGNO) \
 731   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 732
 733 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 734    is larger than 32K bytes.  These registers must come from the
 735    scratch register set, and not used for passing and returning
 736    arguments and any other information used in the calling sequence.  */
 737
 738 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
 739 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
 740
 741 /* This macro is used later on in the file.  */
 742 #define GR_REG_CLASS_P(CLASS)                                           \
 743   ((CLASS) == GR_REGS)
 744
 745 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
 746 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
 747
 748 /* Certain machines have the property that some registers cannot be
 749    copied to some other registers without using memory.  Define this
 750    macro on those machines to be a C expression that is nonzero if
 751    objects of mode MODE in registers of CLASS1 can only be copied to
 752    registers of class CLASS2 by storing a register of CLASS1 into
 753    memory and loading that memory location into a register of CLASS2.
 754
 755    Do not define this macro if its value would always be zero.  */
 756
 757 /* Return the maximum number of consecutive registers
 758    needed to represent mode MODE in a register of class CLASS.  */
 759
 760 #define CLASS_UNITS(mode, size)                                         \
 761   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
 762
 763 /* If defined, gives a class of registers that cannot be used as the
 764    operand of a SUBREG that changes the mode of the object illegally.  */
 765
 766 #define CLASS_CANNOT_CHANGE_MODE 0
 767
 768 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
 769
 770 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
 771   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
 772
 773 /* Make sure 4 words are always allocated on the stack.  */
 774
 775 #ifndef STACK_ARGS_ADJUST
 776 #define STACK_ARGS_ADJUST(SIZE)                                         \
 777   {                                                                     \
 778     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
 779       SIZE.constant = 4 * UNITS_PER_WORD;                               \
 780   }
 781 #endif
 782
 783 \f
 784 /* Symbolic macros for the registers used to return integer and floating
 785    point values.  */
 786
 787 #define GP_RETURN (GP_REG_FIRST + 2)
 788
 789 /* Symbolic macros for the first/last argument registers.  */
 790
 791 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
 792 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
 793
 794 #define MAX_ARGS_IN_REGISTERS   8
 795
 796 \f
 797 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
 798
 799 #define MUST_SAVE_REGISTER(regno) \
 800   ((df_regs_ever_live_p (regno) && !call_used_regs[regno])              \
 801   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
 802    || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
 803
 804 /* ALIGN FRAMES on double word boundaries */
 805 #ifndef IQ2000_STACK_ALIGN
 806 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
 807 #endif
 808
 809 \f
 810 /* These assume that REGNO is a hard or pseudo reg number.
 811    They give nonzero only if REGNO is a hard reg of the suitable class
 812    or a pseudo reg currently allocated to a suitable hard reg.
 813    These definitions are NOT overridden anywhere.  */
 814
 815 #define BASE_REG_P(regno, mode)                                 \
 816   (GP_REG_P (regno))
 817
 818 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
 819   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
 820              (mode))
 821
 822 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
 823   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
 824
 825 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
 826   GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode))
 827
 828 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 829    and check its validity for a certain class.
 830    We have two alternate definitions for each of them.
 831    The usual definition accepts all pseudo regs; the other rejects them all.
 832    The symbol REG_OK_STRICT causes the latter definition to be used.
 833
 834    Most source files want to accept pseudo regs in the hope that
 835    they will get allocated to the class that the insn wants them to be in.
 836    Some source files that are used after register allocation
 837    need to be strict.  */
 838
 839 #ifndef REG_OK_STRICT
 840 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 841   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
 842 #else
 843 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 844   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
 845 #endif
 846
 847 #if 1
 848 #define GO_PRINTF(x)    fprintf (stderr, (x))
 849 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
 850 #define GO_DEBUG_RTX(x) debug_rtx (x)
 851
 852 #else
 853 #define GO_PRINTF(x)
 854 #define GO_PRINTF2(x,y)
 855 #define GO_DEBUG_RTX(x)
 856 #endif
 857
 858 /* If defined, modifies the length assigned to instruction INSN as a
 859    function of the context in which it is used.  LENGTH is an lvalue
 860    that contains the initially computed length of the insn and should
 861    be updated with the correct length of the insn.  */
 862 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
 863   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
 864
 865 \f
 866
 867
 868 /* How to tell the debugger about changes of source files.  */
 869
 870 #ifndef SET_FILE_NUMBER
 871 #define SET_FILE_NUMBER() ++ num_source_filenames
 872 #endif
 873
 874 /* This is how to output a note the debugger telling it the line number
 875    to which the following sequence of instructions corresponds.  */
 876
 877 #ifndef LABEL_AFTER_LOC
 878 #define LABEL_AFTER_LOC(STREAM)
 879 #endif
 880
 881 \f
 882 /* Default to -G 8 */
 883 #ifndef IQ2000_DEFAULT_GVALUE
 884 #define IQ2000_DEFAULT_GVALUE 8
 885 #endif
 886
 887 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
 888
 889 \f
 890 /* The target cpu for optimization and scheduling.  */
 891 extern enum processor_type iq2000_tune;
 892
 893 /* Which instruction set architecture to use.  */
 894 extern int iq2000_isa;
 895
 896 enum iq2000_builtins
 897 {
 898   IQ2000_BUILTIN_ADO16,
 899   IQ2000_BUILTIN_CFC0,
 900   IQ2000_BUILTIN_CFC1,
 901   IQ2000_BUILTIN_CFC2,
 902   IQ2000_BUILTIN_CFC3,
 903   IQ2000_BUILTIN_CHKHDR,
 904   IQ2000_BUILTIN_CTC0,
 905   IQ2000_BUILTIN_CTC1,
 906   IQ2000_BUILTIN_CTC2,
 907   IQ2000_BUILTIN_CTC3,
 908   IQ2000_BUILTIN_LU,
 909   IQ2000_BUILTIN_LUC32L,
 910   IQ2000_BUILTIN_LUC64,
 911   IQ2000_BUILTIN_LUC64L,
 912   IQ2000_BUILTIN_LUK,
 913   IQ2000_BUILTIN_LULCK,
 914   IQ2000_BUILTIN_LUM32,
 915   IQ2000_BUILTIN_LUM32L,
 916   IQ2000_BUILTIN_LUM64,
 917   IQ2000_BUILTIN_LUM64L,
 918   IQ2000_BUILTIN_LUR,
 919   IQ2000_BUILTIN_LURL,
 920   IQ2000_BUILTIN_MFC0,
 921   IQ2000_BUILTIN_MFC1,
 922   IQ2000_BUILTIN_MFC2,
 923   IQ2000_BUILTIN_MFC3,
 924   IQ2000_BUILTIN_MRGB,
 925   IQ2000_BUILTIN_MTC0,
 926   IQ2000_BUILTIN_MTC1,
 927   IQ2000_BUILTIN_MTC2,
 928   IQ2000_BUILTIN_MTC3,
 929   IQ2000_BUILTIN_PKRL,
 930   IQ2000_BUILTIN_RAM,
 931   IQ2000_BUILTIN_RB,
 932   IQ2000_BUILTIN_RX,
 933   IQ2000_BUILTIN_SRRD,
 934   IQ2000_BUILTIN_SRRDL,
 935   IQ2000_BUILTIN_SRULC,
 936   IQ2000_BUILTIN_SRULCK,
 937   IQ2000_BUILTIN_SRWR,
 938   IQ2000_BUILTIN_SRWRU,
 939   IQ2000_BUILTIN_TRAPQF,
 940   IQ2000_BUILTIN_TRAPQFL,
 941   IQ2000_BUILTIN_TRAPQN,
 942   IQ2000_BUILTIN_TRAPQNE,
 943   IQ2000_BUILTIN_TRAPRE,
 944   IQ2000_BUILTIN_TRAPREL,
 945   IQ2000_BUILTIN_WB,
 946   IQ2000_BUILTIN_WBR,
 947   IQ2000_BUILTIN_WBU,
 948   IQ2000_BUILTIN_WX,
 949   IQ2000_BUILTIN_SYSCALL
 950 };