RISC-V: Fix overlap group incorrect overlap on v0

RISC-V: Fix overlap group incorrect overlap on v0

In serious high register pressure case (appended in this patch):

We see vluxei8.v       v0,(s1),v1,v0.t which is not allowed.
Since according to RVV ISA:

+;; The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0),
+;; unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction.

Such case doesn't have spillings, however, we expect such case should be spilled and reload data.

The rootcause is I made a mistake in previous patch on matching dest operand and mask operand constraints:

dest: "=vr"
mask: "vmWc1"

After this patch:

dest: "vd,vr"
mask: "vm,Wc1"

make EEW widening pattern are same as other instruction patterns.

	PR target/112431

gcc/ChangeLog:

	* config/riscv/vector.md: Fix incorrect overlap in v0.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-34.c: New test.