RISC-V: Add xfail test case for highpart overlap of vext.vf
commitf952745943c2e9fbb2df32d2f2b037669d3fc50f
authorPan Li <pan2.li@intel.com>
Wed, 24 Apr 2024 02:39:25 +0000 (24 10:39 +0800)
committerPan Li <pan2.li@intel.com>
Wed, 24 Apr 2024 06:55:06 +0000 (24 14:55 +0800)
treeb95f639013262e2cfae9601f9f662db3eb7e74aa
parent8bcefc2d5fb0d8f8f9671fd830132b4e655c44b4
RISC-V: Add xfail test case for highpart overlap of vext.vf

We reverted below patch for register group overlap, add the related
insn test and mark it as xfail.  And we will remove the xfail
after we support the register overlap in GCC-15.

62685890d88 RISC-V: Support highpart overlap for vext.vf

The below test suites are passed for this patch
* The rv64gcv fully regression test with isl build.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Adjust asm
check cond.
* gcc.target/riscv/rvv/base/pr112431-4.c: New test.
* gcc.target/riscv/rvv/base/pr112431-5.c: New test.
* gcc.target/riscv/rvv/base/pr112431-6.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c