| commit | f6ff841bc8dd87ce364deb217dc6d1ec5dc31de8 | |
| author | Richard Earnshaw <rearnsha@arm.com> | |
| Fri, 18 Oct 2019 19:03:11 +0000 (18 19:03 +0000) | ||
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | |
| Fri, 18 Oct 2019 19:03:11 +0000 (18 19:03 +0000) | ||
| tree | f7fb49934234207a982110dc635c074c39ae023e | treesnapshot (tar.gz zip) |
| parent | 24d28a8778f4c7efcebea6c785806082eeacf9fe | commitdiff |
[arm] Implement negscc using SBC when appropriate.
When the carry flag is appropriately set by a comprison, negscc
patterns can expand into a simple SBC of a register with itself. This
means we can convert two conditional instructions into a single
non-conditional instruction. Furthermore, in Thumb2 we can avoid the
need for an IT instruction as well. This patch also fixes the remaining
testcase that we initially XFAILed in the first patch of this series.
gcc:
* config/arm/arm.md (negscc_borrow): New pattern.
(mov_negscc): Don't split if the insn would match negscc_borrow.
* config/arm/thumb2.md (thumb2_mov_negscc): Likewise.
(thumb2_mov_negscc_strict_it): Likewise.
testsuite:
* gcc.target/arm/negdi-3.c: Remove XFAIL markers.
From-SVN: r277175
When the carry flag is appropriately set by a comprison, negscc
patterns can expand into a simple SBC of a register with itself. This
means we can convert two conditional instructions into a single
non-conditional instruction. Furthermore, in Thumb2 we can avoid the
need for an IT instruction as well. This patch also fixes the remaining
testcase that we initially XFAILed in the first patch of this series.
gcc:
* config/arm/arm.md (negscc_borrow): New pattern.
(mov_negscc): Don't split if the insn would match negscc_borrow.
* config/arm/thumb2.md (thumb2_mov_negscc): Likewise.
(thumb2_mov_negscc_strict_it): Likewise.
testsuite:
* gcc.target/arm/negdi-3.c: Remove XFAIL markers.
From-SVN: r277175